From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8D0F8C433FE for ; Wed, 26 Oct 2022 14:32:02 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230522AbiJZOcB (ORCPT ); Wed, 26 Oct 2022 10:32:01 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40868 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233520AbiJZOcA (ORCPT ); Wed, 26 Oct 2022 10:32:00 -0400 Received: from mail-pf1-x444.google.com (mail-pf1-x444.google.com [IPv6:2607:f8b0:4864:20::444]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4F452FF25F for ; Wed, 26 Oct 2022 07:32:00 -0700 (PDT) Received: by mail-pf1-x444.google.com with SMTP id f140so15475200pfa.1 for ; Wed, 26 Oct 2022 07:32:00 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=in-reply-to:content-transfer-encoding:content-disposition :mime-version:references:message-id:subject:cc:to:from:date:from:to :cc:subject:date:message-id:reply-to; bh=ntZLp7OVSmLd/Z9tfPE0dtDYBArbeZCUDytlptrIcAY=; b=ukHhbkDC6DOXtfdPDryQPu2tSw0ZRs83cKVWZ1T5QXY6hOWZuIKG4tFEDhnrEGIqr6 b8brR1LtEL7CGvOv9VhxOKoEhJTNtJyPa+xHn2D7YouuG6DMAqhZ4pkm64MhuXtRuUgX e8vttbocs3MMmD/la2C5Wopob4hq4+kHWAfPImoyEIUM59ikC3qv7b1ZktG2xI+k8IfN 8hw8AKxpHRsrMic7J92rzkeWFjlHeY3pBgZh1eM1+WikcwbbQyEZXez5YJqSpX2GnXzN j7Naa5ijVBqHfsib2FatH1Lj9MBrnQKY86pV6xaDtF7G7wWBwGbhTswoWIezU3TmLtr9 101w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=in-reply-to:content-transfer-encoding:content-disposition :mime-version:references:message-id:subject:cc:to:from:date :x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=ntZLp7OVSmLd/Z9tfPE0dtDYBArbeZCUDytlptrIcAY=; b=N/16AMPAe3RC42lbEwabJ5J8SybCApbnL4x7RLhob5oikNwRGIvt3FDHKbklsxL+ki 5LeOebElOijGWt0o9wen5e54xTdEcuRON2NxcsHfgvG8nOpaSYY2/m7L//urAjVufKDt lOoXa1eec0oubhjK6oVn43UFg+E6PRoErusRWv3DzrDdPcwBsFElWha9bn+UWW1q0pHs XopiyzI7Sl1QDUhxNdnT9SE/VrqTGndVOQnz8KnKoU0z44O3Bjx0VSi9jtj0hIt9zIt8 1JhKCl31RtoFC87z5bXqLhFHpxsRsfi+UDjIZgnUtVtAlQ3Jaf0e3AfGIuvefbc7ugZt YlpA== X-Gm-Message-State: ACrzQf3l/66BYpQwQOt/J0UH/aqrnQbw1ytlcpAddsh/YoGyMTfbhNzx 1ox6S71qVY9nG6EQPYki4P+u X-Google-Smtp-Source: AMsMyM6SeK6JRTsCgrvuTLYxTBm7A+1WSmXUpZygONc4JZRDonnJRjpbmV0zfxWnha7urSXsWyrXFQ== X-Received: by 2002:a63:5410:0:b0:46f:2a22:13ea with SMTP id i16-20020a635410000000b0046f2a2213eamr8947593pgb.487.1666794719788; Wed, 26 Oct 2022 07:31:59 -0700 (PDT) Received: from thinkpad ([117.193.208.123]) by smtp.gmail.com with ESMTPSA id ij28-20020a170902ab5c00b0017f9147983asm2982657plb.175.2022.10.26.07.31.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 26 Oct 2022 07:31:58 -0700 (PDT) Date: Wed, 26 Oct 2022 20:01:52 +0530 From: Manivannan Sadhasivam To: Dmitry Baryshkov Cc: vkoul@kernel.org, andersson@kernel.org, kishon@ti.com, linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH] phy: qcom-qmp-pcie: Fix the SM8450 PCS registers Message-ID: <20221026143152.GA93939@thinkpad> References: <20220910063857.17372-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org On Wed, Sep 21, 2022 at 04:06:10PM +0300, Dmitry Baryshkov wrote: > On 10/09/2022 09:38, Manivannan Sadhasivam wrote: > > In the PCS region, registers QPHY_V5_PCS_EQ_CONFIG4 and > > QPHY_V5_PCS_EQ_CONFIG5 should be used instead of QPHY_V5_PCS_EQ_CONFIG2 > > and QPHY_V5_PCS_EQ_CONFIG3. > > > > This causes high latency when ASPM is enabled, so fix it! > > I have checked against vendor's tree [1]. The registers in question have > offsets 0x01c0f3e0 / 0x01c0f3e4. The sm8450.dtsi uses 0x1c0f200 as the PCS > region base for the PCIe PHY1. Thus the correct offsets for the table are > 0x1e0/0x1e4. > > There might be a mistake in the name of the register, but the address > corresponds to the address in the vendor's tree. > Right. Only the register name is wrong and I've got the offset wrong here. But the actual latency issue is fixed by clearing the QPHY_V4_PCS_PCIE_PRESET_P10_POST register in pcs_misc register space. I will check with Qcom on this behaviour and post v2 with register name fix. Thanks, Mani > [1] https://github.com/MiCode/kernel_devicetree/blob/zeus-s-oss/qcom/waipio-pcie.dtsi#L520 > > > > > Fixes: 2c91bf6bf290 ("phy: qcom-qmp: Add SM8450 PCIe1 PHY support") > > Signed-off-by: Manivannan Sadhasivam > > --- > > drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 4 ++-- > > drivers/phy/qualcomm/phy-qcom-qmp-pcs-v5.h | 4 ++-- > > 2 files changed, 4 insertions(+), 4 deletions(-) > > > > diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c > > index 4648467d5cac..b508903d77d0 100644 > > --- a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c > > +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c > > @@ -1332,8 +1332,8 @@ static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_rx_tbl[] = { > > }; > > static const struct qmp_phy_init_tbl sm8450_qmp_gen4x2_pcie_pcs_tbl[] = { > > - QMP_PHY_INIT_CFG(QPHY_V5_PCS_EQ_CONFIG2, 0x16), > > - QMP_PHY_INIT_CFG(QPHY_V5_PCS_EQ_CONFIG3, 0x22), > > + QMP_PHY_INIT_CFG(QPHY_V5_PCS_EQ_CONFIG4, 0x16), > > + QMP_PHY_INIT_CFG(QPHY_V5_PCS_EQ_CONFIG5, 0x22), > > QMP_PHY_INIT_CFG(QPHY_V5_PCS_G3S2_PRE_GAIN, 0x2e), > > QMP_PHY_INIT_CFG(QPHY_V5_PCS_RX_SIGDET_LVL, 0x99), > > }; > > diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-v5.h b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-v5.h > > index 61a44519f969..cca6455ec98c 100644 > > --- a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-v5.h > > +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-v5.h > > @@ -11,7 +11,7 @@ > > #define QPHY_V5_PCS_G3S2_PRE_GAIN 0x170 > > #define QPHY_V5_PCS_RX_SIGDET_LVL 0x188 > > #define QPHY_V5_PCS_RATE_SLEW_CNTRL1 0x198 > > -#define QPHY_V5_PCS_EQ_CONFIG2 0x1e0 > > -#define QPHY_V5_PCS_EQ_CONFIG3 0x1e4 > > +#define QPHY_V5_PCS_EQ_CONFIG4 0x2e0 > > +#define QPHY_V5_PCS_EQ_CONFIG5 0x2e4 > > #endif > > -- > With best wishes > Dmitry > -- மணிவண்ணன் சதாசிவம்