[PATCH RFC 01/15] dt-bindings: mfd: Split out Qcom RPM MSG RAM

[Konrad Dybcio <konrad.dybcio@linaro.org>]

The RPM Message RAM is a part of the RPM low-power core's RAM that's a
MMIO-mapped region from the main ARM CPUs' POV. It contains sleep stats
divided per "RPM master" (ARM cluster, *DSP, ...), an interrupt controller
(MPM) that's vital in the low-power mode entry/exit sequence, as it
signals the readiness to enter sleep, replays the interrupts after a total
power collapse recovery and is able to receive external interrupts from
other IPs (like the PMIC, TSENS and USB) on the SoC to initiate a wakeup
sequence.

On top of that, it contains some regions that are (ab)used by SMEM (by
design!), but we're not completely sure what ranges are r/w to/from.
This would probably need to be determined on a SoC-by-SoC - or even worse
- firmware-by-firmware basis, but since this region is quite "wild west"
by design (it may be accessed and altered in one form or another by all of
the subsystems at the same time) this shouldn't really worry us..

Split out the bindings and re-model it as a simple-mfd to allow for better
representation of the partitions within and allow child devices (MPM,
master sleep stats - coming soon).

Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
---
 .../devicetree/bindings/mfd/qcom,rpm-msg-ram.yaml  | 82 ++++++++++++++++++++++
 Documentation/devicetree/bindings/sram/sram.yaml   |  2 -
 2 files changed, 82 insertions(+), 2 deletions(-)

diff --git a/Documentation/devicetree/bindings/mfd/qcom,rpm-msg-ram.yaml b/Documentation/devicetree/bindings/mfd/qcom,rpm-msg-ram.yaml
new file mode 100644
index 000000000000..b1fee2b2d923
--- /dev/null
+++ b/Documentation/devicetree/bindings/mfd/qcom,rpm-msg-ram.yaml
@@ -0,0 +1,82 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/mfd/qcom,rpm-msg-ram.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm RPM Message RAM
+
+maintainers:
+  - Konrad Dybcio <konrad.dybcio@linaro.org>
+
+description:
+  Part of the remote Resource Power Manager (RPM) core's RAM is exposed to
+  the main ARM cores as a MMIO-mapped device and referred to as the RPM
+  Message RAM. It contains per-RPM-master sleep statistics, an interrupt
+  controller (MPM) that's capable of replaying interrupts after a total power
+  collapse of a given master and some memory for mailbox-like functionality.
+  An RPM master is any remote core on the SoC, including APSS (the main ARM
+  clusters), ADSP etc., depending on the platform capabilities.
+
+properties:
+  compatible:
+    items:
+      - const: qcom,rpm-msg-ram
+      - const: simple-mfd
+
+  reg:
+    maxItems: 1
+
+  # The RPM message RAM should be <=0x7000-long so 1 cell is all it needs.
+  '#address-cells':
+    const: 1
+
+  '#size-cells':
+    const: 1
+
+  ranges: true
+
+required:
+  - compatible
+  - reg
+
+patternProperties:
+  # The MPM comes at fixed offsets: 0x1b8 on MSM8996 and later, 0x1d0 before it
+  "^interrupt-controller@(1d0|1b8)":
+    type: object
+    oneOf:
+      - $ref: /schemas/interrupt-controller/qcom,mpm.yaml#
+
+additionalProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/interrupt-controller/arm-gic.h>
+    #include <dt-bindings/mailbox/qcom-ipcc.h>
+
+    sram@45f0000 {
+        compatible = "qcom,rpm-msg-ram", "simple-mfd";
+        reg = <0x045f0000 0x7000>;
+        #address-cells = <1>;
+        #size-cells = <1>;
+        ranges = <0 0x045f0000 0x7000>;
+
+        wakegic: interrupt-controller@1b8 {
+            compatible = "qcom,mpm";
+            reg = <0x1b8 0x48>;
+            interrupts = <GIC_SPI 197 IRQ_TYPE_EDGE_RISING>;
+            mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_SMP2P>;
+            interrupt-controller;
+            #interrupt-cells = <2>;
+            #power-domain-cells = <0>;
+            interrupt-parent = <&intc>;
+            qcom,mpm-pin-count = <96>;
+            qcom,mpm-pin-map = <5 296>,  /* Soundwire wake_irq */
+                               <12 422>, /* DWC3 ss_phy_irq */
+                               <86 183>, /* MPM wake, SPMI */
+                               <89 314>, /* TSENS0 0C */
+                               <90 315>, /* TSENS1 0C */
+                               <93 164>, /* DWC3 dm_hs_phy_irq */
+                               <94 165>; /* DWC3 dp_hs_phy_irq */
+        };
+    };
diff --git a/Documentation/devicetree/bindings/sram/sram.yaml b/Documentation/devicetree/bindings/sram/sram.yaml
index 993430be355b..2e9e57b2602f 100644
--- a/Documentation/devicetree/bindings/sram/sram.yaml
+++ b/Documentation/devicetree/bindings/sram/sram.yaml
@@ -34,7 +34,6 @@ properties:
         - nvidia,tegra186-sysram
         - nvidia,tegra194-sysram
         - nvidia,tegra234-sysram
-        - qcom,rpm-msg-ram
         - rockchip,rk3288-pmu-sram
 
   reg:
@@ -141,7 +140,6 @@ if:
       compatible:
         contains:
           enum:
-            - qcom,rpm-msg-ram
             - rockchip,rk3288-pmu-sram
 then:
   required:

-- 
2.39.2