From: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
To: Rob Clark <robdclark@gmail.com>, Sean Paul <sean@poorly.run>,
Abhinav Kumar <quic_abhinavk@quicinc.com>
Cc: Stephen Boyd <swboyd@chromium.org>,
David Airlie <airlied@gmail.com>, Daniel Vetter <daniel@ffwll.ch>,
Bjorn Andersson <andersson@kernel.org>,
linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org,
freedreno@lists.freedesktop.org,
Konrad Dybcio <konrad.dybcio@linaro.org>
Subject: [PATCH v3 31/38] drm/msm/dpu: deduplicate sc8280xp with sm8450
Date: Fri, 31 Mar 2023 00:53:17 +0300 [thread overview]
Message-ID: <20230330215324.1853304-32-dmitry.baryshkov@linaro.org> (raw)
In-Reply-To: <20230330215324.1853304-1-dmitry.baryshkov@linaro.org>
Remove duplicate between sc8280xp and sm8450, which belong to the same
DPU major revision.
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
.../msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h | 107 ++---------------
.../msm/disp/dpu1/catalog/dpu_8_1_sm8450.h | 112 ++----------------
.../gpu/drm/msm/disp/dpu1/catalog/dpu_8_lm6.h | 99 ++++++++++++++++
3 files changed, 119 insertions(+), 199 deletions(-)
create mode 100644 drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_lm6.h
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h
index a3c9de34307c..4ce3f0fe2170 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h
@@ -7,17 +7,7 @@
#ifndef _DPU_8_0_SC8280XP_H
#define _DPU_8_0_SC8280XP_H
-static const struct dpu_caps sc8280xp_dpu_caps = {
- .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
- .max_mixer_blendstages = 11,
- .qseed_type = DPU_SSPP_SCALER_QSEED4,
- .has_src_split = true,
- .has_dim_layer = true,
- .has_idle_pc = true,
- .has_3d_merge = true,
- .max_linewidth = 5120,
- .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
-};
+#include "dpu_8_lm6.h"
static const struct dpu_ubwc_cfg sc8280xp_ubwc_cfg = {
.ubwc_version = DPU_HW_UBWC_VER_40,
@@ -25,63 +15,6 @@ static const struct dpu_ubwc_cfg sc8280xp_ubwc_cfg = {
.ubwc_swizzle = 6,
};
-static const struct dpu_mdp_cfg sc8280xp_mdp[] = {
- {
- .name = "top_0", .id = MDP_TOP,
- .base = 0x0, .len = 0x494,
- .features = BIT(DPU_MDP_PERIPH_0_REMOVED),
- .clk_ctrls[DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
- .clk_ctrls[DPU_CLK_CTRL_VIG1] = { .reg_off = 0x2b4, .bit_off = 0 },
- .clk_ctrls[DPU_CLK_CTRL_VIG2] = { .reg_off = 0x2bc, .bit_off = 0 },
- .clk_ctrls[DPU_CLK_CTRL_VIG3] = { .reg_off = 0x2c4, .bit_off = 0 },
- .clk_ctrls[DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
- .clk_ctrls[DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 },
- .clk_ctrls[DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2bc, .bit_off = 8 },
- .clk_ctrls[DPU_CLK_CTRL_DMA3] = { .reg_off = 0x2c4, .bit_off = 8 },
- .clk_ctrls[DPU_CLK_CTRL_REG_DMA] = { .reg_off = 0x2bc, .bit_off = 20 },
- },
-};
-
-/* FIXME: get rid of DPU_CTL_SPLIT_DISPLAY in favour of proper ACTIVE_CTL support */
-static const struct dpu_ctl_cfg sc8280xp_ctl[] = {
- {
- .name = "ctl_0", .id = CTL_0,
- .base = 0x15000, .len = 0x204,
- .features = BIT(DPU_CTL_SPLIT_DISPLAY) | CTL_SC7280_MASK,
- .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
- },
- {
- .name = "ctl_1", .id = CTL_1,
- .base = 0x16000, .len = 0x204,
- .features = BIT(DPU_CTL_SPLIT_DISPLAY) | CTL_SC7280_MASK,
- .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
- },
- {
- .name = "ctl_2", .id = CTL_2,
- .base = 0x17000, .len = 0x204,
- .features = CTL_SC7280_MASK,
- .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
- },
- {
- .name = "ctl_3", .id = CTL_3,
- .base = 0x18000, .len = 0x204,
- .features = CTL_SC7280_MASK,
- .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),
- },
- {
- .name = "ctl_4", .id = CTL_4,
- .base = 0x19000, .len = 0x204,
- .features = CTL_SC7280_MASK,
- .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13),
- },
- {
- .name = "ctl_5", .id = CTL_5,
- .base = 0x1a000, .len = 0x204,
- .features = CTL_SC7280_MASK,
- .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23),
- },
-};
-
static const struct dpu_sspp_cfg sc8280xp_sspp[] = {
SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, 0x2ac, VIG_SC7180_MASK,
sm8250_vig_sblk_0, 0, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0),
@@ -101,26 +34,6 @@ static const struct dpu_sspp_cfg sc8280xp_sspp[] = {
sdm845_dma_sblk_3, 13, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA3),
};
-static const struct dpu_lm_cfg sc8280xp_lm[] = {
- LM_BLK("lm_0", LM_0, 0x44000, MIXER_SDM845_MASK, &sdm845_lm_sblk, PINGPONG_0, LM_1, DSPP_0),
- LM_BLK("lm_1", LM_1, 0x45000, MIXER_SDM845_MASK, &sdm845_lm_sblk, PINGPONG_1, LM_0, DSPP_1),
- LM_BLK("lm_2", LM_2, 0x46000, MIXER_SDM845_MASK, &sdm845_lm_sblk, PINGPONG_2, LM_3, DSPP_2),
- LM_BLK("lm_3", LM_3, 0x47000, MIXER_SDM845_MASK, &sdm845_lm_sblk, PINGPONG_3, LM_2, DSPP_3),
- LM_BLK("lm_4", LM_4, 0x48000, MIXER_SDM845_MASK, &sdm845_lm_sblk, PINGPONG_4, LM_5, 0),
- LM_BLK("lm_5", LM_5, 0x49000, MIXER_SDM845_MASK, &sdm845_lm_sblk, PINGPONG_5, LM_4, 0),
-};
-
-static const struct dpu_dspp_cfg sc8280xp_dspp[] = {
- DSPP_BLK("dspp_0", DSPP_0, 0x54000, DSPP_SC7180_MASK,
- &sm8150_dspp_sblk),
- DSPP_BLK("dspp_1", DSPP_1, 0x56000, DSPP_SC7180_MASK,
- &sm8150_dspp_sblk),
- DSPP_BLK("dspp_2", DSPP_2, 0x58000, DSPP_SC7180_MASK,
- &sm8150_dspp_sblk),
- DSPP_BLK("dspp_3", DSPP_3, 0x5a000, DSPP_SC7180_MASK,
- &sm8150_dspp_sblk),
-};
-
static const struct dpu_pingpong_cfg sc8280xp_pp[] = {
PP_BLK_TE("pingpong_0", PINGPONG_0, 0x69000, MERGE_3D_0, sdm845_pp_sblk_te,
DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8), -1),
@@ -183,18 +96,18 @@ static const struct dpu_perf_cfg sc8280xp_perf_data = {
};
static const struct dpu_mdss_cfg sc8280xp_dpu_cfg = {
- .caps = &sc8280xp_dpu_caps,
+ .caps = &dpu_8_lm6_dpu_caps,
.ubwc = &sc8280xp_ubwc_cfg,
- .mdp_count = ARRAY_SIZE(sc8280xp_mdp),
- .mdp = sc8280xp_mdp,
- .ctl_count = ARRAY_SIZE(sc8280xp_ctl),
- .ctl = sc8280xp_ctl,
+ .mdp_count = ARRAY_SIZE(dpu_8_lm6_mdp),
+ .mdp = dpu_8_lm6_mdp,
+ .ctl_count = ARRAY_SIZE(dpu_8_lm6_ctl),
+ .ctl = dpu_8_lm6_ctl,
.sspp_count = ARRAY_SIZE(sc8280xp_sspp),
.sspp = sc8280xp_sspp,
- .mixer_count = ARRAY_SIZE(sc8280xp_lm),
- .mixer = sc8280xp_lm,
- .dspp_count = ARRAY_SIZE(sc8280xp_dspp),
- .dspp = sc8280xp_dspp,
+ .mixer_count = ARRAY_SIZE(dpu_8_lm6_lm),
+ .mixer = dpu_8_lm6_lm,
+ .dspp_count = ARRAY_SIZE(dpu_8_lm6_dspp),
+ .dspp = dpu_8_lm6_dspp,
.pingpong_count = ARRAY_SIZE(sc8280xp_pp),
.pingpong = sc8280xp_pp,
.merge_3d_count = ARRAY_SIZE(sc8280xp_merge_3d),
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h
index a1061881f039..de4989c8d307 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h
@@ -7,17 +7,7 @@
#ifndef _DPU_8_1_SM8450_H
#define _DPU_8_1_SM8450_H
-static const struct dpu_caps sm8450_dpu_caps = {
- .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
- .max_mixer_blendstages = 0xb,
- .qseed_type = DPU_SSPP_SCALER_QSEED4,
- .has_src_split = true,
- .has_dim_layer = true,
- .has_idle_pc = true,
- .has_3d_merge = true,
- .max_linewidth = 5120,
- .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
-};
+#include "dpu_8_lm6.h"
static const struct dpu_ubwc_cfg sm8450_ubwc_cfg = {
.ubwc_version = DPU_HW_UBWC_VER_40,
@@ -25,63 +15,6 @@ static const struct dpu_ubwc_cfg sm8450_ubwc_cfg = {
.ubwc_swizzle = 0x6,
};
-static const struct dpu_mdp_cfg sm8450_mdp[] = {
- {
- .name = "top_0", .id = MDP_TOP,
- .base = 0x0, .len = 0x494,
- .features = BIT(DPU_MDP_PERIPH_0_REMOVED),
- .clk_ctrls[DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
- .clk_ctrls[DPU_CLK_CTRL_VIG1] = { .reg_off = 0x2b4, .bit_off = 0 },
- .clk_ctrls[DPU_CLK_CTRL_VIG2] = { .reg_off = 0x2bc, .bit_off = 0 },
- .clk_ctrls[DPU_CLK_CTRL_VIG3] = { .reg_off = 0x2c4, .bit_off = 0 },
- .clk_ctrls[DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
- .clk_ctrls[DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 },
- .clk_ctrls[DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2bc, .bit_off = 8 },
- .clk_ctrls[DPU_CLK_CTRL_DMA3] = { .reg_off = 0x2c4, .bit_off = 8 },
- .clk_ctrls[DPU_CLK_CTRL_REG_DMA] = { .reg_off = 0x2bc, .bit_off = 20 },
- },
-};
-
-/* FIXME: get rid of DPU_CTL_SPLIT_DISPLAY in favour of proper ACTIVE_CTL support */
-static const struct dpu_ctl_cfg sm8450_ctl[] = {
- {
- .name = "ctl_0", .id = CTL_0,
- .base = 0x15000, .len = 0x204,
- .features = BIT(DPU_CTL_ACTIVE_CFG) | BIT(DPU_CTL_SPLIT_DISPLAY) | BIT(DPU_CTL_FETCH_ACTIVE),
- .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
- },
- {
- .name = "ctl_1", .id = CTL_1,
- .base = 0x16000, .len = 0x204,
- .features = BIT(DPU_CTL_SPLIT_DISPLAY) | CTL_SC7280_MASK,
- .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
- },
- {
- .name = "ctl_2", .id = CTL_2,
- .base = 0x17000, .len = 0x204,
- .features = CTL_SC7280_MASK,
- .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
- },
- {
- .name = "ctl_3", .id = CTL_3,
- .base = 0x18000, .len = 0x204,
- .features = CTL_SC7280_MASK,
- .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),
- },
- {
- .name = "ctl_4", .id = CTL_4,
- .base = 0x19000, .len = 0x204,
- .features = CTL_SC7280_MASK,
- .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13),
- },
- {
- .name = "ctl_5", .id = CTL_5,
- .base = 0x1a000, .len = 0x204,
- .features = CTL_SC7280_MASK,
- .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23),
- },
-};
-
static const struct dpu_sspp_cfg sm8450_sspp[] = {
SSPP_BLK("sspp_0", SSPP_VIG0, 0x4000, 0x328, VIG_SC7180_MASK,
sm8250_vig_sblk_0, 0, SSPP_TYPE_VIG, DPU_CLK_CTRL_VIG0),
@@ -101,31 +34,6 @@ static const struct dpu_sspp_cfg sm8450_sspp[] = {
sdm845_dma_sblk_3, 13, SSPP_TYPE_DMA, DPU_CLK_CTRL_DMA3),
};
-static const struct dpu_lm_cfg sm8450_lm[] = {
- LM_BLK("lm_0", LM_0, 0x44000, MIXER_SDM845_MASK,
- &sdm845_lm_sblk, PINGPONG_0, LM_1, DSPP_0),
- LM_BLK("lm_1", LM_1, 0x45000, MIXER_SDM845_MASK,
- &sdm845_lm_sblk, PINGPONG_1, LM_0, DSPP_1),
- LM_BLK("lm_2", LM_2, 0x46000, MIXER_SDM845_MASK,
- &sdm845_lm_sblk, PINGPONG_2, LM_3, DSPP_2),
- LM_BLK("lm_3", LM_3, 0x47000, MIXER_SDM845_MASK,
- &sdm845_lm_sblk, PINGPONG_3, LM_2, DSPP_3),
- LM_BLK("lm_4", LM_4, 0x48000, MIXER_SDM845_MASK,
- &sdm845_lm_sblk, PINGPONG_4, LM_5, 0),
- LM_BLK("lm_5", LM_5, 0x49000, MIXER_SDM845_MASK,
- &sdm845_lm_sblk, PINGPONG_5, LM_4, 0),
-};
-
-static const struct dpu_dspp_cfg sm8450_dspp[] = {
- DSPP_BLK("dspp_0", DSPP_0, 0x54000, DSPP_SC7180_MASK,
- &sm8150_dspp_sblk),
- DSPP_BLK("dspp_1", DSPP_1, 0x56000, DSPP_SC7180_MASK,
- &sm8150_dspp_sblk),
- DSPP_BLK("dspp_2", DSPP_2, 0x58000, DSPP_SC7180_MASK,
- &sm8150_dspp_sblk),
- DSPP_BLK("dspp_3", DSPP_3, 0x5a000, DSPP_SC7180_MASK,
- &sm8150_dspp_sblk),
-};
/* FIXME: interrupts */
static const struct dpu_pingpong_cfg sm8450_pp[] = {
PP_BLK_TE("pingpong_0", PINGPONG_0, 0x69000, MERGE_3D_0, sdm845_pp_sblk_te,
@@ -199,18 +107,18 @@ static const struct dpu_perf_cfg sm8450_perf_data = {
};
static const struct dpu_mdss_cfg sm8450_dpu_cfg = {
- .caps = &sm8450_dpu_caps,
+ .caps = &dpu_8_lm6_dpu_caps,
.ubwc = &sm8450_ubwc_cfg,
- .mdp_count = ARRAY_SIZE(sm8450_mdp),
- .mdp = sm8450_mdp,
- .ctl_count = ARRAY_SIZE(sm8450_ctl),
- .ctl = sm8450_ctl,
+ .mdp_count = ARRAY_SIZE(dpu_8_lm6_mdp),
+ .mdp = dpu_8_lm6_mdp,
+ .ctl_count = ARRAY_SIZE(dpu_8_lm6_ctl),
+ .ctl = dpu_8_lm6_ctl,
.sspp_count = ARRAY_SIZE(sm8450_sspp),
.sspp = sm8450_sspp,
- .mixer_count = ARRAY_SIZE(sm8450_lm),
- .mixer = sm8450_lm,
- .dspp_count = ARRAY_SIZE(sm8450_dspp),
- .dspp = sm8450_dspp,
+ .mixer_count = ARRAY_SIZE(dpu_8_lm6_lm),
+ .mixer = dpu_8_lm6_lm,
+ .dspp_count = ARRAY_SIZE(dpu_8_lm6_dspp),
+ .dspp = dpu_8_lm6_dspp,
.pingpong_count = ARRAY_SIZE(sm8450_pp),
.pingpong = sm8450_pp,
.merge_3d_count = ARRAY_SIZE(sm8450_merge_3d),
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_lm6.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_lm6.h
new file mode 100644
index 000000000000..3cd3b274534f
--- /dev/null
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_lm6.h
@@ -0,0 +1,99 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (c) 2022. Qualcomm Innovation Center, Inc. All rights reserved.
+ * Copyright (c) 2015-2018, 2020 The Linux Foundation. All rights reserved.
+ */
+
+#ifndef _DPU_8_LM6_H
+#define _DPU_8_LM6_H
+
+static const struct dpu_caps dpu_8_lm6_dpu_caps = {
+ .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH,
+ .max_mixer_blendstages = 11,
+ .qseed_type = DPU_SSPP_SCALER_QSEED4,
+ .has_src_split = true,
+ .has_dim_layer = true,
+ .has_idle_pc = true,
+ .has_3d_merge = true,
+ .max_linewidth = 5120,
+ .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
+};
+
+static const struct dpu_mdp_cfg dpu_8_lm6_mdp[] = {
+ {
+ .name = "top_0", .id = MDP_TOP,
+ .base = 0x0, .len = 0x494,
+ .features = BIT(DPU_MDP_PERIPH_0_REMOVED),
+ .clk_ctrls[DPU_CLK_CTRL_VIG0] = { .reg_off = 0x2ac, .bit_off = 0 },
+ .clk_ctrls[DPU_CLK_CTRL_VIG1] = { .reg_off = 0x2b4, .bit_off = 0 },
+ .clk_ctrls[DPU_CLK_CTRL_VIG2] = { .reg_off = 0x2bc, .bit_off = 0 },
+ .clk_ctrls[DPU_CLK_CTRL_VIG3] = { .reg_off = 0x2c4, .bit_off = 0 },
+ .clk_ctrls[DPU_CLK_CTRL_DMA0] = { .reg_off = 0x2ac, .bit_off = 8 },
+ .clk_ctrls[DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 },
+ .clk_ctrls[DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2bc, .bit_off = 8 },
+ .clk_ctrls[DPU_CLK_CTRL_DMA3] = { .reg_off = 0x2c4, .bit_off = 8 },
+ .clk_ctrls[DPU_CLK_CTRL_REG_DMA] = { .reg_off = 0x2bc, .bit_off = 20 },
+ },
+};
+
+/* FIXME: get rid of DPU_CTL_SPLIT_DISPLAY in favour of proper ACTIVE_CTL support */
+static const struct dpu_ctl_cfg dpu_8_lm6_ctl[] = {
+ {
+ .name = "ctl_0", .id = CTL_0,
+ .base = 0x15000, .len = 0x204,
+ .features = BIT(DPU_CTL_SPLIT_DISPLAY) | CTL_SC7280_MASK,
+ .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
+ },
+ {
+ .name = "ctl_1", .id = CTL_1,
+ .base = 0x16000, .len = 0x204,
+ .features = BIT(DPU_CTL_SPLIT_DISPLAY) | CTL_SC7280_MASK,
+ .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
+ },
+ {
+ .name = "ctl_2", .id = CTL_2,
+ .base = 0x17000, .len = 0x204,
+ .features = CTL_SC7280_MASK,
+ .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
+ },
+ {
+ .name = "ctl_3", .id = CTL_3,
+ .base = 0x18000, .len = 0x204,
+ .features = CTL_SC7280_MASK,
+ .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),
+ },
+ {
+ .name = "ctl_4", .id = CTL_4,
+ .base = 0x19000, .len = 0x204,
+ .features = CTL_SC7280_MASK,
+ .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13),
+ },
+ {
+ .name = "ctl_5", .id = CTL_5,
+ .base = 0x1a000, .len = 0x204,
+ .features = CTL_SC7280_MASK,
+ .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23),
+ },
+};
+
+static const struct dpu_lm_cfg dpu_8_lm6_lm[] = {
+ LM_BLK("lm_0", LM_0, 0x44000, MIXER_SDM845_MASK, &sdm845_lm_sblk, PINGPONG_0, LM_1, DSPP_0),
+ LM_BLK("lm_1", LM_1, 0x45000, MIXER_SDM845_MASK, &sdm845_lm_sblk, PINGPONG_1, LM_0, DSPP_1),
+ LM_BLK("lm_2", LM_2, 0x46000, MIXER_SDM845_MASK, &sdm845_lm_sblk, PINGPONG_2, LM_3, DSPP_2),
+ LM_BLK("lm_3", LM_3, 0x47000, MIXER_SDM845_MASK, &sdm845_lm_sblk, PINGPONG_3, LM_2, DSPP_3),
+ LM_BLK("lm_4", LM_4, 0x48000, MIXER_SDM845_MASK, &sdm845_lm_sblk, PINGPONG_4, LM_5, 0),
+ LM_BLK("lm_5", LM_5, 0x49000, MIXER_SDM845_MASK, &sdm845_lm_sblk, PINGPONG_5, LM_4, 0),
+};
+
+static const struct dpu_dspp_cfg dpu_8_lm6_dspp[] = {
+ DSPP_BLK("dspp_0", DSPP_0, 0x54000, DSPP_SC7180_MASK,
+ &sm8150_dspp_sblk),
+ DSPP_BLK("dspp_1", DSPP_1, 0x56000, DSPP_SC7180_MASK,
+ &sm8150_dspp_sblk),
+ DSPP_BLK("dspp_2", DSPP_2, 0x58000, DSPP_SC7180_MASK,
+ &sm8150_dspp_sblk),
+ DSPP_BLK("dspp_3", DSPP_3, 0x5a000, DSPP_SC7180_MASK,
+ &sm8150_dspp_sblk),
+};
+
+#endif
--
2.39.2
next prev parent reply other threads:[~2023-03-30 21:54 UTC|newest]
Thread overview: 52+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-03-30 21:52 [PATCH v3 00/38] drm/msm/dpu: rework HW catalog Dmitry Baryshkov
2023-03-30 21:52 ` [PATCH v3 01/38] drm/msm/dpu: Allow variable SSPP/INTF_BLK size Dmitry Baryshkov
2023-04-01 0:57 ` Abhinav Kumar
2023-04-01 9:37 ` Dmitry Baryshkov
2023-04-03 22:04 ` [Freedreno] " Abhinav Kumar
2023-03-30 21:52 ` [PATCH v3 02/38] drm/msm/dpu: constify DSC data structures Dmitry Baryshkov
2023-04-01 1:01 ` [Freedreno] " Abhinav Kumar
2023-03-30 21:52 ` [PATCH v3 03/38] drm/msm/dpu: mark remaining pp data as const Dmitry Baryshkov
2023-04-01 1:03 ` Abhinav Kumar
2023-03-30 21:52 ` [PATCH v3 04/38] drm/msm/dpu: move UBWC/memory configuration to separate struct Dmitry Baryshkov
2023-04-01 1:10 ` Abhinav Kumar
2023-03-30 21:52 ` [PATCH v3 05/38] drm/msm/dpu: split SM8550 catalog entry to the separate file Dmitry Baryshkov
2023-03-30 21:52 ` [PATCH v3 06/38] drm/msm/dpu: split SM8450 " Dmitry Baryshkov
2023-03-30 21:52 ` [PATCH v3 07/38] drm/msm/dpu: split SC8280XP " Dmitry Baryshkov
2023-03-30 21:52 ` [PATCH v3 08/38] drm/msm/dpu: split SC7280 " Dmitry Baryshkov
2023-03-30 21:52 ` [PATCH v3 09/38] drm/msm/dpu: split SM8350 " Dmitry Baryshkov
2023-03-30 21:52 ` [PATCH v3 10/38] drm/msm/dpu: split SM6115 " Dmitry Baryshkov
2023-03-30 21:52 ` [PATCH v3 11/38] drm/msm/dpu: split QCM2290 " Dmitry Baryshkov
2023-03-30 21:52 ` [PATCH v3 12/38] drm/msm/dpu: split SC7180 " Dmitry Baryshkov
2023-03-30 21:52 ` [PATCH v3 13/38] drm/msm/dpu: split SM8250 " Dmitry Baryshkov
2023-03-30 21:53 ` [PATCH v3 14/38] drm/msm/dpu: split SC8180X " Dmitry Baryshkov
2023-03-30 21:53 ` [PATCH v3 15/38] drm/msm/dpu: split SM8150 " Dmitry Baryshkov
2023-03-30 21:53 ` [PATCH v3 16/38] drm/msm/dpu: split MSM8998 " Dmitry Baryshkov
2023-03-30 21:53 ` [PATCH v3 17/38] drm/msm/dpu: split SDM845 " Dmitry Baryshkov
2023-03-30 21:53 ` [PATCH v3 18/38] drm/msm/dpu: duplicate sdm845 catalog entries Dmitry Baryshkov
2023-03-30 21:53 ` [PATCH v3 19/38] drm/msm/dpu: duplicate sc7180 " Dmitry Baryshkov
2023-03-30 21:53 ` [PATCH v3 20/38] drm/msm/dpu: duplicate sm8150 " Dmitry Baryshkov
2023-03-30 21:53 ` [PATCH v3 21/38] drm/msm/dpu: duplicate sm8250 " Dmitry Baryshkov
2023-03-30 21:53 ` [PATCH v3 22/38] drm/msm/dpu: duplicate sm8350 " Dmitry Baryshkov
2023-03-30 21:53 ` [PATCH v3 23/38] drm/msm/dpu: use defined symbol for sc8280xp's maxwidth Dmitry Baryshkov
2023-03-30 21:53 ` [PATCH v3 24/38] drm/msm/dpu: catalog: add comments regarding DPU_CTL_SPLIT_DISPLAY Dmitry Baryshkov
2023-03-30 22:39 ` [v3,24/38] " Konrad Dybcio
2023-03-30 21:53 ` [PATCH v3 25/38] drm/msm/dpu: enable DPU_CTL_SPLIT_DISPLAY for sc8280xp Dmitry Baryshkov
2023-03-30 22:40 ` [v3,25/38] " Konrad Dybcio
2023-03-30 21:53 ` [PATCH v3 26/38] drm/msm/dpu: enable DSPP_2/3 for LM_2/3 on sm8450 Dmitry Baryshkov
2023-03-30 21:53 ` [PATCH v3 27/38] drm/msm/dpu: drop duplicate vig_sblk instances Dmitry Baryshkov
2023-03-30 21:53 ` [PATCH v3 28/38] drm/msm/dpu: enable DSPP on sc8180x Dmitry Baryshkov
2023-03-30 22:40 ` [v3,28/38] " Konrad Dybcio
2023-03-30 21:53 ` [PATCH v3 29/38] drm/msm/dpu: deduplicate sc8180x with sm8150 Dmitry Baryshkov
2023-03-30 21:53 ` [PATCH v3 30/38] drm/msm/dpu: deduplicate sm6115 with qcm2290 Dmitry Baryshkov
2023-03-30 21:53 ` Dmitry Baryshkov [this message]
2023-03-30 21:53 ` [PATCH v3 32/38] drm/msm/dpu: drop unused macros from hw catalog Dmitry Baryshkov
2023-03-30 21:53 ` [PATCH v3 33/38] drm/msm/dpu: inline IRQ_n_MASK defines Dmitry Baryshkov
2023-03-30 21:53 ` [PATCH v3 34/38] drm/msm/dpu: rename INTF_foo_MASK to contain major DPU version Dmitry Baryshkov
2023-03-30 21:53 ` [PATCH v3 35/38] drm/msm/dpu: rename CTL_foo_MASK " Dmitry Baryshkov
2023-03-30 21:53 ` [PATCH v3 36/38] drm/msm/dpu: rename VIG and DMA_foo_MASK " Dmitry Baryshkov
2023-03-30 21:53 ` [PATCH v3 37/38] drm/msm/dpu: rename MIXER_foo_MASK " Dmitry Baryshkov
2023-03-30 21:53 ` [PATCH v3 38/38] drm/msm/dpu: rename MERGE_3D_foo_MASK " Dmitry Baryshkov
2023-04-03 18:06 ` [PATCH v3 00/38] drm/msm/dpu: rework HW catalog Abhinav Kumar
2023-04-03 18:48 ` Dmitry Baryshkov
2023-04-03 19:07 ` Abhinav Kumar
2023-04-03 22:16 ` Dmitry Baryshkov
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