From: Konrad Dybcio <konrad.dybcio@linaro.org>
To: Rob Clark <robdclark@gmail.com>,
Abhinav Kumar <quic_abhinavk@quicinc.com>,
Dmitry Baryshkov <dmitry.baryshkov@linaro.org>,
Sean Paul <sean@poorly.run>, David Airlie <airlied@gmail.com>,
Daniel Vetter <daniel@ffwll.ch>
Cc: Marijn Suijten <marijn.suijten@somainline.org>,
Jonathan Marek <jonathan@marek.ca>,
linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org,
freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org,
Konrad Dybcio <konrad.dybcio@linaro.org>
Subject: [PATCH v2 3/6] drm/msm/a6xx: Skip empty protection ranges entries
Date: Fri, 19 May 2023 15:29:08 +0200 [thread overview]
Message-ID: <20230517-topic-a7xx_prep-v2-3-5b9daa2b2cf0@linaro.org> (raw)
In-Reply-To: <20230517-topic-a7xx_prep-v2-0-5b9daa2b2cf0@linaro.org>
Some specific SKUs leave certain protection range registers empty.
Allow for that behavior.
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
---
drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 7 +++++--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
index deed42675fe2..8707e8b6ac7e 100644
--- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
+++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
@@ -778,8 +778,11 @@ static void a6xx_set_cp_protect(struct msm_gpu *gpu)
*/
gpu_write(gpu, REG_A6XX_CP_PROTECT_CNTL, BIT(0) | BIT(1) | BIT(3));
- for (i = 0; i < count - 1; i++)
- gpu_write(gpu, REG_A6XX_CP_PROTECT(i), regs[i]);
+ for (i = 0; i < count - 1; i++) {
+ /* Intentionally skip writing to some registers */
+ if (regs[i])
+ gpu_write(gpu, REG_A6XX_CP_PROTECT(i), regs[i]);
+ }
/* last CP_PROTECT to have "infinite" length on the last entry */
gpu_write(gpu, REG_A6XX_CP_PROTECT(count_max - 1), regs[i]);
}
--
2.40.1
next prev parent reply other threads:[~2023-05-19 13:29 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-05-19 13:29 [PATCH v2 0/6] Adreno QoL changes Konrad Dybcio
2023-05-19 13:29 ` [PATCH v2 1/6] drm/msm/a6xx: Add REG_A6XX_GMU_AHB_FENCE_STATUS_CLR definition Konrad Dybcio
2023-05-19 13:29 ` [PATCH v2 2/6] drm/msm/a6xx: Explain CP_PROTECT_CNTL writes in a6xx_set_cp_protect Konrad Dybcio
2023-05-25 17:38 ` Rob Clark
2023-05-19 13:29 ` Konrad Dybcio [this message]
2023-05-19 13:29 ` [PATCH v2 4/6] drm/msm/a6xx: Ensure clean GMU state in a6xx_gmu_fw_start Konrad Dybcio
2023-05-19 13:29 ` [PATCH v2 5/6] drm/msm/a6xx: Improve GMU force shutdown sequence Konrad Dybcio
2023-05-19 13:29 ` [PATCH v2 6/6] drm/msm/a6xx: Fix up GMU region reservations Konrad Dybcio
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