[PATCH v2 0/6] drm/msm/dpu: rework interrupt handling

[PATCH v2 0/6] drm/msm/dpu: rework interrupt handling

[Dmitry Baryshkov]

Declaring the mask of supported interrupts proved to be error-prone. It
is very easy to add a bit with no corresponding backing block or to miss
the INTF TE bit. Replace this static configuration with the irq mask
calculated from the HW catalog data.

Changes since v1:
 - Enable dpu_caps::has_7xxx_intr for DPU >= 7.0 (Neil)

Dmitry Baryshkov (6):
  drm/msm/dpu: don't set DPU_INTF_TE globally
  drm/msm/dpu: inline __intr_offset
  drm/msm/dpu: split interrupt address arrays
  drm/msm/dpu: autodetect supported interrupts
  drm/msm/dpu: drop now-unused mdss_irqs field from hw catalog
  drm/msm/dpu: drop compatibility INTR defines

 .../msm/disp/dpu1/catalog/dpu_3_0_msm8998.h   |   8 --
 .../msm/disp/dpu1/catalog/dpu_4_0_sdm845.h    |   9 --
 .../msm/disp/dpu1/catalog/dpu_5_0_sm8150.h    |  11 --
 .../msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h   |  13 ---
 .../msm/disp/dpu1/catalog/dpu_6_0_sm8250.h    |  10 --
 .../msm/disp/dpu1/catalog/dpu_6_2_sc7180.h    |   6 -
 .../msm/disp/dpu1/catalog/dpu_6_3_sm6115.h    |   5 -
 .../msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h   |   5 -
 .../msm/disp/dpu1/catalog/dpu_7_0_sm8350.h    |  14 +--
 .../msm/disp/dpu1/catalog/dpu_7_2_sc7280.h    |  10 +-
 .../msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h  |  19 +--
 .../msm/disp/dpu1/catalog/dpu_8_1_sm8450.h    |  14 +--
 .../msm/disp/dpu1/catalog/dpu_9_0_sm8550.h    |  14 +--
 .../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c    |   3 +-
 .../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h    |   5 +-
 .../gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c | 110 ++++++++++++------
 .../gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h |  21 ++--
 17 files changed, 102 insertions(+), 175 deletions(-)

-- 
2.39.2

[PATCH v2 1/6] drm/msm/dpu: don't set DPU_INTF_TE globally

[Dmitry Baryshkov]

Using BIT(DPU_INTF_TE) in INTF_SC7180_MASK (and by extension in
INTF_SC7280_MASK) results in this bit (and corrsponding operations)
being enabled for all interfaces, even the ones which do not have TE
block. Move this bit setting to INTF_DSI_TE(), so that it is only
enabled for those INTF blocks which have TE support.

Fixes: 152c1d430992 ("drm/msm/dpu: Add TEAR-READ-pointer interrupt to INTF block")
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
index 1dee5ba2b312..162141cb5c83 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
@@ -101,7 +101,6 @@
 
 #define INTF_SC7180_MASK \
 	(BIT(DPU_INTF_INPUT_CTRL) | \
-	 BIT(DPU_INTF_TE) | \
 	 BIT(DPU_INTF_STATUS_SUPPORTED) | \
 	 BIT(DPU_DATA_HCTL_EN))
 
@@ -544,7 +543,7 @@ static const struct dpu_pingpong_sub_blks sc7280_pp_sblk = {
 	{\
 	.name = _name, .id = _id, \
 	.base = _base, .len = _len, \
-	.features = _features, \
+	.features = _features | BIT(DPU_INTF_TE), \
 	.type = _type, \
 	.controller_id = _ctrl_id, \
 	.prog_fetch_lines_worst_case = _progfetch, \
-- 
2.39.2

Re: [PATCH v2 1/6] drm/msm/dpu: don't set DPU_INTF_TE globally

[Marijn Suijten]

Title suggestion: s/globally/on non-TE/DSI (INTF) blocks

On 2023-05-23 00:45:22, Dmitry Baryshkov wrote:
> Using BIT(DPU_INTF_TE) in INTF_SC7180_MASK (and by extension in
> INTF_SC7280_MASK) results in this bit (and corrsponding operations)
> being enabled for all interfaces, even the ones which do not have TE
> block. Move this bit setting to INTF_DSI_TE(), so that it is only
> enabled for those INTF blocks which have TE support.
> 
> Fixes: 152c1d430992 ("drm/msm/dpu: Add TEAR-READ-pointer interrupt to INTF block")
> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>

We've always been setting flags globally but I guess it makes sense to
not only restrict this flag to DPU >= 5.0.0 but also just the few
hardware blocks that actually have these in their *enlarged* register
space (and have the interrupt).

Reviewed-by: Marijn Suijten <marijn.suijten@somainline.org>

> ---
>  drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 3 +--
>  1 file changed, 1 insertion(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
> index 1dee5ba2b312..162141cb5c83 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
> @@ -101,7 +101,6 @@
>  
>  #define INTF_SC7180_MASK \
>  	(BIT(DPU_INTF_INPUT_CTRL) | \
> -	 BIT(DPU_INTF_TE) | \
>  	 BIT(DPU_INTF_STATUS_SUPPORTED) | \
>  	 BIT(DPU_DATA_HCTL_EN))
>  
> @@ -544,7 +543,7 @@ static const struct dpu_pingpong_sub_blks sc7280_pp_sblk = {
>  	{\
>  	.name = _name, .id = _id, \
>  	.base = _base, .len = _len, \
> -	.features = _features, \
> +	.features = _features | BIT(DPU_INTF_TE), \

Now that we're more broadly switching to this pattern, should we do the
same for PP_BLK() with and without TE block?  That way we can also
forcefully initialize intr_rdptr=-1 similar to what I did for
intr_tear_rd_ptr in INTF_BLK() (vs INTF_BLK_DSI_TE) here, instead of
having the -1's floating around the catalog when I added them in commit
7952f5180eb3e ("drm/msm/dpu: Remove intr_rdptr from DPU >= 5.0.0
pingpong config").

- Marijn

>  	.type = _type, \
>  	.controller_id = _ctrl_id, \
>  	.prog_fetch_lines_worst_case = _progfetch, \
> -- 
> 2.39.2
> 

Re: [PATCH v2 1/6] drm/msm/dpu: don't set DPU_INTF_TE globally

[Dmitry Baryshkov]

On 23/05/2023 00:56, Marijn Suijten wrote:
> Title suggestion: s/globally/on non-TE/DSI (INTF) blocks
> 
> On 2023-05-23 00:45:22, Dmitry Baryshkov wrote:
>> Using BIT(DPU_INTF_TE) in INTF_SC7180_MASK (and by extension in
>> INTF_SC7280_MASK) results in this bit (and corrsponding operations)
>> being enabled for all interfaces, even the ones which do not have TE
>> block. Move this bit setting to INTF_DSI_TE(), so that it is only
>> enabled for those INTF blocks which have TE support.
>>
>> Fixes: 152c1d430992 ("drm/msm/dpu: Add TEAR-READ-pointer interrupt to INTF block")
>> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
>> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> 
> We've always been setting flags globally but I guess it makes sense to
> not only restrict this flag to DPU >= 5.0.0 but also just the few
> hardware blocks that actually have these in their *enlarged* register
> space (and have the interrupt).
> 
> Reviewed-by: Marijn Suijten <marijn.suijten@somainline.org>
> 
>> ---
>>   drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 3 +--
>>   1 file changed, 1 insertion(+), 2 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
>> index 1dee5ba2b312..162141cb5c83 100644
>> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
>> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
>> @@ -101,7 +101,6 @@
>>   
>>   #define INTF_SC7180_MASK \
>>   	(BIT(DPU_INTF_INPUT_CTRL) | \
>> -	 BIT(DPU_INTF_TE) | \
>>   	 BIT(DPU_INTF_STATUS_SUPPORTED) | \
>>   	 BIT(DPU_DATA_HCTL_EN))
>>   
>> @@ -544,7 +543,7 @@ static const struct dpu_pingpong_sub_blks sc7280_pp_sblk = {
>>   	{\
>>   	.name = _name, .id = _id, \
>>   	.base = _base, .len = _len, \
>> -	.features = _features, \
>> +	.features = _features | BIT(DPU_INTF_TE), \
> 
> Now that we're more broadly switching to this pattern, should we do the
> same for PP_BLK() with and without TE block?  That way we can also
> forcefully initialize intr_rdptr=-1 similar to what I did for
> intr_tear_rd_ptr in INTF_BLK() (vs INTF_BLK_DSI_TE) here, instead of
> having the -1's floating around the catalog when I added them in commit
> 7952f5180eb3e ("drm/msm/dpu: Remove intr_rdptr from DPU >= 5.0.0
> pingpong config").

If we are going to expand the macros, then hiding -1 probably doesn't 
make sense as it will reappear soon.

Probably it makes sense to do another thing (which would play better 
with the expanded macros): increase IRQ indices by 1, making 'NO IRQ' 
equal to 0 instead of -1. This way all non-existing interrupts can be 
omitted during macros expansion. WDYT?

> 
> - Marijn
> 
>>   	.type = _type, \
>>   	.controller_id = _ctrl_id, \
>>   	.prog_fetch_lines_worst_case = _progfetch, \
>> -- 
>> 2.39.2
>>

-- 
With best wishes
Dmitry

Re: [PATCH v2 1/6] drm/msm/dpu: don't set DPU_INTF_TE globally

[Marijn Suijten]

On 2023-05-23 01:01:50, Dmitry Baryshkov wrote:
> On 23/05/2023 00:56, Marijn Suijten wrote:
> > Title suggestion: s/globally/on non-TE/DSI (INTF) blocks
> > 
> > On 2023-05-23 00:45:22, Dmitry Baryshkov wrote:
> >> Using BIT(DPU_INTF_TE) in INTF_SC7180_MASK (and by extension in
> >> INTF_SC7280_MASK) results in this bit (and corrsponding operations)
> >> being enabled for all interfaces, even the ones which do not have TE
> >> block. Move this bit setting to INTF_DSI_TE(), so that it is only
> >> enabled for those INTF blocks which have TE support.
> >>
> >> Fixes: 152c1d430992 ("drm/msm/dpu: Add TEAR-READ-pointer interrupt to INTF block")
> >> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
> >> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> > 
> > We've always been setting flags globally but I guess it makes sense to
> > not only restrict this flag to DPU >= 5.0.0 but also just the few
> > hardware blocks that actually have these in their *enlarged* register
> > space (and have the interrupt).
> > 
> > Reviewed-by: Marijn Suijten <marijn.suijten@somainline.org>
> > 
> >> ---
> >>   drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 3 +--
> >>   1 file changed, 1 insertion(+), 2 deletions(-)
> >>
> >> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
> >> index 1dee5ba2b312..162141cb5c83 100644
> >> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
> >> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
> >> @@ -101,7 +101,6 @@
> >>   
> >>   #define INTF_SC7180_MASK \
> >>   	(BIT(DPU_INTF_INPUT_CTRL) | \
> >> -	 BIT(DPU_INTF_TE) | \
> >>   	 BIT(DPU_INTF_STATUS_SUPPORTED) | \
> >>   	 BIT(DPU_DATA_HCTL_EN))
> >>   
> >> @@ -544,7 +543,7 @@ static const struct dpu_pingpong_sub_blks sc7280_pp_sblk = {
> >>   	{\
> >>   	.name = _name, .id = _id, \
> >>   	.base = _base, .len = _len, \
> >> -	.features = _features, \
> >> +	.features = _features | BIT(DPU_INTF_TE), \
> > 
> > Now that we're more broadly switching to this pattern, should we do the
> > same for PP_BLK() with and without TE block?  That way we can also
> > forcefully initialize intr_rdptr=-1 similar to what I did for
> > intr_tear_rd_ptr in INTF_BLK() (vs INTF_BLK_DSI_TE) here, instead of
> > having the -1's floating around the catalog when I added them in commit
> > 7952f5180eb3e ("drm/msm/dpu: Remove intr_rdptr from DPU >= 5.0.0
> > pingpong config").
> 
> If we are going to expand the macros, then hiding -1 probably doesn't 
> make sense as it will reappear soon.
> 
> Probably it makes sense to do another thing (which would play better 
> with the expanded macros): increase IRQ indices by 1, making 'NO IRQ' 
> equal to 0 instead of -1. This way all non-existing interrupts can be 
> omitted during macros expansion. WDYT?

I'm fine explicitly setting it to -1 to clarify it is missing.  On the
other hand, default struct initialization might accidentally initialize
it to the first interrupt on MDP_SSPP_TOP0_INTR (when users forget to
write the member), where it makes sense to start at 1 instead.  Need to
think about this for a bit.
(The forced number of arguments is an advantage of the macro, even if we
 now have too many numeric constants to know which field it sets)

- Marijn

> > - Marijn
> > 
> >>   	.type = _type, \
> >>   	.controller_id = _ctrl_id, \
> >>   	.prog_fetch_lines_worst_case = _progfetch, \
> >> -- 
> >> 2.39.2
> >>
> 
> -- 
> With best wishes
> Dmitry
> 

Re: [PATCH v2 1/6] drm/msm/dpu: don't set DPU_INTF_TE globally

[Marijn Suijten]

On 2023-05-23 00:45:22, Dmitry Baryshkov wrote:
> Using BIT(DPU_INTF_TE) in INTF_SC7180_MASK (and by extension in
> INTF_SC7280_MASK) results in this bit (and corrsponding operations)
> being enabled for all interfaces, even the ones which do not have TE
> block. Move this bit setting to INTF_DSI_TE(), so that it is only
> enabled for those INTF blocks which have TE support.
> 
> Fixes: 152c1d430992 ("drm/msm/dpu: Add TEAR-READ-pointer interrupt to INTF block")
> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> ---
>  drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 3 +--
>  1 file changed, 1 insertion(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
> index 1dee5ba2b312..162141cb5c83 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
> @@ -101,7 +101,6 @@
>  
>  #define INTF_SC7180_MASK \
>  	(BIT(DPU_INTF_INPUT_CTRL) | \
> -	 BIT(DPU_INTF_TE) | \
>  	 BIT(DPU_INTF_STATUS_SUPPORTED) | \
>  	 BIT(DPU_DATA_HCTL_EN))
>  
> @@ -544,7 +543,7 @@ static const struct dpu_pingpong_sub_blks sc7280_pp_sblk = {
>  	{\
>  	.name = _name, .id = _id, \
>  	.base = _base, .len = _len, \
> -	.features = _features, \
> +	.features = _features | BIT(DPU_INTF_TE), \

We'll have to be very careful when applying this.  I already had a hard
time reviewing because of missing the #define context but assumed it
would apply to INTF_BLK_DSI_TE()... but when actually applying it
locally this ended up in INTF_BLK() and breaking everything.

- Marijn

>  	.type = _type, \
>  	.controller_id = _ctrl_id, \
>  	.prog_fetch_lines_worst_case = _progfetch, \
> -- 
> 2.39.2
> 

[PATCH v2 2/6] drm/msm/dpu: inline __intr_offset

[Dmitry Baryshkov]

Inline __intr_offset(), there is no point in having a separate oneline
function for setting base block address.

Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c | 8 +-------
 1 file changed, 1 insertion(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c
index 5e2d68ebb113..0776b0f6df4f 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c
@@ -435,12 +435,6 @@ u32 dpu_core_irq_read(struct dpu_kms *dpu_kms, int irq_idx)
 	return intr_status;
 }
 
-static void __intr_offset(const struct dpu_mdss_cfg *m,
-		void __iomem *addr, struct dpu_hw_blk_reg_map *hw)
-{
-	hw->blk_addr = addr + m->mdp[0].base;
-}
-
 struct dpu_hw_intr *dpu_hw_intr_init(void __iomem *addr,
 		const struct dpu_mdss_cfg *m)
 {
@@ -454,7 +448,7 @@ struct dpu_hw_intr *dpu_hw_intr_init(void __iomem *addr,
 	if (!intr)
 		return ERR_PTR(-ENOMEM);
 
-	__intr_offset(m, addr, &intr->hw);
+	intr->hw.blk_addr = addr + m->mdp[0].base;
 
 	intr->total_irqs = nirq;
 
-- 
2.39.2

Re: [PATCH v2 2/6] drm/msm/dpu: inline __intr_offset

[Marijn Suijten]

On 2023-05-23 00:45:23, Dmitry Baryshkov wrote:
> Inline __intr_offset(), there is no point in having a separate oneline
> function for setting base block address.
> 
> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>

Reviewed-by: Marijn Suijten <marijn.suijten@somainline.org>

> ---
>  drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c | 8 +-------
>  1 file changed, 1 insertion(+), 7 deletions(-)
> 
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c
> index 5e2d68ebb113..0776b0f6df4f 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c
> @@ -435,12 +435,6 @@ u32 dpu_core_irq_read(struct dpu_kms *dpu_kms, int irq_idx)
>  	return intr_status;
>  }
>  
> -static void __intr_offset(const struct dpu_mdss_cfg *m,
> -		void __iomem *addr, struct dpu_hw_blk_reg_map *hw)
> -{
> -	hw->blk_addr = addr + m->mdp[0].base;
> -}
> -
>  struct dpu_hw_intr *dpu_hw_intr_init(void __iomem *addr,
>  		const struct dpu_mdss_cfg *m)
>  {
> @@ -454,7 +448,7 @@ struct dpu_hw_intr *dpu_hw_intr_init(void __iomem *addr,
>  	if (!intr)
>  		return ERR_PTR(-ENOMEM);
>  
> -	__intr_offset(m, addr, &intr->hw);
> +	intr->hw.blk_addr = addr + m->mdp[0].base;
>  
>  	intr->total_irqs = nirq;
>  

We could also drop the two newlines here and make these member
assignments sit clearly/tightly together.

- Marijn

> -- 
> 2.39.2
> 

[PATCH v2 3/6] drm/msm/dpu: split interrupt address arrays

[Dmitry Baryshkov]

There is no point in having a single enum (and a single array) for both
DPU < 7.0 and DPU >= 7.0 interrupt registers. Instead define a single
enum and two IRQ address arrays.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
 .../msm/disp/dpu1/catalog/dpu_7_0_sm8350.h    |  1 +
 .../msm/disp/dpu1/catalog/dpu_7_2_sc7280.h    |  1 +
 .../msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h  |  1 +
 .../msm/disp/dpu1/catalog/dpu_8_1_sm8450.h    |  1 +
 .../msm/disp/dpu1/catalog/dpu_9_0_sm8550.h    |  1 +
 .../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h    |  2 +
 .../gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c | 82 +++++++++++++------
 .../gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h | 28 ++++---
 8 files changed, 79 insertions(+), 38 deletions(-)

diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h
index 3c1b2c13398d..320cfa4be633 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h
@@ -15,6 +15,7 @@ static const struct dpu_caps sm8350_dpu_caps = {
 	.has_dim_layer = true,
 	.has_idle_pc = true,
 	.has_3d_merge = true,
+	.has_7xxx_intr = true,
 	.max_linewidth = 4096,
 	.pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
 };
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h
index 5d894cbb0a62..9306c7a115e9 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h
@@ -13,6 +13,7 @@ static const struct dpu_caps sc7280_dpu_caps = {
 	.qseed_type = DPU_SSPP_SCALER_QSEED4,
 	.has_dim_layer = true,
 	.has_idle_pc = true,
+	.has_7xxx_intr = true,
 	.max_linewidth = 2400,
 	.pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
 };
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h
index c3f1ae000a21..fc1e17c495f0 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h
@@ -15,6 +15,7 @@ static const struct dpu_caps sc8280xp_dpu_caps = {
 	.has_dim_layer = true,
 	.has_idle_pc = true,
 	.has_3d_merge = true,
+	.has_7xxx_intr = true,
 	.max_linewidth = 5120,
 	.pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
 };
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h
index 86c2e68ebd2c..eb72411c16db 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h
@@ -14,6 +14,7 @@ static const struct dpu_caps sm8450_dpu_caps = {
 	.has_src_split = true,
 	.has_dim_layer = true,
 	.has_idle_pc = true,
+	.has_7xxx_intr = true,
 	.has_3d_merge = true,
 	.max_linewidth = 5120,
 	.pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h
index 85dc34458b88..8209ca317bdc 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h
@@ -15,6 +15,7 @@ static const struct dpu_caps sm8550_dpu_caps = {
 	.has_dim_layer = true,
 	.has_idle_pc = true,
 	.has_3d_merge = true,
+	.has_7xxx_intr = true,
 	.max_linewidth = 5120,
 	.pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
 };
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
index 677048cc3b7d..72530ebb0ae6 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
@@ -351,6 +351,7 @@ struct dpu_rotation_cfg {
  * @has_dim_layer      dim layer feature status
  * @has_idle_pc        indicate if idle power collapse feature is supported
  * @has_3d_merge       indicate if 3D merge is supported
+ * @has_7xxx_intr      indicate that INTF/IRQs use addressing for DPU 7.0 and greater
  * @max_linewidth      max linewidth for sspp
  * @pixel_ram_size     size of latency hiding and de-tiling buffer in bytes
  * @max_hdeci_exp      max horizontal decimation supported (max is 2^value)
@@ -364,6 +365,7 @@ struct dpu_caps {
 	bool has_dim_layer;
 	bool has_idle_pc;
 	bool has_3d_merge;
+	bool has_7xxx_intr;
 	/* SSPP limits */
 	u32 max_linewidth;
 	u32 pixel_ram_size;
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c
index 0776b0f6df4f..a03d826bb9ad 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c
@@ -51,11 +51,9 @@ struct dpu_intr_reg {
 };
 
 /*
- * struct dpu_intr_reg -  List of DPU interrupt registers
- *
- * When making changes be sure to sync with dpu_hw_intr_reg
+ * dpu_intr_set_legacy -  List of DPU interrupt registers for DPU <= 6.x
  */
-static const struct dpu_intr_reg dpu_intr_set[] = {
+static const struct dpu_intr_reg dpu_intr_set_legacy[] = {
 	[MDP_SSPP_TOP0_INTR] = {
 		INTR_CLEAR,
 		INTR_EN,
@@ -121,57 +119,78 @@ static const struct dpu_intr_reg dpu_intr_set[] = {
 		MDP_AD4_INTR_EN_OFF(1),
 		MDP_AD4_INTR_STATUS_OFF(1),
 	},
-	[MDP_INTF0_7xxx_INTR] = {
+};
+
+/*
+ * dpu_intr_set_7xxx -  List of DPU interrupt registers for DPU >= 7.0
+ */
+static const struct dpu_intr_reg dpu_intr_set_7xxx[] = {
+	[MDP_SSPP_TOP0_INTR] = {
+		INTR_CLEAR,
+		INTR_EN,
+		INTR_STATUS
+	},
+	[MDP_SSPP_TOP0_INTR2] = {
+		INTR2_CLEAR,
+		INTR2_EN,
+		INTR2_STATUS
+	},
+	[MDP_SSPP_TOP0_HIST_INTR] = {
+		HIST_INTR_CLEAR,
+		HIST_INTR_EN,
+		HIST_INTR_STATUS
+	},
+	[MDP_INTF0_INTR] = {
 		MDP_INTF_REV_7xxx_INTR_CLEAR(0),
 		MDP_INTF_REV_7xxx_INTR_EN(0),
 		MDP_INTF_REV_7xxx_INTR_STATUS(0)
 	},
-	[MDP_INTF1_7xxx_INTR] = {
+	[MDP_INTF1_INTR] = {
 		MDP_INTF_REV_7xxx_INTR_CLEAR(1),
 		MDP_INTF_REV_7xxx_INTR_EN(1),
 		MDP_INTF_REV_7xxx_INTR_STATUS(1)
 	},
-	[MDP_INTF1_7xxx_TEAR_INTR] = {
+	[MDP_INTF1_TEAR_INTR] = {
 		MDP_INTF_REV_7xxx_INTR_TEAR_CLEAR(1),
 		MDP_INTF_REV_7xxx_INTR_TEAR_EN(1),
 		MDP_INTF_REV_7xxx_INTR_TEAR_STATUS(1)
 	},
-	[MDP_INTF2_7xxx_INTR] = {
+	[MDP_INTF2_INTR] = {
 		MDP_INTF_REV_7xxx_INTR_CLEAR(2),
 		MDP_INTF_REV_7xxx_INTR_EN(2),
 		MDP_INTF_REV_7xxx_INTR_STATUS(2)
 	},
-	[MDP_INTF2_7xxx_TEAR_INTR] = {
+	[MDP_INTF2_TEAR_INTR] = {
 		MDP_INTF_REV_7xxx_INTR_TEAR_CLEAR(2),
 		MDP_INTF_REV_7xxx_INTR_TEAR_EN(2),
 		MDP_INTF_REV_7xxx_INTR_TEAR_STATUS(2)
 	},
-	[MDP_INTF3_7xxx_INTR] = {
+	[MDP_INTF3_INTR] = {
 		MDP_INTF_REV_7xxx_INTR_CLEAR(3),
 		MDP_INTF_REV_7xxx_INTR_EN(3),
 		MDP_INTF_REV_7xxx_INTR_STATUS(3)
 	},
-	[MDP_INTF4_7xxx_INTR] = {
+	[MDP_INTF4_INTR] = {
 		MDP_INTF_REV_7xxx_INTR_CLEAR(4),
 		MDP_INTF_REV_7xxx_INTR_EN(4),
 		MDP_INTF_REV_7xxx_INTR_STATUS(4)
 	},
-	[MDP_INTF5_7xxx_INTR] = {
+	[MDP_INTF5_INTR] = {
 		MDP_INTF_REV_7xxx_INTR_CLEAR(5),
 		MDP_INTF_REV_7xxx_INTR_EN(5),
 		MDP_INTF_REV_7xxx_INTR_STATUS(5)
 	},
-	[MDP_INTF6_7xxx_INTR] = {
+	[MDP_INTF6_INTR] = {
 		MDP_INTF_REV_7xxx_INTR_CLEAR(6),
 		MDP_INTF_REV_7xxx_INTR_EN(6),
 		MDP_INTF_REV_7xxx_INTR_STATUS(6)
 	},
-	[MDP_INTF7_7xxx_INTR] = {
+	[MDP_INTF7_INTR] = {
 		MDP_INTF_REV_7xxx_INTR_CLEAR(7),
 		MDP_INTF_REV_7xxx_INTR_EN(7),
 		MDP_INTF_REV_7xxx_INTR_STATUS(7)
 	},
-	[MDP_INTF8_7xxx_INTR] = {
+	[MDP_INTF8_INTR] = {
 		MDP_INTF_REV_7xxx_INTR_CLEAR(8),
 		MDP_INTF_REV_7xxx_INTR_EN(8),
 		MDP_INTF_REV_7xxx_INTR_STATUS(8)
@@ -216,19 +235,19 @@ irqreturn_t dpu_core_irq(struct msm_kms *kms)
 		return IRQ_NONE;
 
 	spin_lock_irqsave(&intr->irq_lock, irq_flags);
-	for (reg_idx = 0; reg_idx < ARRAY_SIZE(dpu_intr_set); reg_idx++) {
+	for (reg_idx = 0; reg_idx < MDP_INTR_MAX; reg_idx++) {
 		if (!test_bit(reg_idx, &intr->irq_mask))
 			continue;
 
 		/* Read interrupt status */
-		irq_status = DPU_REG_READ(&intr->hw, dpu_intr_set[reg_idx].status_off);
+		irq_status = DPU_REG_READ(&intr->hw, intr->intr_set[reg_idx].status_off);
 
 		/* Read enable mask */
-		enable_mask = DPU_REG_READ(&intr->hw, dpu_intr_set[reg_idx].en_off);
+		enable_mask = DPU_REG_READ(&intr->hw, intr->intr_set[reg_idx].en_off);
 
 		/* and clear the interrupt */
 		if (irq_status)
-			DPU_REG_WRITE(&intr->hw, dpu_intr_set[reg_idx].clr_off,
+			DPU_REG_WRITE(&intr->hw, intr->intr_set[reg_idx].clr_off,
 				     irq_status);
 
 		/* Finally update IRQ status based on enable mask */
@@ -285,7 +304,11 @@ static int dpu_hw_intr_enable_irq_locked(struct dpu_hw_intr *intr, int irq_idx)
 	assert_spin_locked(&intr->irq_lock);
 
 	reg_idx = DPU_IRQ_REG(irq_idx);
-	reg = &dpu_intr_set[reg_idx];
+	reg = &intr->intr_set[reg_idx];
+
+	/* Is this interrupt register supported on the platform */
+	if (WARN_ON(!reg->en_off))
+		return -EINVAL;
 
 	cache_irq_mask = intr->cache_irq_mask[reg_idx];
 	if (cache_irq_mask & DPU_IRQ_MASK(irq_idx)) {
@@ -334,7 +357,7 @@ static int dpu_hw_intr_disable_irq_locked(struct dpu_hw_intr *intr, int irq_idx)
 	assert_spin_locked(&intr->irq_lock);
 
 	reg_idx = DPU_IRQ_REG(irq_idx);
-	reg = &dpu_intr_set[reg_idx];
+	reg = &intr->intr_set[reg_idx];
 
 	cache_irq_mask = intr->cache_irq_mask[reg_idx];
 	if ((cache_irq_mask & DPU_IRQ_MASK(irq_idx)) == 0) {
@@ -368,10 +391,10 @@ static void dpu_clear_irqs(struct dpu_kms *dpu_kms)
 	if (!intr)
 		return;
 
-	for (i = 0; i < ARRAY_SIZE(dpu_intr_set); i++) {
+	for (i = 0; i < MDP_INTR_MAX; i++) {
 		if (test_bit(i, &intr->irq_mask))
 			DPU_REG_WRITE(&intr->hw,
-					dpu_intr_set[i].clr_off, 0xffffffff);
+					intr->intr_set[i].clr_off, 0xffffffff);
 	}
 
 	/* ensure register writes go through */
@@ -386,10 +409,10 @@ static void dpu_disable_all_irqs(struct dpu_kms *dpu_kms)
 	if (!intr)
 		return;
 
-	for (i = 0; i < ARRAY_SIZE(dpu_intr_set); i++) {
+	for (i = 0; i < MDP_INTR_MAX; i++) {
 		if (test_bit(i, &intr->irq_mask))
 			DPU_REG_WRITE(&intr->hw,
-					dpu_intr_set[i].en_off, 0x00000000);
+					intr->intr_set[i].en_off, 0x00000000);
 	}
 
 	/* ensure register writes go through */
@@ -421,10 +444,10 @@ u32 dpu_core_irq_read(struct dpu_kms *dpu_kms, int irq_idx)
 
 	reg_idx = DPU_IRQ_REG(irq_idx);
 	intr_status = DPU_REG_READ(&intr->hw,
-			dpu_intr_set[reg_idx].status_off) &
+			intr->intr_set[reg_idx].status_off) &
 		DPU_IRQ_MASK(irq_idx);
 	if (intr_status)
-		DPU_REG_WRITE(&intr->hw, dpu_intr_set[reg_idx].clr_off,
+		DPU_REG_WRITE(&intr->hw, intr->intr_set[reg_idx].clr_off,
 				intr_status);
 
 	/* ensure register writes go through */
@@ -448,6 +471,11 @@ struct dpu_hw_intr *dpu_hw_intr_init(void __iomem *addr,
 	if (!intr)
 		return ERR_PTR(-ENOMEM);
 
+	if (m->caps->has_7xxx_intr)
+		intr->intr_set = dpu_intr_set_7xxx;
+	else
+		intr->intr_set = dpu_intr_set_legacy;
+
 	intr->hw.blk_addr = addr + m->mdp[0].base;
 
 	intr->total_irqs = nirq;
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h
index 1f2dabc54c22..f329d6d7f646 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h
@@ -23,24 +23,29 @@ enum dpu_hw_intr_reg {
 	MDP_INTF3_INTR,
 	MDP_INTF4_INTR,
 	MDP_INTF5_INTR,
+	MDP_INTF6_INTR,
+	MDP_INTF7_INTR,
+	MDP_INTF8_INTR,
 	MDP_INTF1_TEAR_INTR,
 	MDP_INTF2_TEAR_INTR,
 	MDP_AD4_0_INTR,
 	MDP_AD4_1_INTR,
-	MDP_INTF0_7xxx_INTR,
-	MDP_INTF1_7xxx_INTR,
-	MDP_INTF1_7xxx_TEAR_INTR,
-	MDP_INTF2_7xxx_INTR,
-	MDP_INTF2_7xxx_TEAR_INTR,
-	MDP_INTF3_7xxx_INTR,
-	MDP_INTF4_7xxx_INTR,
-	MDP_INTF5_7xxx_INTR,
-	MDP_INTF6_7xxx_INTR,
-	MDP_INTF7_7xxx_INTR,
-	MDP_INTF8_7xxx_INTR,
 	MDP_INTR_MAX,
 };
 
+/* compatibility */
+#define MDP_INTF0_7xxx_INTR MDP_INTF0_INTR
+#define MDP_INTF1_7xxx_INTR MDP_INTF1_INTR
+#define MDP_INTF2_7xxx_INTR MDP_INTF2_INTR
+#define MDP_INTF3_7xxx_INTR MDP_INTF3_INTR
+#define MDP_INTF4_7xxx_INTR MDP_INTF4_INTR
+#define MDP_INTF5_7xxx_INTR MDP_INTF5_INTR
+#define MDP_INTF6_7xxx_INTR MDP_INTF6_INTR
+#define MDP_INTF7_7xxx_INTR MDP_INTF7_INTR
+#define MDP_INTF8_7xxx_INTR MDP_INTF8_INTR
+#define MDP_INTF1_7xxx_TEAR_INTR MDP_INTF1_TEAR_INTR
+#define MDP_INTF2_7xxx_TEAR_INTR MDP_INTF2_TEAR_INTR
+
 #define DPU_IRQ_IDX(reg_idx, offset)	(reg_idx * 32 + offset)
 
 /**
@@ -60,6 +65,7 @@ struct dpu_hw_intr {
 	u32 total_irqs;
 	spinlock_t irq_lock;
 	unsigned long irq_mask;
+	const struct dpu_intr_reg *intr_set;
 
 	struct {
 		void (*cb)(void *arg, int irq_idx);
-- 
2.39.2

Re: [PATCH v2 3/6] drm/msm/dpu: split interrupt address arrays

[Marijn Suijten]

... for 7xxx?

On 2023-05-23 00:45:24, Dmitry Baryshkov wrote:
> There is no point in having a single enum (and a single array) for both
> DPU < 7.0 and DPU >= 7.0 interrupt registers. Instead define a single
> enum and two IRQ address arrays.
> 
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>

Really like this idea to simplify some:

Reviewed-by: Marijn Suijten <marijn.suijten@somainline.org>

> ---
>  .../msm/disp/dpu1/catalog/dpu_7_0_sm8350.h    |  1 +
>  .../msm/disp/dpu1/catalog/dpu_7_2_sc7280.h    |  1 +
>  .../msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h  |  1 +
>  .../msm/disp/dpu1/catalog/dpu_8_1_sm8450.h    |  1 +
>  .../msm/disp/dpu1/catalog/dpu_9_0_sm8550.h    |  1 +
>  .../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h    |  2 +
>  .../gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c | 82 +++++++++++++------
>  .../gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h | 28 ++++---
>  8 files changed, 79 insertions(+), 38 deletions(-)
> 
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h
> index 3c1b2c13398d..320cfa4be633 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h
> @@ -15,6 +15,7 @@ static const struct dpu_caps sm8350_dpu_caps = {
>  	.has_dim_layer = true,
>  	.has_idle_pc = true,
>  	.has_3d_merge = true,
> +	.has_7xxx_intr = true,
>  	.max_linewidth = 4096,
>  	.pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
>  };
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h
> index 5d894cbb0a62..9306c7a115e9 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h
> @@ -13,6 +13,7 @@ static const struct dpu_caps sc7280_dpu_caps = {
>  	.qseed_type = DPU_SSPP_SCALER_QSEED4,
>  	.has_dim_layer = true,
>  	.has_idle_pc = true,
> +	.has_7xxx_intr = true,
>  	.max_linewidth = 2400,
>  	.pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
>  };
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h
> index c3f1ae000a21..fc1e17c495f0 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h
> @@ -15,6 +15,7 @@ static const struct dpu_caps sc8280xp_dpu_caps = {
>  	.has_dim_layer = true,
>  	.has_idle_pc = true,
>  	.has_3d_merge = true,
> +	.has_7xxx_intr = true,
>  	.max_linewidth = 5120,
>  	.pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
>  };
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h
> index 86c2e68ebd2c..eb72411c16db 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h
> @@ -14,6 +14,7 @@ static const struct dpu_caps sm8450_dpu_caps = {
>  	.has_src_split = true,
>  	.has_dim_layer = true,
>  	.has_idle_pc = true,
> +	.has_7xxx_intr = true,
>  	.has_3d_merge = true,
>  	.max_linewidth = 5120,
>  	.pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h
> index 85dc34458b88..8209ca317bdc 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h
> @@ -15,6 +15,7 @@ static const struct dpu_caps sm8550_dpu_caps = {
>  	.has_dim_layer = true,
>  	.has_idle_pc = true,
>  	.has_3d_merge = true,
> +	.has_7xxx_intr = true,
>  	.max_linewidth = 5120,
>  	.pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
>  };
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
> index 677048cc3b7d..72530ebb0ae6 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
> @@ -351,6 +351,7 @@ struct dpu_rotation_cfg {
>   * @has_dim_layer      dim layer feature status
>   * @has_idle_pc        indicate if idle power collapse feature is supported
>   * @has_3d_merge       indicate if 3D merge is supported
> + * @has_7xxx_intr      indicate that INTF/IRQs use addressing for DPU 7.0 and greater
>   * @max_linewidth      max linewidth for sspp
>   * @pixel_ram_size     size of latency hiding and de-tiling buffer in bytes
>   * @max_hdeci_exp      max horizontal decimation supported (max is 2^value)
> @@ -364,6 +365,7 @@ struct dpu_caps {
>  	bool has_dim_layer;
>  	bool has_idle_pc;
>  	bool has_3d_merge;
> +	bool has_7xxx_intr;
>  	/* SSPP limits */
>  	u32 max_linewidth;
>  	u32 pixel_ram_size;
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c
> index 0776b0f6df4f..a03d826bb9ad 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c
> @@ -51,11 +51,9 @@ struct dpu_intr_reg {
>  };
>  
>  /*
> - * struct dpu_intr_reg n-  List of DPU interrupt registers

That could almost be a:

    Fixes: c7314613226a0 ("drm/msm: Add missing struct identifier")

Because no struct is defined here; only an array consuming the struct
that is *already documented right above*.

> - *
> - * When making changes be sure to sync with dpu_hw_intr_reg
> + * dpu_intr_set_legacy -  List of DPU interrupt registers for DPU <= 6.x
>   */
> -static const struct dpu_intr_reg dpu_intr_set[] = {
> +static const struct dpu_intr_reg dpu_intr_set_legacy[] = {
>  	[MDP_SSPP_TOP0_INTR] = {
>  		INTR_CLEAR,
>  		INTR_EN,
> @@ -121,57 +119,78 @@ static const struct dpu_intr_reg dpu_intr_set[] = {
>  		MDP_AD4_INTR_EN_OFF(1),
>  		MDP_AD4_INTR_STATUS_OFF(1),
>  	},
> -	[MDP_INTF0_7xxx_INTR] = {
> +};
> +
> +/*
> + * dpu_intr_set_7xxx -  List of DPU interrupt registers for DPU >= 7.0
> + */
> +static const struct dpu_intr_reg dpu_intr_set_7xxx[] = {
> +	[MDP_SSPP_TOP0_INTR] = {
> +		INTR_CLEAR,
> +		INTR_EN,
> +		INTR_STATUS
> +	},
> +	[MDP_SSPP_TOP0_INTR2] = {
> +		INTR2_CLEAR,
> +		INTR2_EN,
> +		INTR2_STATUS
> +	},
> +	[MDP_SSPP_TOP0_HIST_INTR] = {
> +		HIST_INTR_CLEAR,
> +		HIST_INTR_EN,
> +		HIST_INTR_STATUS
> +	},
> +	[MDP_INTF0_INTR] = {
>  		MDP_INTF_REV_7xxx_INTR_CLEAR(0),
>  		MDP_INTF_REV_7xxx_INTR_EN(0),
>  		MDP_INTF_REV_7xxx_INTR_STATUS(0)
>  	},
> -	[MDP_INTF1_7xxx_INTR] = {
> +	[MDP_INTF1_INTR] = {
>  		MDP_INTF_REV_7xxx_INTR_CLEAR(1),
>  		MDP_INTF_REV_7xxx_INTR_EN(1),
>  		MDP_INTF_REV_7xxx_INTR_STATUS(1)
>  	},
> -	[MDP_INTF1_7xxx_TEAR_INTR] = {
> +	[MDP_INTF1_TEAR_INTR] = {
>  		MDP_INTF_REV_7xxx_INTR_TEAR_CLEAR(1),
>  		MDP_INTF_REV_7xxx_INTR_TEAR_EN(1),
>  		MDP_INTF_REV_7xxx_INTR_TEAR_STATUS(1)
>  	},
> -	[MDP_INTF2_7xxx_INTR] = {
> +	[MDP_INTF2_INTR] = {
>  		MDP_INTF_REV_7xxx_INTR_CLEAR(2),
>  		MDP_INTF_REV_7xxx_INTR_EN(2),
>  		MDP_INTF_REV_7xxx_INTR_STATUS(2)
>  	},
> -	[MDP_INTF2_7xxx_TEAR_INTR] = {
> +	[MDP_INTF2_TEAR_INTR] = {
>  		MDP_INTF_REV_7xxx_INTR_TEAR_CLEAR(2),
>  		MDP_INTF_REV_7xxx_INTR_TEAR_EN(2),
>  		MDP_INTF_REV_7xxx_INTR_TEAR_STATUS(2)
>  	},
> -	[MDP_INTF3_7xxx_INTR] = {
> +	[MDP_INTF3_INTR] = {
>  		MDP_INTF_REV_7xxx_INTR_CLEAR(3),
>  		MDP_INTF_REV_7xxx_INTR_EN(3),
>  		MDP_INTF_REV_7xxx_INTR_STATUS(3)
>  	},
> -	[MDP_INTF4_7xxx_INTR] = {
> +	[MDP_INTF4_INTR] = {
>  		MDP_INTF_REV_7xxx_INTR_CLEAR(4),
>  		MDP_INTF_REV_7xxx_INTR_EN(4),
>  		MDP_INTF_REV_7xxx_INTR_STATUS(4)
>  	},
> -	[MDP_INTF5_7xxx_INTR] = {
> +	[MDP_INTF5_INTR] = {
>  		MDP_INTF_REV_7xxx_INTR_CLEAR(5),
>  		MDP_INTF_REV_7xxx_INTR_EN(5),
>  		MDP_INTF_REV_7xxx_INTR_STATUS(5)
>  	},
> -	[MDP_INTF6_7xxx_INTR] = {
> +	[MDP_INTF6_INTR] = {
>  		MDP_INTF_REV_7xxx_INTR_CLEAR(6),
>  		MDP_INTF_REV_7xxx_INTR_EN(6),
>  		MDP_INTF_REV_7xxx_INTR_STATUS(6)
>  	},
> -	[MDP_INTF7_7xxx_INTR] = {
> +	[MDP_INTF7_INTR] = {
>  		MDP_INTF_REV_7xxx_INTR_CLEAR(7),
>  		MDP_INTF_REV_7xxx_INTR_EN(7),
>  		MDP_INTF_REV_7xxx_INTR_STATUS(7)
>  	},
> -	[MDP_INTF8_7xxx_INTR] = {
> +	[MDP_INTF8_INTR] = {
>  		MDP_INTF_REV_7xxx_INTR_CLEAR(8),
>  		MDP_INTF_REV_7xxx_INTR_EN(8),
>  		MDP_INTF_REV_7xxx_INTR_STATUS(8)
> @@ -216,19 +235,19 @@ irqreturn_t dpu_core_irq(struct msm_kms *kms)
>  		return IRQ_NONE;
>  
>  	spin_lock_irqsave(&intr->irq_lock, irq_flags);
> -	for (reg_idx = 0; reg_idx < ARRAY_SIZE(dpu_intr_set); reg_idx++) {
> +	for (reg_idx = 0; reg_idx < MDP_INTR_MAX; reg_idx++) {
>  		if (!test_bit(reg_idx, &intr->irq_mask))
>  			continue;
>  
>  		/* Read interrupt status */
> -		irq_status = DPU_REG_READ(&intr->hw, dpu_intr_set[reg_idx].status_off);
> +		irq_status = DPU_REG_READ(&intr->hw, intr->intr_set[reg_idx].status_off);
>  
>  		/* Read enable mask */
> -		enable_mask = DPU_REG_READ(&intr->hw, dpu_intr_set[reg_idx].en_off);
> +		enable_mask = DPU_REG_READ(&intr->hw, intr->intr_set[reg_idx].en_off);
>  
>  		/* and clear the interrupt */
>  		if (irq_status)
> -			DPU_REG_WRITE(&intr->hw, dpu_intr_set[reg_idx].clr_off,
> +			DPU_REG_WRITE(&intr->hw, intr->intr_set[reg_idx].clr_off,
>  				     irq_status);
>  
>  		/* Finally update IRQ status based on enable mask */
> @@ -285,7 +304,11 @@ static int dpu_hw_intr_enable_irq_locked(struct dpu_hw_intr *intr, int irq_idx)
>  	assert_spin_locked(&intr->irq_lock);
>  
>  	reg_idx = DPU_IRQ_REG(irq_idx);
> -	reg = &dpu_intr_set[reg_idx];
> +	reg = &intr->intr_set[reg_idx];
> +
> +	/* Is this interrupt register supported on the platform */
> +	if (WARN_ON(!reg->en_off))
> +		return -EINVAL;
>  
>  	cache_irq_mask = intr->cache_irq_mask[reg_idx];
>  	if (cache_irq_mask & DPU_IRQ_MASK(irq_idx)) {
> @@ -334,7 +357,7 @@ static int dpu_hw_intr_disable_irq_locked(struct dpu_hw_intr *intr, int irq_idx)
>  	assert_spin_locked(&intr->irq_lock);
>  
>  	reg_idx = DPU_IRQ_REG(irq_idx);
> -	reg = &dpu_intr_set[reg_idx];
> +	reg = &intr->intr_set[reg_idx];
>  
>  	cache_irq_mask = intr->cache_irq_mask[reg_idx];
>  	if ((cache_irq_mask & DPU_IRQ_MASK(irq_idx)) == 0) {
> @@ -368,10 +391,10 @@ static void dpu_clear_irqs(struct dpu_kms *dpu_kms)
>  	if (!intr)
>  		return;
>  
> -	for (i = 0; i < ARRAY_SIZE(dpu_intr_set); i++) {
> +	for (i = 0; i < MDP_INTR_MAX; i++) {
>  		if (test_bit(i, &intr->irq_mask))
>  			DPU_REG_WRITE(&intr->hw,
> -					dpu_intr_set[i].clr_off, 0xffffffff);
> +					intr->intr_set[i].clr_off, 0xffffffff);
>  	}
>  
>  	/* ensure register writes go through */
> @@ -386,10 +409,10 @@ static void dpu_disable_all_irqs(struct dpu_kms *dpu_kms)
>  	if (!intr)
>  		return;
>  
> -	for (i = 0; i < ARRAY_SIZE(dpu_intr_set); i++) {
> +	for (i = 0; i < MDP_INTR_MAX; i++) {
>  		if (test_bit(i, &intr->irq_mask))
>  			DPU_REG_WRITE(&intr->hw,
> -					dpu_intr_set[i].en_off, 0x00000000);
> +					intr->intr_set[i].en_off, 0x00000000);
>  	}
>  
>  	/* ensure register writes go through */
> @@ -421,10 +444,10 @@ u32 dpu_core_irq_read(struct dpu_kms *dpu_kms, int irq_idx)
>  
>  	reg_idx = DPU_IRQ_REG(irq_idx);
>  	intr_status = DPU_REG_READ(&intr->hw,
> -			dpu_intr_set[reg_idx].status_off) &
> +			intr->intr_set[reg_idx].status_off) &
>  		DPU_IRQ_MASK(irq_idx);
>  	if (intr_status)
> -		DPU_REG_WRITE(&intr->hw, dpu_intr_set[reg_idx].clr_off,
> +		DPU_REG_WRITE(&intr->hw, intr->intr_set[reg_idx].clr_off,
>  				intr_status);
>  
>  	/* ensure register writes go through */
> @@ -448,6 +471,11 @@ struct dpu_hw_intr *dpu_hw_intr_init(void __iomem *addr,
>  	if (!intr)
>  		return ERR_PTR(-ENOMEM);
>  
> +	if (m->caps->has_7xxx_intr)
> +		intr->intr_set = dpu_intr_set_7xxx;
> +	else
> +		intr->intr_set = dpu_intr_set_legacy;
> +
>  	intr->hw.blk_addr = addr + m->mdp[0].base;
>  
>  	intr->total_irqs = nirq;
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h
> index 1f2dabc54c22..f329d6d7f646 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h
> @@ -23,24 +23,29 @@ enum dpu_hw_intr_reg {
>  	MDP_INTF3_INTR,
>  	MDP_INTF4_INTR,
>  	MDP_INTF5_INTR,
> +	MDP_INTF6_INTR,
> +	MDP_INTF7_INTR,
> +	MDP_INTF8_INTR,
>  	MDP_INTF1_TEAR_INTR,
>  	MDP_INTF2_TEAR_INTR,
>  	MDP_AD4_0_INTR,
>  	MDP_AD4_1_INTR,
> -	MDP_INTF0_7xxx_INTR,
> -	MDP_INTF1_7xxx_INTR,
> -	MDP_INTF1_7xxx_TEAR_INTR,
> -	MDP_INTF2_7xxx_INTR,
> -	MDP_INTF2_7xxx_TEAR_INTR,
> -	MDP_INTF3_7xxx_INTR,
> -	MDP_INTF4_7xxx_INTR,
> -	MDP_INTF5_7xxx_INTR,
> -	MDP_INTF6_7xxx_INTR,
> -	MDP_INTF7_7xxx_INTR,
> -	MDP_INTF8_7xxx_INTR,
>  	MDP_INTR_MAX,
>  };
>  
> +/* compatibility */
> +#define MDP_INTF0_7xxx_INTR MDP_INTF0_INTR
> +#define MDP_INTF1_7xxx_INTR MDP_INTF1_INTR
> +#define MDP_INTF2_7xxx_INTR MDP_INTF2_INTR
> +#define MDP_INTF3_7xxx_INTR MDP_INTF3_INTR
> +#define MDP_INTF4_7xxx_INTR MDP_INTF4_INTR
> +#define MDP_INTF5_7xxx_INTR MDP_INTF5_INTR
> +#define MDP_INTF6_7xxx_INTR MDP_INTF6_INTR
> +#define MDP_INTF7_7xxx_INTR MDP_INTF7_INTR
> +#define MDP_INTF8_7xxx_INTR MDP_INTF8_INTR
> +#define MDP_INTF1_7xxx_TEAR_INTR MDP_INTF1_TEAR_INTR
> +#define MDP_INTF2_7xxx_TEAR_INTR MDP_INTF2_TEAR_INTR
> +
>  #define DPU_IRQ_IDX(reg_idx, offset)	(reg_idx * 32 + offset)
>  
>  /**
> @@ -60,6 +65,7 @@ struct dpu_hw_intr {
>  	u32 total_irqs;
>  	spinlock_t irq_lock;
>  	unsigned long irq_mask;
> +	const struct dpu_intr_reg *intr_set;
>  
>  	struct {
>  		void (*cb)(void *arg, int irq_idx);
> -- 
> 2.39.2
> 

Re: [Freedreno] [PATCH v2 3/6] drm/msm/dpu: split interrupt address arrays

[Jeykumar Sankaran]

On 5/22/2023 2:45 PM, Dmitry Baryshkov wrote:
> There is no point in having a single enum (and a single array) for both
> DPU < 7.0 and DPU >= 7.0 interrupt registers. Instead define a single
> enum and two IRQ address arrays.
> 
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> ---
>   .../msm/disp/dpu1/catalog/dpu_7_0_sm8350.h    |  1 +
>   .../msm/disp/dpu1/catalog/dpu_7_2_sc7280.h    |  1 +
>   .../msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h  |  1 +
>   .../msm/disp/dpu1/catalog/dpu_8_1_sm8450.h    |  1 +
>   .../msm/disp/dpu1/catalog/dpu_9_0_sm8550.h    |  1 +
>   .../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h    |  2 +
>   .../gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c | 82 +++++++++++++------
>   .../gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h | 28 ++++---
>   8 files changed, 79 insertions(+), 38 deletions(-)
> 
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h
> index 3c1b2c13398d..320cfa4be633 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h
> @@ -15,6 +15,7 @@ static const struct dpu_caps sm8350_dpu_caps = {
>   	.has_dim_layer = true,
>   	.has_idle_pc = true,
>   	.has_3d_merge = true,
> +	.has_7xxx_intr = true,
>   	.max_linewidth = 4096,
>   	.pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
>   };
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h
> index 5d894cbb0a62..9306c7a115e9 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h
> @@ -13,6 +13,7 @@ static const struct dpu_caps sc7280_dpu_caps = {
>   	.qseed_type = DPU_SSPP_SCALER_QSEED4,
>   	.has_dim_layer = true,
>   	.has_idle_pc = true,
> +	.has_7xxx_intr = true,
>   	.max_linewidth = 2400,
>   	.pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
>   };
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h
> index c3f1ae000a21..fc1e17c495f0 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h
> @@ -15,6 +15,7 @@ static const struct dpu_caps sc8280xp_dpu_caps = {
>   	.has_dim_layer = true,
>   	.has_idle_pc = true,
>   	.has_3d_merge = true,
> +	.has_7xxx_intr = true,
>   	.max_linewidth = 5120,
>   	.pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
>   };
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h
> index 86c2e68ebd2c..eb72411c16db 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h
> @@ -14,6 +14,7 @@ static const struct dpu_caps sm8450_dpu_caps = {
>   	.has_src_split = true,
>   	.has_dim_layer = true,
>   	.has_idle_pc = true,
> +	.has_7xxx_intr = true,
>   	.has_3d_merge = true,
>   	.max_linewidth = 5120,
>   	.pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h
> index 85dc34458b88..8209ca317bdc 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h
> @@ -15,6 +15,7 @@ static const struct dpu_caps sm8550_dpu_caps = {
>   	.has_dim_layer = true,
>   	.has_idle_pc = true,
>   	.has_3d_merge = true,
> +	.has_7xxx_intr = true,
>   	.max_linewidth = 5120,
>   	.pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
>   };
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
> index 677048cc3b7d..72530ebb0ae6 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
> @@ -351,6 +351,7 @@ struct dpu_rotation_cfg {
>    * @has_dim_layer      dim layer feature status
>    * @has_idle_pc        indicate if idle power collapse feature is supported
>    * @has_3d_merge       indicate if 3D merge is supported
> + * @has_7xxx_intr      indicate that INTF/IRQs use addressing for DPU 7.0 and greater

I see the requirement to distinguish feature support based on the DPU 
version in more than one series. Is it a good idea to bring in the DPU 
version info in chipset catalog? This will relieve us from maintaining 
such version flags for individual HW sub-blocks.

Thanks and Regards,
Jeykumar S.

>    * @max_linewidth      max linewidth for sspp
>    * @pixel_ram_size     size of latency hiding and de-tiling buffer in bytes
>    * @max_hdeci_exp      max horizontal decimation supported (max is 2^value)
> @@ -364,6 +365,7 @@ struct dpu_caps {
>   	bool has_dim_layer;
>   	bool has_idle_pc;
>   	bool has_3d_merge;
> +	bool has_7xxx_intr;
>   	/* SSPP limits */
>   	u32 max_linewidth;
>   	u32 pixel_ram_size;
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c
> index 0776b0f6df4f..a03d826bb9ad 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c
> @@ -51,11 +51,9 @@ struct dpu_intr_reg {
>   };
>   
>   /*
> - * struct dpu_intr_reg -  List of DPU interrupt registers
> - *
> - * When making changes be sure to sync with dpu_hw_intr_reg
> + * dpu_intr_set_legacy -  List of DPU interrupt registers for DPU <= 6.x
>    */
> -static const struct dpu_intr_reg dpu_intr_set[] = {
> +static const struct dpu_intr_reg dpu_intr_set_legacy[] = {
>   	[MDP_SSPP_TOP0_INTR] = {
>   		INTR_CLEAR,
>   		INTR_EN,
> @@ -121,57 +119,78 @@ static const struct dpu_intr_reg dpu_intr_set[] = {
>   		MDP_AD4_INTR_EN_OFF(1),
>   		MDP_AD4_INTR_STATUS_OFF(1),
>   	},
> -	[MDP_INTF0_7xxx_INTR] = {
> +};
> +
> +/*
> + * dpu_intr_set_7xxx -  List of DPU interrupt registers for DPU >= 7.0
> + */
> +static const struct dpu_intr_reg dpu_intr_set_7xxx[] = {
> +	[MDP_SSPP_TOP0_INTR] = {
> +		INTR_CLEAR,
> +		INTR_EN,
> +		INTR_STATUS
> +	},
> +	[MDP_SSPP_TOP0_INTR2] = {
> +		INTR2_CLEAR,
> +		INTR2_EN,
> +		INTR2_STATUS
> +	},
> +	[MDP_SSPP_TOP0_HIST_INTR] = {
> +		HIST_INTR_CLEAR,
> +		HIST_INTR_EN,
> +		HIST_INTR_STATUS
> +	},
> +	[MDP_INTF0_INTR] = {
>   		MDP_INTF_REV_7xxx_INTR_CLEAR(0),
>   		MDP_INTF_REV_7xxx_INTR_EN(0),
>   		MDP_INTF_REV_7xxx_INTR_STATUS(0)
>   	},
> -	[MDP_INTF1_7xxx_INTR] = {
> +	[MDP_INTF1_INTR] = {
>   		MDP_INTF_REV_7xxx_INTR_CLEAR(1),
>   		MDP_INTF_REV_7xxx_INTR_EN(1),
>   		MDP_INTF_REV_7xxx_INTR_STATUS(1)
>   	},
> -	[MDP_INTF1_7xxx_TEAR_INTR] = {
> +	[MDP_INTF1_TEAR_INTR] = {
>   		MDP_INTF_REV_7xxx_INTR_TEAR_CLEAR(1),
>   		MDP_INTF_REV_7xxx_INTR_TEAR_EN(1),
>   		MDP_INTF_REV_7xxx_INTR_TEAR_STATUS(1)
>   	},
> -	[MDP_INTF2_7xxx_INTR] = {
> +	[MDP_INTF2_INTR] = {
>   		MDP_INTF_REV_7xxx_INTR_CLEAR(2),
>   		MDP_INTF_REV_7xxx_INTR_EN(2),
>   		MDP_INTF_REV_7xxx_INTR_STATUS(2)
>   	},
> -	[MDP_INTF2_7xxx_TEAR_INTR] = {
> +	[MDP_INTF2_TEAR_INTR] = {
>   		MDP_INTF_REV_7xxx_INTR_TEAR_CLEAR(2),
>   		MDP_INTF_REV_7xxx_INTR_TEAR_EN(2),
>   		MDP_INTF_REV_7xxx_INTR_TEAR_STATUS(2)
>   	},
> -	[MDP_INTF3_7xxx_INTR] = {
> +	[MDP_INTF3_INTR] = {
>   		MDP_INTF_REV_7xxx_INTR_CLEAR(3),
>   		MDP_INTF_REV_7xxx_INTR_EN(3),
>   		MDP_INTF_REV_7xxx_INTR_STATUS(3)
>   	},
> -	[MDP_INTF4_7xxx_INTR] = {
> +	[MDP_INTF4_INTR] = {
>   		MDP_INTF_REV_7xxx_INTR_CLEAR(4),
>   		MDP_INTF_REV_7xxx_INTR_EN(4),
>   		MDP_INTF_REV_7xxx_INTR_STATUS(4)
>   	},
> -	[MDP_INTF5_7xxx_INTR] = {
> +	[MDP_INTF5_INTR] = {
>   		MDP_INTF_REV_7xxx_INTR_CLEAR(5),
>   		MDP_INTF_REV_7xxx_INTR_EN(5),
>   		MDP_INTF_REV_7xxx_INTR_STATUS(5)
>   	},
> -	[MDP_INTF6_7xxx_INTR] = {
> +	[MDP_INTF6_INTR] = {
>   		MDP_INTF_REV_7xxx_INTR_CLEAR(6),
>   		MDP_INTF_REV_7xxx_INTR_EN(6),
>   		MDP_INTF_REV_7xxx_INTR_STATUS(6)
>   	},
> -	[MDP_INTF7_7xxx_INTR] = {
> +	[MDP_INTF7_INTR] = {
>   		MDP_INTF_REV_7xxx_INTR_CLEAR(7),
>   		MDP_INTF_REV_7xxx_INTR_EN(7),
>   		MDP_INTF_REV_7xxx_INTR_STATUS(7)
>   	},
> -	[MDP_INTF8_7xxx_INTR] = {
> +	[MDP_INTF8_INTR] = {
>   		MDP_INTF_REV_7xxx_INTR_CLEAR(8),
>   		MDP_INTF_REV_7xxx_INTR_EN(8),
>   		MDP_INTF_REV_7xxx_INTR_STATUS(8)
> @@ -216,19 +235,19 @@ irqreturn_t dpu_core_irq(struct msm_kms *kms)
>   		return IRQ_NONE;
>   
>   	spin_lock_irqsave(&intr->irq_lock, irq_flags);
> -	for (reg_idx = 0; reg_idx < ARRAY_SIZE(dpu_intr_set); reg_idx++) {
> +	for (reg_idx = 0; reg_idx < MDP_INTR_MAX; reg_idx++) {
>   		if (!test_bit(reg_idx, &intr->irq_mask))
>   			continue;
>   
>   		/* Read interrupt status */
> -		irq_status = DPU_REG_READ(&intr->hw, dpu_intr_set[reg_idx].status_off);
> +		irq_status = DPU_REG_READ(&intr->hw, intr->intr_set[reg_idx].status_off);
>   
>   		/* Read enable mask */
> -		enable_mask = DPU_REG_READ(&intr->hw, dpu_intr_set[reg_idx].en_off);
> +		enable_mask = DPU_REG_READ(&intr->hw, intr->intr_set[reg_idx].en_off);
>   
>   		/* and clear the interrupt */
>   		if (irq_status)
> -			DPU_REG_WRITE(&intr->hw, dpu_intr_set[reg_idx].clr_off,
> +			DPU_REG_WRITE(&intr->hw, intr->intr_set[reg_idx].clr_off,
>   				     irq_status);
>   
>   		/* Finally update IRQ status based on enable mask */
> @@ -285,7 +304,11 @@ static int dpu_hw_intr_enable_irq_locked(struct dpu_hw_intr *intr, int irq_idx)
>   	assert_spin_locked(&intr->irq_lock);
>   
>   	reg_idx = DPU_IRQ_REG(irq_idx);
> -	reg = &dpu_intr_set[reg_idx];
> +	reg = &intr->intr_set[reg_idx];
> +
> +	/* Is this interrupt register supported on the platform */
> +	if (WARN_ON(!reg->en_off))
> +		return -EINVAL;
>   
>   	cache_irq_mask = intr->cache_irq_mask[reg_idx];
>   	if (cache_irq_mask & DPU_IRQ_MASK(irq_idx)) {
> @@ -334,7 +357,7 @@ static int dpu_hw_intr_disable_irq_locked(struct dpu_hw_intr *intr, int irq_idx)
>   	assert_spin_locked(&intr->irq_lock);
>   
>   	reg_idx = DPU_IRQ_REG(irq_idx);
> -	reg = &dpu_intr_set[reg_idx];
> +	reg = &intr->intr_set[reg_idx];
>   
>   	cache_irq_mask = intr->cache_irq_mask[reg_idx];
>   	if ((cache_irq_mask & DPU_IRQ_MASK(irq_idx)) == 0) {
> @@ -368,10 +391,10 @@ static void dpu_clear_irqs(struct dpu_kms *dpu_kms)
>   	if (!intr)
>   		return;
>   
> -	for (i = 0; i < ARRAY_SIZE(dpu_intr_set); i++) {
> +	for (i = 0; i < MDP_INTR_MAX; i++) {
>   		if (test_bit(i, &intr->irq_mask))
>   			DPU_REG_WRITE(&intr->hw,
> -					dpu_intr_set[i].clr_off, 0xffffffff);
> +					intr->intr_set[i].clr_off, 0xffffffff);
>   	}
>   
>   	/* ensure register writes go through */
> @@ -386,10 +409,10 @@ static void dpu_disable_all_irqs(struct dpu_kms *dpu_kms)
>   	if (!intr)
>   		return;
>   
> -	for (i = 0; i < ARRAY_SIZE(dpu_intr_set); i++) {
> +	for (i = 0; i < MDP_INTR_MAX; i++) {
>   		if (test_bit(i, &intr->irq_mask))
>   			DPU_REG_WRITE(&intr->hw,
> -					dpu_intr_set[i].en_off, 0x00000000);
> +					intr->intr_set[i].en_off, 0x00000000);
>   	}
>   
>   	/* ensure register writes go through */
> @@ -421,10 +444,10 @@ u32 dpu_core_irq_read(struct dpu_kms *dpu_kms, int irq_idx)
>   
>   	reg_idx = DPU_IRQ_REG(irq_idx);
>   	intr_status = DPU_REG_READ(&intr->hw,
> -			dpu_intr_set[reg_idx].status_off) &
> +			intr->intr_set[reg_idx].status_off) &
>   		DPU_IRQ_MASK(irq_idx);
>   	if (intr_status)
> -		DPU_REG_WRITE(&intr->hw, dpu_intr_set[reg_idx].clr_off,
> +		DPU_REG_WRITE(&intr->hw, intr->intr_set[reg_idx].clr_off,
>   				intr_status);
>   
>   	/* ensure register writes go through */
> @@ -448,6 +471,11 @@ struct dpu_hw_intr *dpu_hw_intr_init(void __iomem *addr,
>   	if (!intr)
>   		return ERR_PTR(-ENOMEM);
>   
> +	if (m->caps->has_7xxx_intr)
> +		intr->intr_set = dpu_intr_set_7xxx;
> +	else
> +		intr->intr_set = dpu_intr_set_legacy;
> +
>   	intr->hw.blk_addr = addr + m->mdp[0].base;
>   
>   	intr->total_irqs = nirq;
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h
> index 1f2dabc54c22..f329d6d7f646 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h
> @@ -23,24 +23,29 @@ enum dpu_hw_intr_reg {
>   	MDP_INTF3_INTR,
>   	MDP_INTF4_INTR,
>   	MDP_INTF5_INTR,
> +	MDP_INTF6_INTR,
> +	MDP_INTF7_INTR,
> +	MDP_INTF8_INTR,
>   	MDP_INTF1_TEAR_INTR,
>   	MDP_INTF2_TEAR_INTR,
>   	MDP_AD4_0_INTR,
>   	MDP_AD4_1_INTR,
> -	MDP_INTF0_7xxx_INTR,
> -	MDP_INTF1_7xxx_INTR,
> -	MDP_INTF1_7xxx_TEAR_INTR,
> -	MDP_INTF2_7xxx_INTR,
> -	MDP_INTF2_7xxx_TEAR_INTR,
> -	MDP_INTF3_7xxx_INTR,
> -	MDP_INTF4_7xxx_INTR,
> -	MDP_INTF5_7xxx_INTR,
> -	MDP_INTF6_7xxx_INTR,
> -	MDP_INTF7_7xxx_INTR,
> -	MDP_INTF8_7xxx_INTR,
>   	MDP_INTR_MAX,
>   };
>   
> +/* compatibility */
> +#define MDP_INTF0_7xxx_INTR MDP_INTF0_INTR
> +#define MDP_INTF1_7xxx_INTR MDP_INTF1_INTR
> +#define MDP_INTF2_7xxx_INTR MDP_INTF2_INTR
> +#define MDP_INTF3_7xxx_INTR MDP_INTF3_INTR
> +#define MDP_INTF4_7xxx_INTR MDP_INTF4_INTR
> +#define MDP_INTF5_7xxx_INTR MDP_INTF5_INTR
> +#define MDP_INTF6_7xxx_INTR MDP_INTF6_INTR
> +#define MDP_INTF7_7xxx_INTR MDP_INTF7_INTR
> +#define MDP_INTF8_7xxx_INTR MDP_INTF8_INTR
> +#define MDP_INTF1_7xxx_TEAR_INTR MDP_INTF1_TEAR_INTR
> +#define MDP_INTF2_7xxx_TEAR_INTR MDP_INTF2_TEAR_INTR
> +
>   #define DPU_IRQ_IDX(reg_idx, offset)	(reg_idx * 32 + offset)
>   
>   /**
> @@ -60,6 +65,7 @@ struct dpu_hw_intr {
>   	u32 total_irqs;
>   	spinlock_t irq_lock;
>   	unsigned long irq_mask;
> +	const struct dpu_intr_reg *intr_set;
>   
>   	struct {
>   		void (*cb)(void *arg, int irq_idx);

Re: [Freedreno] [PATCH v2 3/6] drm/msm/dpu: split interrupt address arrays

[Dmitry Baryshkov]

On Fri, 26 May 2023 at 00:40, Jeykumar Sankaran
<quic_jeykumar@quicinc.com> wrote:
>
>
>
> On 5/22/2023 2:45 PM, Dmitry Baryshkov wrote:
> > There is no point in having a single enum (and a single array) for both
> > DPU < 7.0 and DPU >= 7.0 interrupt registers. Instead define a single
> > enum and two IRQ address arrays.
> >
> > Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> > ---
> >   .../msm/disp/dpu1/catalog/dpu_7_0_sm8350.h    |  1 +
> >   .../msm/disp/dpu1/catalog/dpu_7_2_sc7280.h    |  1 +
> >   .../msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h  |  1 +
> >   .../msm/disp/dpu1/catalog/dpu_8_1_sm8450.h    |  1 +
> >   .../msm/disp/dpu1/catalog/dpu_9_0_sm8550.h    |  1 +
> >   .../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h    |  2 +
> >   .../gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c | 82 +++++++++++++------
> >   .../gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h | 28 ++++---
> >   8 files changed, 79 insertions(+), 38 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h
> > index 3c1b2c13398d..320cfa4be633 100644
> > --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h
> > +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h
> > @@ -15,6 +15,7 @@ static const struct dpu_caps sm8350_dpu_caps = {
> >       .has_dim_layer = true,
> >       .has_idle_pc = true,
> >       .has_3d_merge = true,
> > +     .has_7xxx_intr = true,
> >       .max_linewidth = 4096,
> >       .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
> >   };
> > diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h
> > index 5d894cbb0a62..9306c7a115e9 100644
> > --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h
> > +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h
> > @@ -13,6 +13,7 @@ static const struct dpu_caps sc7280_dpu_caps = {
> >       .qseed_type = DPU_SSPP_SCALER_QSEED4,
> >       .has_dim_layer = true,
> >       .has_idle_pc = true,
> > +     .has_7xxx_intr = true,
> >       .max_linewidth = 2400,
> >       .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
> >   };
> > diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h
> > index c3f1ae000a21..fc1e17c495f0 100644
> > --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h
> > +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h
> > @@ -15,6 +15,7 @@ static const struct dpu_caps sc8280xp_dpu_caps = {
> >       .has_dim_layer = true,
> >       .has_idle_pc = true,
> >       .has_3d_merge = true,
> > +     .has_7xxx_intr = true,
> >       .max_linewidth = 5120,
> >       .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
> >   };
> > diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h
> > index 86c2e68ebd2c..eb72411c16db 100644
> > --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h
> > +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h
> > @@ -14,6 +14,7 @@ static const struct dpu_caps sm8450_dpu_caps = {
> >       .has_src_split = true,
> >       .has_dim_layer = true,
> >       .has_idle_pc = true,
> > +     .has_7xxx_intr = true,
> >       .has_3d_merge = true,
> >       .max_linewidth = 5120,
> >       .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
> > diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h
> > index 85dc34458b88..8209ca317bdc 100644
> > --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h
> > +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h
> > @@ -15,6 +15,7 @@ static const struct dpu_caps sm8550_dpu_caps = {
> >       .has_dim_layer = true,
> >       .has_idle_pc = true,
> >       .has_3d_merge = true,
> > +     .has_7xxx_intr = true,
> >       .max_linewidth = 5120,
> >       .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
> >   };
> > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
> > index 677048cc3b7d..72530ebb0ae6 100644
> > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
> > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
> > @@ -351,6 +351,7 @@ struct dpu_rotation_cfg {
> >    * @has_dim_layer      dim layer feature status
> >    * @has_idle_pc        indicate if idle power collapse feature is supported
> >    * @has_3d_merge       indicate if 3D merge is supported
> > + * @has_7xxx_intr      indicate that INTF/IRQs use addressing for DPU 7.0 and greater
>
> I see the requirement to distinguish feature support based on the DPU
> version in more than one series. Is it a good idea to bring in the DPU
> version info in chipset catalog? This will relieve us from maintaining
> such version flags for individual HW sub-blocks.

This would not play well with the rest of the driver. The driver
usually does not compute features by DPU revision. Instead it lists
feature flags.

>
> Thanks and Regards,
> Jeykumar S.
>
> >    * @max_linewidth      max linewidth for sspp
> >    * @pixel_ram_size     size of latency hiding and de-tiling buffer in bytes
> >    * @max_hdeci_exp      max horizontal decimation supported (max is 2^value)
> > @@ -364,6 +365,7 @@ struct dpu_caps {
> >       bool has_dim_layer;
> >       bool has_idle_pc;
> >       bool has_3d_merge;
> > +     bool has_7xxx_intr;
> >       /* SSPP limits */
> >       u32 max_linewidth;
> >       u32 pixel_ram_size;
> > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c
> > index 0776b0f6df4f..a03d826bb9ad 100644
> > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c
> > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c
> > @@ -51,11 +51,9 @@ struct dpu_intr_reg {
> >   };
> >
> >   /*
> > - * struct dpu_intr_reg -  List of DPU interrupt registers
> > - *
> > - * When making changes be sure to sync with dpu_hw_intr_reg
> > + * dpu_intr_set_legacy -  List of DPU interrupt registers for DPU <= 6.x
> >    */
> > -static const struct dpu_intr_reg dpu_intr_set[] = {
> > +static const struct dpu_intr_reg dpu_intr_set_legacy[] = {
> >       [MDP_SSPP_TOP0_INTR] = {
> >               INTR_CLEAR,
> >               INTR_EN,
> > @@ -121,57 +119,78 @@ static const struct dpu_intr_reg dpu_intr_set[] = {
> >               MDP_AD4_INTR_EN_OFF(1),
> >               MDP_AD4_INTR_STATUS_OFF(1),
> >       },
> > -     [MDP_INTF0_7xxx_INTR] = {
> > +};
> > +
> > +/*
> > + * dpu_intr_set_7xxx -  List of DPU interrupt registers for DPU >= 7.0
> > + */
> > +static const struct dpu_intr_reg dpu_intr_set_7xxx[] = {
> > +     [MDP_SSPP_TOP0_INTR] = {
> > +             INTR_CLEAR,
> > +             INTR_EN,
> > +             INTR_STATUS
> > +     },
> > +     [MDP_SSPP_TOP0_INTR2] = {
> > +             INTR2_CLEAR,
> > +             INTR2_EN,
> > +             INTR2_STATUS
> > +     },
> > +     [MDP_SSPP_TOP0_HIST_INTR] = {
> > +             HIST_INTR_CLEAR,
> > +             HIST_INTR_EN,
> > +             HIST_INTR_STATUS
> > +     },
> > +     [MDP_INTF0_INTR] = {
> >               MDP_INTF_REV_7xxx_INTR_CLEAR(0),
> >               MDP_INTF_REV_7xxx_INTR_EN(0),
> >               MDP_INTF_REV_7xxx_INTR_STATUS(0)
> >       },
> > -     [MDP_INTF1_7xxx_INTR] = {
> > +     [MDP_INTF1_INTR] = {
> >               MDP_INTF_REV_7xxx_INTR_CLEAR(1),
> >               MDP_INTF_REV_7xxx_INTR_EN(1),
> >               MDP_INTF_REV_7xxx_INTR_STATUS(1)
> >       },
> > -     [MDP_INTF1_7xxx_TEAR_INTR] = {
> > +     [MDP_INTF1_TEAR_INTR] = {
> >               MDP_INTF_REV_7xxx_INTR_TEAR_CLEAR(1),
> >               MDP_INTF_REV_7xxx_INTR_TEAR_EN(1),
> >               MDP_INTF_REV_7xxx_INTR_TEAR_STATUS(1)
> >       },
> > -     [MDP_INTF2_7xxx_INTR] = {
> > +     [MDP_INTF2_INTR] = {
> >               MDP_INTF_REV_7xxx_INTR_CLEAR(2),
> >               MDP_INTF_REV_7xxx_INTR_EN(2),
> >               MDP_INTF_REV_7xxx_INTR_STATUS(2)
> >       },
> > -     [MDP_INTF2_7xxx_TEAR_INTR] = {
> > +     [MDP_INTF2_TEAR_INTR] = {
> >               MDP_INTF_REV_7xxx_INTR_TEAR_CLEAR(2),
> >               MDP_INTF_REV_7xxx_INTR_TEAR_EN(2),
> >               MDP_INTF_REV_7xxx_INTR_TEAR_STATUS(2)
> >       },
> > -     [MDP_INTF3_7xxx_INTR] = {
> > +     [MDP_INTF3_INTR] = {
> >               MDP_INTF_REV_7xxx_INTR_CLEAR(3),
> >               MDP_INTF_REV_7xxx_INTR_EN(3),
> >               MDP_INTF_REV_7xxx_INTR_STATUS(3)
> >       },
> > -     [MDP_INTF4_7xxx_INTR] = {
> > +     [MDP_INTF4_INTR] = {
> >               MDP_INTF_REV_7xxx_INTR_CLEAR(4),
> >               MDP_INTF_REV_7xxx_INTR_EN(4),
> >               MDP_INTF_REV_7xxx_INTR_STATUS(4)
> >       },
> > -     [MDP_INTF5_7xxx_INTR] = {
> > +     [MDP_INTF5_INTR] = {
> >               MDP_INTF_REV_7xxx_INTR_CLEAR(5),
> >               MDP_INTF_REV_7xxx_INTR_EN(5),
> >               MDP_INTF_REV_7xxx_INTR_STATUS(5)
> >       },
> > -     [MDP_INTF6_7xxx_INTR] = {
> > +     [MDP_INTF6_INTR] = {
> >               MDP_INTF_REV_7xxx_INTR_CLEAR(6),
> >               MDP_INTF_REV_7xxx_INTR_EN(6),
> >               MDP_INTF_REV_7xxx_INTR_STATUS(6)
> >       },
> > -     [MDP_INTF7_7xxx_INTR] = {
> > +     [MDP_INTF7_INTR] = {
> >               MDP_INTF_REV_7xxx_INTR_CLEAR(7),
> >               MDP_INTF_REV_7xxx_INTR_EN(7),
> >               MDP_INTF_REV_7xxx_INTR_STATUS(7)
> >       },
> > -     [MDP_INTF8_7xxx_INTR] = {
> > +     [MDP_INTF8_INTR] = {
> >               MDP_INTF_REV_7xxx_INTR_CLEAR(8),
> >               MDP_INTF_REV_7xxx_INTR_EN(8),
> >               MDP_INTF_REV_7xxx_INTR_STATUS(8)
> > @@ -216,19 +235,19 @@ irqreturn_t dpu_core_irq(struct msm_kms *kms)
> >               return IRQ_NONE;
> >
> >       spin_lock_irqsave(&intr->irq_lock, irq_flags);
> > -     for (reg_idx = 0; reg_idx < ARRAY_SIZE(dpu_intr_set); reg_idx++) {
> > +     for (reg_idx = 0; reg_idx < MDP_INTR_MAX; reg_idx++) {
> >               if (!test_bit(reg_idx, &intr->irq_mask))
> >                       continue;
> >
> >               /* Read interrupt status */
> > -             irq_status = DPU_REG_READ(&intr->hw, dpu_intr_set[reg_idx].status_off);
> > +             irq_status = DPU_REG_READ(&intr->hw, intr->intr_set[reg_idx].status_off);
> >
> >               /* Read enable mask */
> > -             enable_mask = DPU_REG_READ(&intr->hw, dpu_intr_set[reg_idx].en_off);
> > +             enable_mask = DPU_REG_READ(&intr->hw, intr->intr_set[reg_idx].en_off);
> >
> >               /* and clear the interrupt */
> >               if (irq_status)
> > -                     DPU_REG_WRITE(&intr->hw, dpu_intr_set[reg_idx].clr_off,
> > +                     DPU_REG_WRITE(&intr->hw, intr->intr_set[reg_idx].clr_off,
> >                                    irq_status);
> >
> >               /* Finally update IRQ status based on enable mask */
> > @@ -285,7 +304,11 @@ static int dpu_hw_intr_enable_irq_locked(struct dpu_hw_intr *intr, int irq_idx)
> >       assert_spin_locked(&intr->irq_lock);
> >
> >       reg_idx = DPU_IRQ_REG(irq_idx);
> > -     reg = &dpu_intr_set[reg_idx];
> > +     reg = &intr->intr_set[reg_idx];
> > +
> > +     /* Is this interrupt register supported on the platform */
> > +     if (WARN_ON(!reg->en_off))
> > +             return -EINVAL;
> >
> >       cache_irq_mask = intr->cache_irq_mask[reg_idx];
> >       if (cache_irq_mask & DPU_IRQ_MASK(irq_idx)) {
> > @@ -334,7 +357,7 @@ static int dpu_hw_intr_disable_irq_locked(struct dpu_hw_intr *intr, int irq_idx)
> >       assert_spin_locked(&intr->irq_lock);
> >
> >       reg_idx = DPU_IRQ_REG(irq_idx);
> > -     reg = &dpu_intr_set[reg_idx];
> > +     reg = &intr->intr_set[reg_idx];
> >
> >       cache_irq_mask = intr->cache_irq_mask[reg_idx];
> >       if ((cache_irq_mask & DPU_IRQ_MASK(irq_idx)) == 0) {
> > @@ -368,10 +391,10 @@ static void dpu_clear_irqs(struct dpu_kms *dpu_kms)
> >       if (!intr)
> >               return;
> >
> > -     for (i = 0; i < ARRAY_SIZE(dpu_intr_set); i++) {
> > +     for (i = 0; i < MDP_INTR_MAX; i++) {
> >               if (test_bit(i, &intr->irq_mask))
> >                       DPU_REG_WRITE(&intr->hw,
> > -                                     dpu_intr_set[i].clr_off, 0xffffffff);
> > +                                     intr->intr_set[i].clr_off, 0xffffffff);
> >       }
> >
> >       /* ensure register writes go through */
> > @@ -386,10 +409,10 @@ static void dpu_disable_all_irqs(struct dpu_kms *dpu_kms)
> >       if (!intr)
> >               return;
> >
> > -     for (i = 0; i < ARRAY_SIZE(dpu_intr_set); i++) {
> > +     for (i = 0; i < MDP_INTR_MAX; i++) {
> >               if (test_bit(i, &intr->irq_mask))
> >                       DPU_REG_WRITE(&intr->hw,
> > -                                     dpu_intr_set[i].en_off, 0x00000000);
> > +                                     intr->intr_set[i].en_off, 0x00000000);
> >       }
> >
> >       /* ensure register writes go through */
> > @@ -421,10 +444,10 @@ u32 dpu_core_irq_read(struct dpu_kms *dpu_kms, int irq_idx)
> >
> >       reg_idx = DPU_IRQ_REG(irq_idx);
> >       intr_status = DPU_REG_READ(&intr->hw,
> > -                     dpu_intr_set[reg_idx].status_off) &
> > +                     intr->intr_set[reg_idx].status_off) &
> >               DPU_IRQ_MASK(irq_idx);
> >       if (intr_status)
> > -             DPU_REG_WRITE(&intr->hw, dpu_intr_set[reg_idx].clr_off,
> > +             DPU_REG_WRITE(&intr->hw, intr->intr_set[reg_idx].clr_off,
> >                               intr_status);
> >
> >       /* ensure register writes go through */
> > @@ -448,6 +471,11 @@ struct dpu_hw_intr *dpu_hw_intr_init(void __iomem *addr,
> >       if (!intr)
> >               return ERR_PTR(-ENOMEM);
> >
> > +     if (m->caps->has_7xxx_intr)
> > +             intr->intr_set = dpu_intr_set_7xxx;
> > +     else
> > +             intr->intr_set = dpu_intr_set_legacy;
> > +
> >       intr->hw.blk_addr = addr + m->mdp[0].base;
> >
> >       intr->total_irqs = nirq;
> > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h
> > index 1f2dabc54c22..f329d6d7f646 100644
> > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h
> > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h
> > @@ -23,24 +23,29 @@ enum dpu_hw_intr_reg {
> >       MDP_INTF3_INTR,
> >       MDP_INTF4_INTR,
> >       MDP_INTF5_INTR,
> > +     MDP_INTF6_INTR,
> > +     MDP_INTF7_INTR,
> > +     MDP_INTF8_INTR,
> >       MDP_INTF1_TEAR_INTR,
> >       MDP_INTF2_TEAR_INTR,
> >       MDP_AD4_0_INTR,
> >       MDP_AD4_1_INTR,
> > -     MDP_INTF0_7xxx_INTR,
> > -     MDP_INTF1_7xxx_INTR,
> > -     MDP_INTF1_7xxx_TEAR_INTR,
> > -     MDP_INTF2_7xxx_INTR,
> > -     MDP_INTF2_7xxx_TEAR_INTR,
> > -     MDP_INTF3_7xxx_INTR,
> > -     MDP_INTF4_7xxx_INTR,
> > -     MDP_INTF5_7xxx_INTR,
> > -     MDP_INTF6_7xxx_INTR,
> > -     MDP_INTF7_7xxx_INTR,
> > -     MDP_INTF8_7xxx_INTR,
> >       MDP_INTR_MAX,
> >   };
> >
> > +/* compatibility */
> > +#define MDP_INTF0_7xxx_INTR MDP_INTF0_INTR
> > +#define MDP_INTF1_7xxx_INTR MDP_INTF1_INTR
> > +#define MDP_INTF2_7xxx_INTR MDP_INTF2_INTR
> > +#define MDP_INTF3_7xxx_INTR MDP_INTF3_INTR
> > +#define MDP_INTF4_7xxx_INTR MDP_INTF4_INTR
> > +#define MDP_INTF5_7xxx_INTR MDP_INTF5_INTR
> > +#define MDP_INTF6_7xxx_INTR MDP_INTF6_INTR
> > +#define MDP_INTF7_7xxx_INTR MDP_INTF7_INTR
> > +#define MDP_INTF8_7xxx_INTR MDP_INTF8_INTR
> > +#define MDP_INTF1_7xxx_TEAR_INTR MDP_INTF1_TEAR_INTR
> > +#define MDP_INTF2_7xxx_TEAR_INTR MDP_INTF2_TEAR_INTR
> > +
> >   #define DPU_IRQ_IDX(reg_idx, offset)        (reg_idx * 32 + offset)
> >
> >   /**
> > @@ -60,6 +65,7 @@ struct dpu_hw_intr {
> >       u32 total_irqs;
> >       spinlock_t irq_lock;
> >       unsigned long irq_mask;
> > +     const struct dpu_intr_reg *intr_set;
> >
> >       struct {
> >               void (*cb)(void *arg, int irq_idx);



-- 
With best wishes
Dmitry

Re: [Freedreno] [PATCH v2 3/6] drm/msm/dpu: split interrupt address arrays

[Abhinav Kumar]

On 5/25/2023 3:30 PM, Dmitry Baryshkov wrote:
> On Fri, 26 May 2023 at 00:40, Jeykumar Sankaran
> <quic_jeykumar@quicinc.com> wrote:
>>
>>
>>
>> On 5/22/2023 2:45 PM, Dmitry Baryshkov wrote:
>>> There is no point in having a single enum (and a single array) for both
>>> DPU < 7.0 and DPU >= 7.0 interrupt registers. Instead define a single
>>> enum and two IRQ address arrays.
>>>
>>> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
>>> ---
>>>    .../msm/disp/dpu1/catalog/dpu_7_0_sm8350.h    |  1 +
>>>    .../msm/disp/dpu1/catalog/dpu_7_2_sc7280.h    |  1 +
>>>    .../msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h  |  1 +
>>>    .../msm/disp/dpu1/catalog/dpu_8_1_sm8450.h    |  1 +
>>>    .../msm/disp/dpu1/catalog/dpu_9_0_sm8550.h    |  1 +
>>>    .../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h    |  2 +
>>>    .../gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c | 82 +++++++++++++------
>>>    .../gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h | 28 ++++---
>>>    8 files changed, 79 insertions(+), 38 deletions(-)
>>>
>>> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h
>>> index 3c1b2c13398d..320cfa4be633 100644
>>> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h
>>> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h
>>> @@ -15,6 +15,7 @@ static const struct dpu_caps sm8350_dpu_caps = {
>>>        .has_dim_layer = true,
>>>        .has_idle_pc = true,
>>>        .has_3d_merge = true,
>>> +     .has_7xxx_intr = true,
>>>        .max_linewidth = 4096,
>>>        .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
>>>    };
>>> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h
>>> index 5d894cbb0a62..9306c7a115e9 100644
>>> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h
>>> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h
>>> @@ -13,6 +13,7 @@ static const struct dpu_caps sc7280_dpu_caps = {
>>>        .qseed_type = DPU_SSPP_SCALER_QSEED4,
>>>        .has_dim_layer = true,
>>>        .has_idle_pc = true,
>>> +     .has_7xxx_intr = true,
>>>        .max_linewidth = 2400,
>>>        .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
>>>    };
>>> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h
>>> index c3f1ae000a21..fc1e17c495f0 100644
>>> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h
>>> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h
>>> @@ -15,6 +15,7 @@ static const struct dpu_caps sc8280xp_dpu_caps = {
>>>        .has_dim_layer = true,
>>>        .has_idle_pc = true,
>>>        .has_3d_merge = true,
>>> +     .has_7xxx_intr = true,
>>>        .max_linewidth = 5120,
>>>        .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
>>>    };
>>> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h
>>> index 86c2e68ebd2c..eb72411c16db 100644
>>> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h
>>> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h
>>> @@ -14,6 +14,7 @@ static const struct dpu_caps sm8450_dpu_caps = {
>>>        .has_src_split = true,
>>>        .has_dim_layer = true,
>>>        .has_idle_pc = true,
>>> +     .has_7xxx_intr = true,
>>>        .has_3d_merge = true,
>>>        .max_linewidth = 5120,
>>>        .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
>>> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h
>>> index 85dc34458b88..8209ca317bdc 100644
>>> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h
>>> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h
>>> @@ -15,6 +15,7 @@ static const struct dpu_caps sm8550_dpu_caps = {
>>>        .has_dim_layer = true,
>>>        .has_idle_pc = true,
>>>        .has_3d_merge = true,
>>> +     .has_7xxx_intr = true,
>>>        .max_linewidth = 5120,
>>>        .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
>>>    };
>>> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
>>> index 677048cc3b7d..72530ebb0ae6 100644
>>> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
>>> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
>>> @@ -351,6 +351,7 @@ struct dpu_rotation_cfg {
>>>     * @has_dim_layer      dim layer feature status
>>>     * @has_idle_pc        indicate if idle power collapse feature is supported
>>>     * @has_3d_merge       indicate if 3D merge is supported
>>> + * @has_7xxx_intr      indicate that INTF/IRQs use addressing for DPU 7.0 and greater
>>
>> I see the requirement to distinguish feature support based on the DPU
>> version in more than one series. Is it a good idea to bring in the DPU
>> version info in chipset catalog? This will relieve us from maintaining
>> such version flags for individual HW sub-blocks.
> 
> This would not play well with the rest of the driver. The driver
> usually does not compute features by DPU revision. Instead it lists
> feature flags.
> 

So I am increasingly seeing examples such as data_compress, widebus 
where it looks like version based enablement in the code will be just 
more efficient. For example.

if (DPU_MAJOR_VER > xxx && DPU_MAJOR_VER < yyy)
	enable data_compress;

will be much easier to do than adding catalog entry for each chipset for 
these bit level details of registers especially when some of these 
cannot be considered as catalog features.

Thats why I am wondering that, we dont need to add the revision based 
cfg picking anymore and rely on the compatible but in the dpu_mdss_cfg 
perhaps add a .core_rev.

We will still stick to catalog based feature bits when its actually 
indeed a feature.

Thoughts?

>>
>> Thanks and Regards,
>> Jeykumar S.
>>
>>>     * @max_linewidth      max linewidth for sspp
>>>     * @pixel_ram_size     size of latency hiding and de-tiling buffer in bytes
>>>     * @max_hdeci_exp      max horizontal decimation supported (max is 2^value)
>>> @@ -364,6 +365,7 @@ struct dpu_caps {
>>>        bool has_dim_layer;
>>>        bool has_idle_pc;
>>>        bool has_3d_merge;
>>> +     bool has_7xxx_intr;
>>>        /* SSPP limits */
>>>        u32 max_linewidth;
>>>        u32 pixel_ram_size;
>>> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c
>>> index 0776b0f6df4f..a03d826bb9ad 100644
>>> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c
>>> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c
>>> @@ -51,11 +51,9 @@ struct dpu_intr_reg {
>>>    };
>>>
>>>    /*
>>> - * struct dpu_intr_reg -  List of DPU interrupt registers
>>> - *
>>> - * When making changes be sure to sync with dpu_hw_intr_reg
>>> + * dpu_intr_set_legacy -  List of DPU interrupt registers for DPU <= 6.x
>>>     */
>>> -static const struct dpu_intr_reg dpu_intr_set[] = {
>>> +static const struct dpu_intr_reg dpu_intr_set_legacy[] = {
>>>        [MDP_SSPP_TOP0_INTR] = {
>>>                INTR_CLEAR,
>>>                INTR_EN,
>>> @@ -121,57 +119,78 @@ static const struct dpu_intr_reg dpu_intr_set[] = {
>>>                MDP_AD4_INTR_EN_OFF(1),
>>>                MDP_AD4_INTR_STATUS_OFF(1),
>>>        },
>>> -     [MDP_INTF0_7xxx_INTR] = {
>>> +};
>>> +
>>> +/*
>>> + * dpu_intr_set_7xxx -  List of DPU interrupt registers for DPU >= 7.0
>>> + */
>>> +static const struct dpu_intr_reg dpu_intr_set_7xxx[] = {
>>> +     [MDP_SSPP_TOP0_INTR] = {
>>> +             INTR_CLEAR,
>>> +             INTR_EN,
>>> +             INTR_STATUS
>>> +     },
>>> +     [MDP_SSPP_TOP0_INTR2] = {
>>> +             INTR2_CLEAR,
>>> +             INTR2_EN,
>>> +             INTR2_STATUS
>>> +     },
>>> +     [MDP_SSPP_TOP0_HIST_INTR] = {
>>> +             HIST_INTR_CLEAR,
>>> +             HIST_INTR_EN,
>>> +             HIST_INTR_STATUS
>>> +     },
>>> +     [MDP_INTF0_INTR] = {
>>>                MDP_INTF_REV_7xxx_INTR_CLEAR(0),
>>>                MDP_INTF_REV_7xxx_INTR_EN(0),
>>>                MDP_INTF_REV_7xxx_INTR_STATUS(0)
>>>        },
>>> -     [MDP_INTF1_7xxx_INTR] = {
>>> +     [MDP_INTF1_INTR] = {
>>>                MDP_INTF_REV_7xxx_INTR_CLEAR(1),
>>>                MDP_INTF_REV_7xxx_INTR_EN(1),
>>>                MDP_INTF_REV_7xxx_INTR_STATUS(1)
>>>        },
>>> -     [MDP_INTF1_7xxx_TEAR_INTR] = {
>>> +     [MDP_INTF1_TEAR_INTR] = {
>>>                MDP_INTF_REV_7xxx_INTR_TEAR_CLEAR(1),
>>>                MDP_INTF_REV_7xxx_INTR_TEAR_EN(1),
>>>                MDP_INTF_REV_7xxx_INTR_TEAR_STATUS(1)
>>>        },
>>> -     [MDP_INTF2_7xxx_INTR] = {
>>> +     [MDP_INTF2_INTR] = {
>>>                MDP_INTF_REV_7xxx_INTR_CLEAR(2),
>>>                MDP_INTF_REV_7xxx_INTR_EN(2),
>>>                MDP_INTF_REV_7xxx_INTR_STATUS(2)
>>>        },
>>> -     [MDP_INTF2_7xxx_TEAR_INTR] = {
>>> +     [MDP_INTF2_TEAR_INTR] = {
>>>                MDP_INTF_REV_7xxx_INTR_TEAR_CLEAR(2),
>>>                MDP_INTF_REV_7xxx_INTR_TEAR_EN(2),
>>>                MDP_INTF_REV_7xxx_INTR_TEAR_STATUS(2)
>>>        },
>>> -     [MDP_INTF3_7xxx_INTR] = {
>>> +     [MDP_INTF3_INTR] = {
>>>                MDP_INTF_REV_7xxx_INTR_CLEAR(3),
>>>                MDP_INTF_REV_7xxx_INTR_EN(3),
>>>                MDP_INTF_REV_7xxx_INTR_STATUS(3)
>>>        },
>>> -     [MDP_INTF4_7xxx_INTR] = {
>>> +     [MDP_INTF4_INTR] = {
>>>                MDP_INTF_REV_7xxx_INTR_CLEAR(4),
>>>                MDP_INTF_REV_7xxx_INTR_EN(4),
>>>                MDP_INTF_REV_7xxx_INTR_STATUS(4)
>>>        },
>>> -     [MDP_INTF5_7xxx_INTR] = {
>>> +     [MDP_INTF5_INTR] = {
>>>                MDP_INTF_REV_7xxx_INTR_CLEAR(5),
>>>                MDP_INTF_REV_7xxx_INTR_EN(5),
>>>                MDP_INTF_REV_7xxx_INTR_STATUS(5)
>>>        },
>>> -     [MDP_INTF6_7xxx_INTR] = {
>>> +     [MDP_INTF6_INTR] = {
>>>                MDP_INTF_REV_7xxx_INTR_CLEAR(6),
>>>                MDP_INTF_REV_7xxx_INTR_EN(6),
>>>                MDP_INTF_REV_7xxx_INTR_STATUS(6)
>>>        },
>>> -     [MDP_INTF7_7xxx_INTR] = {
>>> +     [MDP_INTF7_INTR] = {
>>>                MDP_INTF_REV_7xxx_INTR_CLEAR(7),
>>>                MDP_INTF_REV_7xxx_INTR_EN(7),
>>>                MDP_INTF_REV_7xxx_INTR_STATUS(7)
>>>        },
>>> -     [MDP_INTF8_7xxx_INTR] = {
>>> +     [MDP_INTF8_INTR] = {
>>>                MDP_INTF_REV_7xxx_INTR_CLEAR(8),
>>>                MDP_INTF_REV_7xxx_INTR_EN(8),
>>>                MDP_INTF_REV_7xxx_INTR_STATUS(8)
>>> @@ -216,19 +235,19 @@ irqreturn_t dpu_core_irq(struct msm_kms *kms)
>>>                return IRQ_NONE;
>>>
>>>        spin_lock_irqsave(&intr->irq_lock, irq_flags);
>>> -     for (reg_idx = 0; reg_idx < ARRAY_SIZE(dpu_intr_set); reg_idx++) {
>>> +     for (reg_idx = 0; reg_idx < MDP_INTR_MAX; reg_idx++) {
>>>                if (!test_bit(reg_idx, &intr->irq_mask))
>>>                        continue;
>>>
>>>                /* Read interrupt status */
>>> -             irq_status = DPU_REG_READ(&intr->hw, dpu_intr_set[reg_idx].status_off);
>>> +             irq_status = DPU_REG_READ(&intr->hw, intr->intr_set[reg_idx].status_off);
>>>
>>>                /* Read enable mask */
>>> -             enable_mask = DPU_REG_READ(&intr->hw, dpu_intr_set[reg_idx].en_off);
>>> +             enable_mask = DPU_REG_READ(&intr->hw, intr->intr_set[reg_idx].en_off);
>>>
>>>                /* and clear the interrupt */
>>>                if (irq_status)
>>> -                     DPU_REG_WRITE(&intr->hw, dpu_intr_set[reg_idx].clr_off,
>>> +                     DPU_REG_WRITE(&intr->hw, intr->intr_set[reg_idx].clr_off,
>>>                                     irq_status);
>>>
>>>                /* Finally update IRQ status based on enable mask */
>>> @@ -285,7 +304,11 @@ static int dpu_hw_intr_enable_irq_locked(struct dpu_hw_intr *intr, int irq_idx)
>>>        assert_spin_locked(&intr->irq_lock);
>>>
>>>        reg_idx = DPU_IRQ_REG(irq_idx);
>>> -     reg = &dpu_intr_set[reg_idx];
>>> +     reg = &intr->intr_set[reg_idx];
>>> +
>>> +     /* Is this interrupt register supported on the platform */
>>> +     if (WARN_ON(!reg->en_off))
>>> +             return -EINVAL;
>>>
>>>        cache_irq_mask = intr->cache_irq_mask[reg_idx];
>>>        if (cache_irq_mask & DPU_IRQ_MASK(irq_idx)) {
>>> @@ -334,7 +357,7 @@ static int dpu_hw_intr_disable_irq_locked(struct dpu_hw_intr *intr, int irq_idx)
>>>        assert_spin_locked(&intr->irq_lock);
>>>
>>>        reg_idx = DPU_IRQ_REG(irq_idx);
>>> -     reg = &dpu_intr_set[reg_idx];
>>> +     reg = &intr->intr_set[reg_idx];
>>>
>>>        cache_irq_mask = intr->cache_irq_mask[reg_idx];
>>>        if ((cache_irq_mask & DPU_IRQ_MASK(irq_idx)) == 0) {
>>> @@ -368,10 +391,10 @@ static void dpu_clear_irqs(struct dpu_kms *dpu_kms)
>>>        if (!intr)
>>>                return;
>>>
>>> -     for (i = 0; i < ARRAY_SIZE(dpu_intr_set); i++) {
>>> +     for (i = 0; i < MDP_INTR_MAX; i++) {
>>>                if (test_bit(i, &intr->irq_mask))
>>>                        DPU_REG_WRITE(&intr->hw,
>>> -                                     dpu_intr_set[i].clr_off, 0xffffffff);
>>> +                                     intr->intr_set[i].clr_off, 0xffffffff);
>>>        }
>>>
>>>        /* ensure register writes go through */
>>> @@ -386,10 +409,10 @@ static void dpu_disable_all_irqs(struct dpu_kms *dpu_kms)
>>>        if (!intr)
>>>                return;
>>>
>>> -     for (i = 0; i < ARRAY_SIZE(dpu_intr_set); i++) {
>>> +     for (i = 0; i < MDP_INTR_MAX; i++) {
>>>                if (test_bit(i, &intr->irq_mask))
>>>                        DPU_REG_WRITE(&intr->hw,
>>> -                                     dpu_intr_set[i].en_off, 0x00000000);
>>> +                                     intr->intr_set[i].en_off, 0x00000000);
>>>        }
>>>
>>>        /* ensure register writes go through */
>>> @@ -421,10 +444,10 @@ u32 dpu_core_irq_read(struct dpu_kms *dpu_kms, int irq_idx)
>>>
>>>        reg_idx = DPU_IRQ_REG(irq_idx);
>>>        intr_status = DPU_REG_READ(&intr->hw,
>>> -                     dpu_intr_set[reg_idx].status_off) &
>>> +                     intr->intr_set[reg_idx].status_off) &
>>>                DPU_IRQ_MASK(irq_idx);
>>>        if (intr_status)
>>> -             DPU_REG_WRITE(&intr->hw, dpu_intr_set[reg_idx].clr_off,
>>> +             DPU_REG_WRITE(&intr->hw, intr->intr_set[reg_idx].clr_off,
>>>                                intr_status);
>>>
>>>        /* ensure register writes go through */
>>> @@ -448,6 +471,11 @@ struct dpu_hw_intr *dpu_hw_intr_init(void __iomem *addr,
>>>        if (!intr)
>>>                return ERR_PTR(-ENOMEM);
>>>
>>> +     if (m->caps->has_7xxx_intr)
>>> +             intr->intr_set = dpu_intr_set_7xxx;
>>> +     else
>>> +             intr->intr_set = dpu_intr_set_legacy;
>>> +
>>>        intr->hw.blk_addr = addr + m->mdp[0].base;
>>>
>>>        intr->total_irqs = nirq;
>>> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h
>>> index 1f2dabc54c22..f329d6d7f646 100644
>>> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h
>>> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h
>>> @@ -23,24 +23,29 @@ enum dpu_hw_intr_reg {
>>>        MDP_INTF3_INTR,
>>>        MDP_INTF4_INTR,
>>>        MDP_INTF5_INTR,
>>> +     MDP_INTF6_INTR,
>>> +     MDP_INTF7_INTR,
>>> +     MDP_INTF8_INTR,
>>>        MDP_INTF1_TEAR_INTR,
>>>        MDP_INTF2_TEAR_INTR,
>>>        MDP_AD4_0_INTR,
>>>        MDP_AD4_1_INTR,
>>> -     MDP_INTF0_7xxx_INTR,
>>> -     MDP_INTF1_7xxx_INTR,
>>> -     MDP_INTF1_7xxx_TEAR_INTR,
>>> -     MDP_INTF2_7xxx_INTR,
>>> -     MDP_INTF2_7xxx_TEAR_INTR,
>>> -     MDP_INTF3_7xxx_INTR,
>>> -     MDP_INTF4_7xxx_INTR,
>>> -     MDP_INTF5_7xxx_INTR,
>>> -     MDP_INTF6_7xxx_INTR,
>>> -     MDP_INTF7_7xxx_INTR,
>>> -     MDP_INTF8_7xxx_INTR,
>>>        MDP_INTR_MAX,
>>>    };
>>>
>>> +/* compatibility */
>>> +#define MDP_INTF0_7xxx_INTR MDP_INTF0_INTR
>>> +#define MDP_INTF1_7xxx_INTR MDP_INTF1_INTR
>>> +#define MDP_INTF2_7xxx_INTR MDP_INTF2_INTR
>>> +#define MDP_INTF3_7xxx_INTR MDP_INTF3_INTR
>>> +#define MDP_INTF4_7xxx_INTR MDP_INTF4_INTR
>>> +#define MDP_INTF5_7xxx_INTR MDP_INTF5_INTR
>>> +#define MDP_INTF6_7xxx_INTR MDP_INTF6_INTR
>>> +#define MDP_INTF7_7xxx_INTR MDP_INTF7_INTR
>>> +#define MDP_INTF8_7xxx_INTR MDP_INTF8_INTR
>>> +#define MDP_INTF1_7xxx_TEAR_INTR MDP_INTF1_TEAR_INTR
>>> +#define MDP_INTF2_7xxx_TEAR_INTR MDP_INTF2_TEAR_INTR
>>> +
>>>    #define DPU_IRQ_IDX(reg_idx, offset)        (reg_idx * 32 + offset)
>>>
>>>    /**
>>> @@ -60,6 +65,7 @@ struct dpu_hw_intr {
>>>        u32 total_irqs;
>>>        spinlock_t irq_lock;
>>>        unsigned long irq_mask;
>>> +     const struct dpu_intr_reg *intr_set;
>>>
>>>        struct {
>>>                void (*cb)(void *arg, int irq_idx);
> 
> 
> 

Re: [Freedreno] [PATCH v2 3/6] drm/msm/dpu: split interrupt address arrays

[Dmitry Baryshkov]

On Fri, 26 May 2023 at 01:42, Abhinav Kumar <quic_abhinavk@quicinc.com> wrote:
> On 5/25/2023 3:30 PM, Dmitry Baryshkov wrote:
> > On Fri, 26 May 2023 at 00:40, Jeykumar Sankaran
> > <quic_jeykumar@quicinc.com> wrote:
> >> On 5/22/2023 2:45 PM, Dmitry Baryshkov wrote:
> >>> There is no point in having a single enum (and a single array) for both
> >>> DPU < 7.0 and DPU >= 7.0 interrupt registers. Instead define a single
> >>> enum and two IRQ address arrays.
> >>>
> >>> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> >>> ---
> >>>    .../msm/disp/dpu1/catalog/dpu_7_0_sm8350.h    |  1 +
> >>>    .../msm/disp/dpu1/catalog/dpu_7_2_sc7280.h    |  1 +
> >>>    .../msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h  |  1 +
> >>>    .../msm/disp/dpu1/catalog/dpu_8_1_sm8450.h    |  1 +
> >>>    .../msm/disp/dpu1/catalog/dpu_9_0_sm8550.h    |  1 +
> >>>    .../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h    |  2 +
> >>>    .../gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c | 82 +++++++++++++------
> >>>    .../gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h | 28 ++++---
> >>>    8 files changed, 79 insertions(+), 38 deletions(-)
> >>>
> >>> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h
> >>> index 3c1b2c13398d..320cfa4be633 100644
> >>> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h
> >>> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h
> >>> @@ -15,6 +15,7 @@ static const struct dpu_caps sm8350_dpu_caps = {
> >>>        .has_dim_layer = true,
> >>>        .has_idle_pc = true,
> >>>        .has_3d_merge = true,
> >>> +     .has_7xxx_intr = true,
> >>>        .max_linewidth = 4096,
> >>>        .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
> >>>    };
> >>> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h
> >>> index 5d894cbb0a62..9306c7a115e9 100644
> >>> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h
> >>> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h
> >>> @@ -13,6 +13,7 @@ static const struct dpu_caps sc7280_dpu_caps = {
> >>>        .qseed_type = DPU_SSPP_SCALER_QSEED4,
> >>>        .has_dim_layer = true,
> >>>        .has_idle_pc = true,
> >>> +     .has_7xxx_intr = true,
> >>>        .max_linewidth = 2400,
> >>>        .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
> >>>    };
> >>> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h
> >>> index c3f1ae000a21..fc1e17c495f0 100644
> >>> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h
> >>> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h
> >>> @@ -15,6 +15,7 @@ static const struct dpu_caps sc8280xp_dpu_caps = {
> >>>        .has_dim_layer = true,
> >>>        .has_idle_pc = true,
> >>>        .has_3d_merge = true,
> >>> +     .has_7xxx_intr = true,
> >>>        .max_linewidth = 5120,
> >>>        .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
> >>>    };
> >>> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h
> >>> index 86c2e68ebd2c..eb72411c16db 100644
> >>> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h
> >>> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h
> >>> @@ -14,6 +14,7 @@ static const struct dpu_caps sm8450_dpu_caps = {
> >>>        .has_src_split = true,
> >>>        .has_dim_layer = true,
> >>>        .has_idle_pc = true,
> >>> +     .has_7xxx_intr = true,
> >>>        .has_3d_merge = true,
> >>>        .max_linewidth = 5120,
> >>>        .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
> >>> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h
> >>> index 85dc34458b88..8209ca317bdc 100644
> >>> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h
> >>> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h
> >>> @@ -15,6 +15,7 @@ static const struct dpu_caps sm8550_dpu_caps = {
> >>>        .has_dim_layer = true,
> >>>        .has_idle_pc = true,
> >>>        .has_3d_merge = true,
> >>> +     .has_7xxx_intr = true,
> >>>        .max_linewidth = 5120,
> >>>        .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
> >>>    };
> >>> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
> >>> index 677048cc3b7d..72530ebb0ae6 100644
> >>> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
> >>> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
> >>> @@ -351,6 +351,7 @@ struct dpu_rotation_cfg {
> >>>     * @has_dim_layer      dim layer feature status
> >>>     * @has_idle_pc        indicate if idle power collapse feature is supported
> >>>     * @has_3d_merge       indicate if 3D merge is supported
> >>> + * @has_7xxx_intr      indicate that INTF/IRQs use addressing for DPU 7.0 and greater
> >>
> >> I see the requirement to distinguish feature support based on the DPU
> >> version in more than one series. Is it a good idea to bring in the DPU
> >> version info in chipset catalog? This will relieve us from maintaining
> >> such version flags for individual HW sub-blocks.
> >
> > This would not play well with the rest of the driver. The driver
> > usually does not compute features by DPU revision. Instead it lists
> > feature flags.
> >
>
> So I am increasingly seeing examples such as data_compress, widebus
> where it looks like version based enablement in the code will be just
> more efficient. For example.
>
> if (DPU_MAJOR_VER > xxx && DPU_MAJOR_VER < yyy)
>         enable data_compress;
>
> will be much easier to do than adding catalog entry for each chipset for
> these bit level details of registers especially when some of these
> cannot be considered as catalog features.

I'm fine with such approach for as long as it doesn't result in something like:
if (DPU_MAJOR_VER > xxx &&
   !(DPU_MAJOR_VER == yy && DPU_MINOR_VER == zz))

>
> Thats why I am wondering that, we dont need to add the revision based
> cfg picking anymore and rely on the compatible but in the dpu_mdss_cfg
> perhaps add a .core_rev.
>
> We will still stick to catalog based feature bits when its actually
> indeed a feature.
>
> Thoughts?
>
> >>
> >> Thanks and Regards,
> >> Jeykumar S.
> >>
> >>>     * @max_linewidth      max linewidth for sspp
> >>>     * @pixel_ram_size     size of latency hiding and de-tiling buffer in bytes
> >>>     * @max_hdeci_exp      max horizontal decimation supported (max is 2^value)
> >>> @@ -364,6 +365,7 @@ struct dpu_caps {
> >>>        bool has_dim_layer;
> >>>        bool has_idle_pc;
> >>>        bool has_3d_merge;
> >>> +     bool has_7xxx_intr;
> >>>        /* SSPP limits */
> >>>        u32 max_linewidth;
> >>>        u32 pixel_ram_size;
> >>> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c
> >>> index 0776b0f6df4f..a03d826bb9ad 100644
> >>> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c
> >>> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c
> >>> @@ -51,11 +51,9 @@ struct dpu_intr_reg {
> >>>    };
> >>>
> >>>    /*
> >>> - * struct dpu_intr_reg -  List of DPU interrupt registers
> >>> - *
> >>> - * When making changes be sure to sync with dpu_hw_intr_reg
> >>> + * dpu_intr_set_legacy -  List of DPU interrupt registers for DPU <= 6.x
> >>>     */
> >>> -static const struct dpu_intr_reg dpu_intr_set[] = {
> >>> +static const struct dpu_intr_reg dpu_intr_set_legacy[] = {
> >>>        [MDP_SSPP_TOP0_INTR] = {
> >>>                INTR_CLEAR,
> >>>                INTR_EN,
> >>> @@ -121,57 +119,78 @@ static const struct dpu_intr_reg dpu_intr_set[] = {
> >>>                MDP_AD4_INTR_EN_OFF(1),
> >>>                MDP_AD4_INTR_STATUS_OFF(1),
> >>>        },
> >>> -     [MDP_INTF0_7xxx_INTR] = {
> >>> +};
> >>> +
> >>> +/*
> >>> + * dpu_intr_set_7xxx -  List of DPU interrupt registers for DPU >= 7.0
> >>> + */
> >>> +static const struct dpu_intr_reg dpu_intr_set_7xxx[] = {
> >>> +     [MDP_SSPP_TOP0_INTR] = {
> >>> +             INTR_CLEAR,
> >>> +             INTR_EN,
> >>> +             INTR_STATUS
> >>> +     },
> >>> +     [MDP_SSPP_TOP0_INTR2] = {
> >>> +             INTR2_CLEAR,
> >>> +             INTR2_EN,
> >>> +             INTR2_STATUS
> >>> +     },
> >>> +     [MDP_SSPP_TOP0_HIST_INTR] = {
> >>> +             HIST_INTR_CLEAR,
> >>> +             HIST_INTR_EN,
> >>> +             HIST_INTR_STATUS
> >>> +     },
> >>> +     [MDP_INTF0_INTR] = {
> >>>                MDP_INTF_REV_7xxx_INTR_CLEAR(0),
> >>>                MDP_INTF_REV_7xxx_INTR_EN(0),
> >>>                MDP_INTF_REV_7xxx_INTR_STATUS(0)
> >>>        },
> >>> -     [MDP_INTF1_7xxx_INTR] = {
> >>> +     [MDP_INTF1_INTR] = {
> >>>                MDP_INTF_REV_7xxx_INTR_CLEAR(1),
> >>>                MDP_INTF_REV_7xxx_INTR_EN(1),
> >>>                MDP_INTF_REV_7xxx_INTR_STATUS(1)
> >>>        },
> >>> -     [MDP_INTF1_7xxx_TEAR_INTR] = {
> >>> +     [MDP_INTF1_TEAR_INTR] = {
> >>>                MDP_INTF_REV_7xxx_INTR_TEAR_CLEAR(1),
> >>>                MDP_INTF_REV_7xxx_INTR_TEAR_EN(1),
> >>>                MDP_INTF_REV_7xxx_INTR_TEAR_STATUS(1)
> >>>        },
> >>> -     [MDP_INTF2_7xxx_INTR] = {
> >>> +     [MDP_INTF2_INTR] = {
> >>>                MDP_INTF_REV_7xxx_INTR_CLEAR(2),
> >>>                MDP_INTF_REV_7xxx_INTR_EN(2),
> >>>                MDP_INTF_REV_7xxx_INTR_STATUS(2)
> >>>        },
> >>> -     [MDP_INTF2_7xxx_TEAR_INTR] = {
> >>> +     [MDP_INTF2_TEAR_INTR] = {
> >>>                MDP_INTF_REV_7xxx_INTR_TEAR_CLEAR(2),
> >>>                MDP_INTF_REV_7xxx_INTR_TEAR_EN(2),
> >>>                MDP_INTF_REV_7xxx_INTR_TEAR_STATUS(2)
> >>>        },
> >>> -     [MDP_INTF3_7xxx_INTR] = {
> >>> +     [MDP_INTF3_INTR] = {
> >>>                MDP_INTF_REV_7xxx_INTR_CLEAR(3),
> >>>                MDP_INTF_REV_7xxx_INTR_EN(3),
> >>>                MDP_INTF_REV_7xxx_INTR_STATUS(3)
> >>>        },
> >>> -     [MDP_INTF4_7xxx_INTR] = {
> >>> +     [MDP_INTF4_INTR] = {
> >>>                MDP_INTF_REV_7xxx_INTR_CLEAR(4),
> >>>                MDP_INTF_REV_7xxx_INTR_EN(4),
> >>>                MDP_INTF_REV_7xxx_INTR_STATUS(4)
> >>>        },
> >>> -     [MDP_INTF5_7xxx_INTR] = {
> >>> +     [MDP_INTF5_INTR] = {
> >>>                MDP_INTF_REV_7xxx_INTR_CLEAR(5),
> >>>                MDP_INTF_REV_7xxx_INTR_EN(5),
> >>>                MDP_INTF_REV_7xxx_INTR_STATUS(5)
> >>>        },
> >>> -     [MDP_INTF6_7xxx_INTR] = {
> >>> +     [MDP_INTF6_INTR] = {
> >>>                MDP_INTF_REV_7xxx_INTR_CLEAR(6),
> >>>                MDP_INTF_REV_7xxx_INTR_EN(6),
> >>>                MDP_INTF_REV_7xxx_INTR_STATUS(6)
> >>>        },
> >>> -     [MDP_INTF7_7xxx_INTR] = {
> >>> +     [MDP_INTF7_INTR] = {
> >>>                MDP_INTF_REV_7xxx_INTR_CLEAR(7),
> >>>                MDP_INTF_REV_7xxx_INTR_EN(7),
> >>>                MDP_INTF_REV_7xxx_INTR_STATUS(7)
> >>>        },
> >>> -     [MDP_INTF8_7xxx_INTR] = {
> >>> +     [MDP_INTF8_INTR] = {
> >>>                MDP_INTF_REV_7xxx_INTR_CLEAR(8),
> >>>                MDP_INTF_REV_7xxx_INTR_EN(8),
> >>>                MDP_INTF_REV_7xxx_INTR_STATUS(8)
> >>> @@ -216,19 +235,19 @@ irqreturn_t dpu_core_irq(struct msm_kms *kms)
> >>>                return IRQ_NONE;
> >>>
> >>>        spin_lock_irqsave(&intr->irq_lock, irq_flags);
> >>> -     for (reg_idx = 0; reg_idx < ARRAY_SIZE(dpu_intr_set); reg_idx++) {
> >>> +     for (reg_idx = 0; reg_idx < MDP_INTR_MAX; reg_idx++) {
> >>>                if (!test_bit(reg_idx, &intr->irq_mask))
> >>>                        continue;
> >>>
> >>>                /* Read interrupt status */
> >>> -             irq_status = DPU_REG_READ(&intr->hw, dpu_intr_set[reg_idx].status_off);
> >>> +             irq_status = DPU_REG_READ(&intr->hw, intr->intr_set[reg_idx].status_off);
> >>>
> >>>                /* Read enable mask */
> >>> -             enable_mask = DPU_REG_READ(&intr->hw, dpu_intr_set[reg_idx].en_off);
> >>> +             enable_mask = DPU_REG_READ(&intr->hw, intr->intr_set[reg_idx].en_off);
> >>>
> >>>                /* and clear the interrupt */
> >>>                if (irq_status)
> >>> -                     DPU_REG_WRITE(&intr->hw, dpu_intr_set[reg_idx].clr_off,
> >>> +                     DPU_REG_WRITE(&intr->hw, intr->intr_set[reg_idx].clr_off,
> >>>                                     irq_status);
> >>>
> >>>                /* Finally update IRQ status based on enable mask */
> >>> @@ -285,7 +304,11 @@ static int dpu_hw_intr_enable_irq_locked(struct dpu_hw_intr *intr, int irq_idx)
> >>>        assert_spin_locked(&intr->irq_lock);
> >>>
> >>>        reg_idx = DPU_IRQ_REG(irq_idx);
> >>> -     reg = &dpu_intr_set[reg_idx];
> >>> +     reg = &intr->intr_set[reg_idx];
> >>> +
> >>> +     /* Is this interrupt register supported on the platform */
> >>> +     if (WARN_ON(!reg->en_off))
> >>> +             return -EINVAL;
> >>>
> >>>        cache_irq_mask = intr->cache_irq_mask[reg_idx];
> >>>        if (cache_irq_mask & DPU_IRQ_MASK(irq_idx)) {
> >>> @@ -334,7 +357,7 @@ static int dpu_hw_intr_disable_irq_locked(struct dpu_hw_intr *intr, int irq_idx)
> >>>        assert_spin_locked(&intr->irq_lock);
> >>>
> >>>        reg_idx = DPU_IRQ_REG(irq_idx);
> >>> -     reg = &dpu_intr_set[reg_idx];
> >>> +     reg = &intr->intr_set[reg_idx];
> >>>
> >>>        cache_irq_mask = intr->cache_irq_mask[reg_idx];
> >>>        if ((cache_irq_mask & DPU_IRQ_MASK(irq_idx)) == 0) {
> >>> @@ -368,10 +391,10 @@ static void dpu_clear_irqs(struct dpu_kms *dpu_kms)
> >>>        if (!intr)
> >>>                return;
> >>>
> >>> -     for (i = 0; i < ARRAY_SIZE(dpu_intr_set); i++) {
> >>> +     for (i = 0; i < MDP_INTR_MAX; i++) {
> >>>                if (test_bit(i, &intr->irq_mask))
> >>>                        DPU_REG_WRITE(&intr->hw,
> >>> -                                     dpu_intr_set[i].clr_off, 0xffffffff);
> >>> +                                     intr->intr_set[i].clr_off, 0xffffffff);
> >>>        }
> >>>
> >>>        /* ensure register writes go through */
> >>> @@ -386,10 +409,10 @@ static void dpu_disable_all_irqs(struct dpu_kms *dpu_kms)
> >>>        if (!intr)
> >>>                return;
> >>>
> >>> -     for (i = 0; i < ARRAY_SIZE(dpu_intr_set); i++) {
> >>> +     for (i = 0; i < MDP_INTR_MAX; i++) {
> >>>                if (test_bit(i, &intr->irq_mask))
> >>>                        DPU_REG_WRITE(&intr->hw,
> >>> -                                     dpu_intr_set[i].en_off, 0x00000000);
> >>> +                                     intr->intr_set[i].en_off, 0x00000000);
> >>>        }
> >>>
> >>>        /* ensure register writes go through */
> >>> @@ -421,10 +444,10 @@ u32 dpu_core_irq_read(struct dpu_kms *dpu_kms, int irq_idx)
> >>>
> >>>        reg_idx = DPU_IRQ_REG(irq_idx);
> >>>        intr_status = DPU_REG_READ(&intr->hw,
> >>> -                     dpu_intr_set[reg_idx].status_off) &
> >>> +                     intr->intr_set[reg_idx].status_off) &
> >>>                DPU_IRQ_MASK(irq_idx);
> >>>        if (intr_status)
> >>> -             DPU_REG_WRITE(&intr->hw, dpu_intr_set[reg_idx].clr_off,
> >>> +             DPU_REG_WRITE(&intr->hw, intr->intr_set[reg_idx].clr_off,
> >>>                                intr_status);
> >>>
> >>>        /* ensure register writes go through */
> >>> @@ -448,6 +471,11 @@ struct dpu_hw_intr *dpu_hw_intr_init(void __iomem *addr,
> >>>        if (!intr)
> >>>                return ERR_PTR(-ENOMEM);
> >>>
> >>> +     if (m->caps->has_7xxx_intr)
> >>> +             intr->intr_set = dpu_intr_set_7xxx;
> >>> +     else
> >>> +             intr->intr_set = dpu_intr_set_legacy;
> >>> +
> >>>        intr->hw.blk_addr = addr + m->mdp[0].base;
> >>>
> >>>        intr->total_irqs = nirq;
> >>> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h
> >>> index 1f2dabc54c22..f329d6d7f646 100644
> >>> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h
> >>> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h
> >>> @@ -23,24 +23,29 @@ enum dpu_hw_intr_reg {
> >>>        MDP_INTF3_INTR,
> >>>        MDP_INTF4_INTR,
> >>>        MDP_INTF5_INTR,
> >>> +     MDP_INTF6_INTR,
> >>> +     MDP_INTF7_INTR,
> >>> +     MDP_INTF8_INTR,
> >>>        MDP_INTF1_TEAR_INTR,
> >>>        MDP_INTF2_TEAR_INTR,
> >>>        MDP_AD4_0_INTR,
> >>>        MDP_AD4_1_INTR,
> >>> -     MDP_INTF0_7xxx_INTR,
> >>> -     MDP_INTF1_7xxx_INTR,
> >>> -     MDP_INTF1_7xxx_TEAR_INTR,
> >>> -     MDP_INTF2_7xxx_INTR,
> >>> -     MDP_INTF2_7xxx_TEAR_INTR,
> >>> -     MDP_INTF3_7xxx_INTR,
> >>> -     MDP_INTF4_7xxx_INTR,
> >>> -     MDP_INTF5_7xxx_INTR,
> >>> -     MDP_INTF6_7xxx_INTR,
> >>> -     MDP_INTF7_7xxx_INTR,
> >>> -     MDP_INTF8_7xxx_INTR,
> >>>        MDP_INTR_MAX,
> >>>    };
> >>>
> >>> +/* compatibility */
> >>> +#define MDP_INTF0_7xxx_INTR MDP_INTF0_INTR
> >>> +#define MDP_INTF1_7xxx_INTR MDP_INTF1_INTR
> >>> +#define MDP_INTF2_7xxx_INTR MDP_INTF2_INTR
> >>> +#define MDP_INTF3_7xxx_INTR MDP_INTF3_INTR
> >>> +#define MDP_INTF4_7xxx_INTR MDP_INTF4_INTR
> >>> +#define MDP_INTF5_7xxx_INTR MDP_INTF5_INTR
> >>> +#define MDP_INTF6_7xxx_INTR MDP_INTF6_INTR
> >>> +#define MDP_INTF7_7xxx_INTR MDP_INTF7_INTR
> >>> +#define MDP_INTF8_7xxx_INTR MDP_INTF8_INTR
> >>> +#define MDP_INTF1_7xxx_TEAR_INTR MDP_INTF1_TEAR_INTR
> >>> +#define MDP_INTF2_7xxx_TEAR_INTR MDP_INTF2_TEAR_INTR
> >>> +
> >>>    #define DPU_IRQ_IDX(reg_idx, offset)        (reg_idx * 32 + offset)
> >>>
> >>>    /**
> >>> @@ -60,6 +65,7 @@ struct dpu_hw_intr {
> >>>        u32 total_irqs;
> >>>        spinlock_t irq_lock;
> >>>        unsigned long irq_mask;
> >>> +     const struct dpu_intr_reg *intr_set;
> >>>
> >>>        struct {
> >>>                void (*cb)(void *arg, int irq_idx);



-- 
With best wishes
Dmitry

Re: [Freedreno] [PATCH v2 3/6] drm/msm/dpu: split interrupt address arrays

[Abhinav Kumar]

On 5/26/2023 1:43 AM, Dmitry Baryshkov wrote:
> On Fri, 26 May 2023 at 01:42, Abhinav Kumar <quic_abhinavk@quicinc.com> wrote:
>> On 5/25/2023 3:30 PM, Dmitry Baryshkov wrote:
>>> On Fri, 26 May 2023 at 00:40, Jeykumar Sankaran
>>> <quic_jeykumar@quicinc.com> wrote:
>>>> On 5/22/2023 2:45 PM, Dmitry Baryshkov wrote:
>>>>> There is no point in having a single enum (and a single array) for both
>>>>> DPU < 7.0 and DPU >= 7.0 interrupt registers. Instead define a single
>>>>> enum and two IRQ address arrays.
>>>>>
>>>>> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
>>>>> ---
>>>>>     .../msm/disp/dpu1/catalog/dpu_7_0_sm8350.h    |  1 +
>>>>>     .../msm/disp/dpu1/catalog/dpu_7_2_sc7280.h    |  1 +
>>>>>     .../msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h  |  1 +
>>>>>     .../msm/disp/dpu1/catalog/dpu_8_1_sm8450.h    |  1 +
>>>>>     .../msm/disp/dpu1/catalog/dpu_9_0_sm8550.h    |  1 +
>>>>>     .../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h    |  2 +
>>>>>     .../gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c | 82 +++++++++++++------
>>>>>     .../gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h | 28 ++++---
>>>>>     8 files changed, 79 insertions(+), 38 deletions(-)
>>>>>
>>>>> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h
>>>>> index 3c1b2c13398d..320cfa4be633 100644
>>>>> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h
>>>>> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h
>>>>> @@ -15,6 +15,7 @@ static const struct dpu_caps sm8350_dpu_caps = {
>>>>>         .has_dim_layer = true,
>>>>>         .has_idle_pc = true,
>>>>>         .has_3d_merge = true,
>>>>> +     .has_7xxx_intr = true,
>>>>>         .max_linewidth = 4096,
>>>>>         .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
>>>>>     };
>>>>> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h
>>>>> index 5d894cbb0a62..9306c7a115e9 100644
>>>>> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h
>>>>> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h
>>>>> @@ -13,6 +13,7 @@ static const struct dpu_caps sc7280_dpu_caps = {
>>>>>         .qseed_type = DPU_SSPP_SCALER_QSEED4,
>>>>>         .has_dim_layer = true,
>>>>>         .has_idle_pc = true,
>>>>> +     .has_7xxx_intr = true,
>>>>>         .max_linewidth = 2400,
>>>>>         .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
>>>>>     };
>>>>> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h
>>>>> index c3f1ae000a21..fc1e17c495f0 100644
>>>>> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h
>>>>> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h
>>>>> @@ -15,6 +15,7 @@ static const struct dpu_caps sc8280xp_dpu_caps = {
>>>>>         .has_dim_layer = true,
>>>>>         .has_idle_pc = true,
>>>>>         .has_3d_merge = true,
>>>>> +     .has_7xxx_intr = true,
>>>>>         .max_linewidth = 5120,
>>>>>         .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
>>>>>     };
>>>>> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h
>>>>> index 86c2e68ebd2c..eb72411c16db 100644
>>>>> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h
>>>>> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h
>>>>> @@ -14,6 +14,7 @@ static const struct dpu_caps sm8450_dpu_caps = {
>>>>>         .has_src_split = true,
>>>>>         .has_dim_layer = true,
>>>>>         .has_idle_pc = true,
>>>>> +     .has_7xxx_intr = true,
>>>>>         .has_3d_merge = true,
>>>>>         .max_linewidth = 5120,
>>>>>         .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
>>>>> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h
>>>>> index 85dc34458b88..8209ca317bdc 100644
>>>>> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h
>>>>> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h
>>>>> @@ -15,6 +15,7 @@ static const struct dpu_caps sm8550_dpu_caps = {
>>>>>         .has_dim_layer = true,
>>>>>         .has_idle_pc = true,
>>>>>         .has_3d_merge = true,
>>>>> +     .has_7xxx_intr = true,
>>>>>         .max_linewidth = 5120,
>>>>>         .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
>>>>>     };
>>>>> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
>>>>> index 677048cc3b7d..72530ebb0ae6 100644
>>>>> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
>>>>> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
>>>>> @@ -351,6 +351,7 @@ struct dpu_rotation_cfg {
>>>>>      * @has_dim_layer      dim layer feature status
>>>>>      * @has_idle_pc        indicate if idle power collapse feature is supported
>>>>>      * @has_3d_merge       indicate if 3D merge is supported
>>>>> + * @has_7xxx_intr      indicate that INTF/IRQs use addressing for DPU 7.0 and greater
>>>>
>>>> I see the requirement to distinguish feature support based on the DPU
>>>> version in more than one series. Is it a good idea to bring in the DPU
>>>> version info in chipset catalog? This will relieve us from maintaining
>>>> such version flags for individual HW sub-blocks.
>>>
>>> This would not play well with the rest of the driver. The driver
>>> usually does not compute features by DPU revision. Instead it lists
>>> feature flags.
>>>
>>
>> So I am increasingly seeing examples such as data_compress, widebus
>> where it looks like version based enablement in the code will be just
>> more efficient. For example.
>>
>> if (DPU_MAJOR_VER > xxx && DPU_MAJOR_VER < yyy)
>>          enable data_compress;
>>
>> will be much easier to do than adding catalog entry for each chipset for
>> these bit level details of registers especially when some of these
>> cannot be considered as catalog features.
> 
> I'm fine with such approach for as long as it doesn't result in something like:
> if (DPU_MAJOR_VER > xxx &&
>     !(DPU_MAJOR_VER == yy && DPU_MINOR_VER == zz))
> 

Agreed, if it gets too messy for any of the conditions, we will fallback 
to catalog approach for those. Thats why I would say this is a good 
hybrid approach.

I can push a change to add the core_rev to the mdss_cfg.

>>
>> Thats why I am wondering that, we dont need to add the revision based
>> cfg picking anymore and rely on the compatible but in the dpu_mdss_cfg
>> perhaps add a .core_rev.
>>
>> We will still stick to catalog based feature bits when its actually
>> indeed a feature.
>>
>> Thoughts?
>>
>>>>
>>>> Thanks and Regards,
>>>> Jeykumar S.
>>>>
>>>>>      * @max_linewidth      max linewidth for sspp
>>>>>      * @pixel_ram_size     size of latency hiding and de-tiling buffer in bytes
>>>>>      * @max_hdeci_exp      max horizontal decimation supported (max is 2^value)
>>>>> @@ -364,6 +365,7 @@ struct dpu_caps {
>>>>>         bool has_dim_layer;
>>>>>         bool has_idle_pc;
>>>>>         bool has_3d_merge;
>>>>> +     bool has_7xxx_intr;
>>>>>         /* SSPP limits */
>>>>>         u32 max_linewidth;
>>>>>         u32 pixel_ram_size;
>>>>> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c
>>>>> index 0776b0f6df4f..a03d826bb9ad 100644
>>>>> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c
>>>>> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c
>>>>> @@ -51,11 +51,9 @@ struct dpu_intr_reg {
>>>>>     };
>>>>>
>>>>>     /*
>>>>> - * struct dpu_intr_reg -  List of DPU interrupt registers
>>>>> - *
>>>>> - * When making changes be sure to sync with dpu_hw_intr_reg
>>>>> + * dpu_intr_set_legacy -  List of DPU interrupt registers for DPU <= 6.x
>>>>>      */
>>>>> -static const struct dpu_intr_reg dpu_intr_set[] = {
>>>>> +static const struct dpu_intr_reg dpu_intr_set_legacy[] = {
>>>>>         [MDP_SSPP_TOP0_INTR] = {
>>>>>                 INTR_CLEAR,
>>>>>                 INTR_EN,
>>>>> @@ -121,57 +119,78 @@ static const struct dpu_intr_reg dpu_intr_set[] = {
>>>>>                 MDP_AD4_INTR_EN_OFF(1),
>>>>>                 MDP_AD4_INTR_STATUS_OFF(1),
>>>>>         },
>>>>> -     [MDP_INTF0_7xxx_INTR] = {
>>>>> +};
>>>>> +
>>>>> +/*
>>>>> + * dpu_intr_set_7xxx -  List of DPU interrupt registers for DPU >= 7.0
>>>>> + */
>>>>> +static const struct dpu_intr_reg dpu_intr_set_7xxx[] = {
>>>>> +     [MDP_SSPP_TOP0_INTR] = {
>>>>> +             INTR_CLEAR,
>>>>> +             INTR_EN,
>>>>> +             INTR_STATUS
>>>>> +     },
>>>>> +     [MDP_SSPP_TOP0_INTR2] = {
>>>>> +             INTR2_CLEAR,
>>>>> +             INTR2_EN,
>>>>> +             INTR2_STATUS
>>>>> +     },
>>>>> +     [MDP_SSPP_TOP0_HIST_INTR] = {
>>>>> +             HIST_INTR_CLEAR,
>>>>> +             HIST_INTR_EN,
>>>>> +             HIST_INTR_STATUS
>>>>> +     },
>>>>> +     [MDP_INTF0_INTR] = {
>>>>>                 MDP_INTF_REV_7xxx_INTR_CLEAR(0),
>>>>>                 MDP_INTF_REV_7xxx_INTR_EN(0),
>>>>>                 MDP_INTF_REV_7xxx_INTR_STATUS(0)
>>>>>         },
>>>>> -     [MDP_INTF1_7xxx_INTR] = {
>>>>> +     [MDP_INTF1_INTR] = {
>>>>>                 MDP_INTF_REV_7xxx_INTR_CLEAR(1),
>>>>>                 MDP_INTF_REV_7xxx_INTR_EN(1),
>>>>>                 MDP_INTF_REV_7xxx_INTR_STATUS(1)
>>>>>         },
>>>>> -     [MDP_INTF1_7xxx_TEAR_INTR] = {
>>>>> +     [MDP_INTF1_TEAR_INTR] = {
>>>>>                 MDP_INTF_REV_7xxx_INTR_TEAR_CLEAR(1),
>>>>>                 MDP_INTF_REV_7xxx_INTR_TEAR_EN(1),
>>>>>                 MDP_INTF_REV_7xxx_INTR_TEAR_STATUS(1)
>>>>>         },
>>>>> -     [MDP_INTF2_7xxx_INTR] = {
>>>>> +     [MDP_INTF2_INTR] = {
>>>>>                 MDP_INTF_REV_7xxx_INTR_CLEAR(2),
>>>>>                 MDP_INTF_REV_7xxx_INTR_EN(2),
>>>>>                 MDP_INTF_REV_7xxx_INTR_STATUS(2)
>>>>>         },
>>>>> -     [MDP_INTF2_7xxx_TEAR_INTR] = {
>>>>> +     [MDP_INTF2_TEAR_INTR] = {
>>>>>                 MDP_INTF_REV_7xxx_INTR_TEAR_CLEAR(2),
>>>>>                 MDP_INTF_REV_7xxx_INTR_TEAR_EN(2),
>>>>>                 MDP_INTF_REV_7xxx_INTR_TEAR_STATUS(2)
>>>>>         },
>>>>> -     [MDP_INTF3_7xxx_INTR] = {
>>>>> +     [MDP_INTF3_INTR] = {
>>>>>                 MDP_INTF_REV_7xxx_INTR_CLEAR(3),
>>>>>                 MDP_INTF_REV_7xxx_INTR_EN(3),
>>>>>                 MDP_INTF_REV_7xxx_INTR_STATUS(3)
>>>>>         },
>>>>> -     [MDP_INTF4_7xxx_INTR] = {
>>>>> +     [MDP_INTF4_INTR] = {
>>>>>                 MDP_INTF_REV_7xxx_INTR_CLEAR(4),
>>>>>                 MDP_INTF_REV_7xxx_INTR_EN(4),
>>>>>                 MDP_INTF_REV_7xxx_INTR_STATUS(4)
>>>>>         },
>>>>> -     [MDP_INTF5_7xxx_INTR] = {
>>>>> +     [MDP_INTF5_INTR] = {
>>>>>                 MDP_INTF_REV_7xxx_INTR_CLEAR(5),
>>>>>                 MDP_INTF_REV_7xxx_INTR_EN(5),
>>>>>                 MDP_INTF_REV_7xxx_INTR_STATUS(5)
>>>>>         },
>>>>> -     [MDP_INTF6_7xxx_INTR] = {
>>>>> +     [MDP_INTF6_INTR] = {
>>>>>                 MDP_INTF_REV_7xxx_INTR_CLEAR(6),
>>>>>                 MDP_INTF_REV_7xxx_INTR_EN(6),
>>>>>                 MDP_INTF_REV_7xxx_INTR_STATUS(6)
>>>>>         },
>>>>> -     [MDP_INTF7_7xxx_INTR] = {
>>>>> +     [MDP_INTF7_INTR] = {
>>>>>                 MDP_INTF_REV_7xxx_INTR_CLEAR(7),
>>>>>                 MDP_INTF_REV_7xxx_INTR_EN(7),
>>>>>                 MDP_INTF_REV_7xxx_INTR_STATUS(7)
>>>>>         },
>>>>> -     [MDP_INTF8_7xxx_INTR] = {
>>>>> +     [MDP_INTF8_INTR] = {
>>>>>                 MDP_INTF_REV_7xxx_INTR_CLEAR(8),
>>>>>                 MDP_INTF_REV_7xxx_INTR_EN(8),
>>>>>                 MDP_INTF_REV_7xxx_INTR_STATUS(8)
>>>>> @@ -216,19 +235,19 @@ irqreturn_t dpu_core_irq(struct msm_kms *kms)
>>>>>                 return IRQ_NONE;
>>>>>
>>>>>         spin_lock_irqsave(&intr->irq_lock, irq_flags);
>>>>> -     for (reg_idx = 0; reg_idx < ARRAY_SIZE(dpu_intr_set); reg_idx++) {
>>>>> +     for (reg_idx = 0; reg_idx < MDP_INTR_MAX; reg_idx++) {
>>>>>                 if (!test_bit(reg_idx, &intr->irq_mask))
>>>>>                         continue;
>>>>>
>>>>>                 /* Read interrupt status */
>>>>> -             irq_status = DPU_REG_READ(&intr->hw, dpu_intr_set[reg_idx].status_off);
>>>>> +             irq_status = DPU_REG_READ(&intr->hw, intr->intr_set[reg_idx].status_off);
>>>>>
>>>>>                 /* Read enable mask */
>>>>> -             enable_mask = DPU_REG_READ(&intr->hw, dpu_intr_set[reg_idx].en_off);
>>>>> +             enable_mask = DPU_REG_READ(&intr->hw, intr->intr_set[reg_idx].en_off);
>>>>>
>>>>>                 /* and clear the interrupt */
>>>>>                 if (irq_status)
>>>>> -                     DPU_REG_WRITE(&intr->hw, dpu_intr_set[reg_idx].clr_off,
>>>>> +                     DPU_REG_WRITE(&intr->hw, intr->intr_set[reg_idx].clr_off,
>>>>>                                      irq_status);
>>>>>
>>>>>                 /* Finally update IRQ status based on enable mask */
>>>>> @@ -285,7 +304,11 @@ static int dpu_hw_intr_enable_irq_locked(struct dpu_hw_intr *intr, int irq_idx)
>>>>>         assert_spin_locked(&intr->irq_lock);
>>>>>
>>>>>         reg_idx = DPU_IRQ_REG(irq_idx);
>>>>> -     reg = &dpu_intr_set[reg_idx];
>>>>> +     reg = &intr->intr_set[reg_idx];
>>>>> +
>>>>> +     /* Is this interrupt register supported on the platform */
>>>>> +     if (WARN_ON(!reg->en_off))
>>>>> +             return -EINVAL;
>>>>>
>>>>>         cache_irq_mask = intr->cache_irq_mask[reg_idx];
>>>>>         if (cache_irq_mask & DPU_IRQ_MASK(irq_idx)) {
>>>>> @@ -334,7 +357,7 @@ static int dpu_hw_intr_disable_irq_locked(struct dpu_hw_intr *intr, int irq_idx)
>>>>>         assert_spin_locked(&intr->irq_lock);
>>>>>
>>>>>         reg_idx = DPU_IRQ_REG(irq_idx);
>>>>> -     reg = &dpu_intr_set[reg_idx];
>>>>> +     reg = &intr->intr_set[reg_idx];
>>>>>
>>>>>         cache_irq_mask = intr->cache_irq_mask[reg_idx];
>>>>>         if ((cache_irq_mask & DPU_IRQ_MASK(irq_idx)) == 0) {
>>>>> @@ -368,10 +391,10 @@ static void dpu_clear_irqs(struct dpu_kms *dpu_kms)
>>>>>         if (!intr)
>>>>>                 return;
>>>>>
>>>>> -     for (i = 0; i < ARRAY_SIZE(dpu_intr_set); i++) {
>>>>> +     for (i = 0; i < MDP_INTR_MAX; i++) {
>>>>>                 if (test_bit(i, &intr->irq_mask))
>>>>>                         DPU_REG_WRITE(&intr->hw,
>>>>> -                                     dpu_intr_set[i].clr_off, 0xffffffff);
>>>>> +                                     intr->intr_set[i].clr_off, 0xffffffff);
>>>>>         }
>>>>>
>>>>>         /* ensure register writes go through */
>>>>> @@ -386,10 +409,10 @@ static void dpu_disable_all_irqs(struct dpu_kms *dpu_kms)
>>>>>         if (!intr)
>>>>>                 return;
>>>>>
>>>>> -     for (i = 0; i < ARRAY_SIZE(dpu_intr_set); i++) {
>>>>> +     for (i = 0; i < MDP_INTR_MAX; i++) {
>>>>>                 if (test_bit(i, &intr->irq_mask))
>>>>>                         DPU_REG_WRITE(&intr->hw,
>>>>> -                                     dpu_intr_set[i].en_off, 0x00000000);
>>>>> +                                     intr->intr_set[i].en_off, 0x00000000);
>>>>>         }
>>>>>
>>>>>         /* ensure register writes go through */
>>>>> @@ -421,10 +444,10 @@ u32 dpu_core_irq_read(struct dpu_kms *dpu_kms, int irq_idx)
>>>>>
>>>>>         reg_idx = DPU_IRQ_REG(irq_idx);
>>>>>         intr_status = DPU_REG_READ(&intr->hw,
>>>>> -                     dpu_intr_set[reg_idx].status_off) &
>>>>> +                     intr->intr_set[reg_idx].status_off) &
>>>>>                 DPU_IRQ_MASK(irq_idx);
>>>>>         if (intr_status)
>>>>> -             DPU_REG_WRITE(&intr->hw, dpu_intr_set[reg_idx].clr_off,
>>>>> +             DPU_REG_WRITE(&intr->hw, intr->intr_set[reg_idx].clr_off,
>>>>>                                 intr_status);
>>>>>
>>>>>         /* ensure register writes go through */
>>>>> @@ -448,6 +471,11 @@ struct dpu_hw_intr *dpu_hw_intr_init(void __iomem *addr,
>>>>>         if (!intr)
>>>>>                 return ERR_PTR(-ENOMEM);
>>>>>
>>>>> +     if (m->caps->has_7xxx_intr)
>>>>> +             intr->intr_set = dpu_intr_set_7xxx;
>>>>> +     else
>>>>> +             intr->intr_set = dpu_intr_set_legacy;
>>>>> +
>>>>>         intr->hw.blk_addr = addr + m->mdp[0].base;
>>>>>
>>>>>         intr->total_irqs = nirq;
>>>>> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h
>>>>> index 1f2dabc54c22..f329d6d7f646 100644
>>>>> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h
>>>>> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h
>>>>> @@ -23,24 +23,29 @@ enum dpu_hw_intr_reg {
>>>>>         MDP_INTF3_INTR,
>>>>>         MDP_INTF4_INTR,
>>>>>         MDP_INTF5_INTR,
>>>>> +     MDP_INTF6_INTR,
>>>>> +     MDP_INTF7_INTR,
>>>>> +     MDP_INTF8_INTR,
>>>>>         MDP_INTF1_TEAR_INTR,
>>>>>         MDP_INTF2_TEAR_INTR,
>>>>>         MDP_AD4_0_INTR,
>>>>>         MDP_AD4_1_INTR,
>>>>> -     MDP_INTF0_7xxx_INTR,
>>>>> -     MDP_INTF1_7xxx_INTR,
>>>>> -     MDP_INTF1_7xxx_TEAR_INTR,
>>>>> -     MDP_INTF2_7xxx_INTR,
>>>>> -     MDP_INTF2_7xxx_TEAR_INTR,
>>>>> -     MDP_INTF3_7xxx_INTR,
>>>>> -     MDP_INTF4_7xxx_INTR,
>>>>> -     MDP_INTF5_7xxx_INTR,
>>>>> -     MDP_INTF6_7xxx_INTR,
>>>>> -     MDP_INTF7_7xxx_INTR,
>>>>> -     MDP_INTF8_7xxx_INTR,
>>>>>         MDP_INTR_MAX,
>>>>>     };
>>>>>
>>>>> +/* compatibility */
>>>>> +#define MDP_INTF0_7xxx_INTR MDP_INTF0_INTR
>>>>> +#define MDP_INTF1_7xxx_INTR MDP_INTF1_INTR
>>>>> +#define MDP_INTF2_7xxx_INTR MDP_INTF2_INTR
>>>>> +#define MDP_INTF3_7xxx_INTR MDP_INTF3_INTR
>>>>> +#define MDP_INTF4_7xxx_INTR MDP_INTF4_INTR
>>>>> +#define MDP_INTF5_7xxx_INTR MDP_INTF5_INTR
>>>>> +#define MDP_INTF6_7xxx_INTR MDP_INTF6_INTR
>>>>> +#define MDP_INTF7_7xxx_INTR MDP_INTF7_INTR
>>>>> +#define MDP_INTF8_7xxx_INTR MDP_INTF8_INTR
>>>>> +#define MDP_INTF1_7xxx_TEAR_INTR MDP_INTF1_TEAR_INTR
>>>>> +#define MDP_INTF2_7xxx_TEAR_INTR MDP_INTF2_TEAR_INTR
>>>>> +
>>>>>     #define DPU_IRQ_IDX(reg_idx, offset)        (reg_idx * 32 + offset)
>>>>>
>>>>>     /**
>>>>> @@ -60,6 +65,7 @@ struct dpu_hw_intr {
>>>>>         u32 total_irqs;
>>>>>         spinlock_t irq_lock;
>>>>>         unsigned long irq_mask;
>>>>> +     const struct dpu_intr_reg *intr_set;
>>>>>
>>>>>         struct {
>>>>>                 void (*cb)(void *arg, int irq_idx);
> 
> 
> 

Re: [PATCH v2 3/6] drm/msm/dpu: split interrupt address arrays

[Neil Armstrong]

On 22/05/2023 23:45, Dmitry Baryshkov wrote:
> There is no point in having a single enum (and a single array) for both
> DPU < 7.0 and DPU >= 7.0 interrupt registers. Instead define a single
> enum and two IRQ address arrays.
> 
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> ---
>   .../msm/disp/dpu1/catalog/dpu_7_0_sm8350.h    |  1 +
>   .../msm/disp/dpu1/catalog/dpu_7_2_sc7280.h    |  1 +
>   .../msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h  |  1 +
>   .../msm/disp/dpu1/catalog/dpu_8_1_sm8450.h    |  1 +
>   .../msm/disp/dpu1/catalog/dpu_9_0_sm8550.h    |  1 +
>   .../gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h    |  2 +
>   .../gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c | 82 +++++++++++++------
>   .../gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h | 28 ++++---
>   8 files changed, 79 insertions(+), 38 deletions(-)
> 
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h
> index 3c1b2c13398d..320cfa4be633 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h
> @@ -15,6 +15,7 @@ static const struct dpu_caps sm8350_dpu_caps = {
>   	.has_dim_layer = true,
>   	.has_idle_pc = true,
>   	.has_3d_merge = true,
> +	.has_7xxx_intr = true,
>   	.max_linewidth = 4096,
>   	.pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
>   };
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h
> index 5d894cbb0a62..9306c7a115e9 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h
> @@ -13,6 +13,7 @@ static const struct dpu_caps sc7280_dpu_caps = {
>   	.qseed_type = DPU_SSPP_SCALER_QSEED4,
>   	.has_dim_layer = true,
>   	.has_idle_pc = true,
> +	.has_7xxx_intr = true,
>   	.max_linewidth = 2400,
>   	.pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
>   };
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h
> index c3f1ae000a21..fc1e17c495f0 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h
> @@ -15,6 +15,7 @@ static const struct dpu_caps sc8280xp_dpu_caps = {
>   	.has_dim_layer = true,
>   	.has_idle_pc = true,
>   	.has_3d_merge = true,
> +	.has_7xxx_intr = true,
>   	.max_linewidth = 5120,
>   	.pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
>   };
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h
> index 86c2e68ebd2c..eb72411c16db 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h
> @@ -14,6 +14,7 @@ static const struct dpu_caps sm8450_dpu_caps = {
>   	.has_src_split = true,
>   	.has_dim_layer = true,
>   	.has_idle_pc = true,
> +	.has_7xxx_intr = true,
>   	.has_3d_merge = true,
>   	.max_linewidth = 5120,
>   	.pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h
> index 85dc34458b88..8209ca317bdc 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h
> @@ -15,6 +15,7 @@ static const struct dpu_caps sm8550_dpu_caps = {
>   	.has_dim_layer = true,
>   	.has_idle_pc = true,
>   	.has_3d_merge = true,
> +	.has_7xxx_intr = true,
>   	.max_linewidth = 5120,
>   	.pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE,
>   };
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
> index 677048cc3b7d..72530ebb0ae6 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
> @@ -351,6 +351,7 @@ struct dpu_rotation_cfg {
>    * @has_dim_layer      dim layer feature status
>    * @has_idle_pc        indicate if idle power collapse feature is supported
>    * @has_3d_merge       indicate if 3D merge is supported
> + * @has_7xxx_intr      indicate that INTF/IRQs use addressing for DPU 7.0 and greater
>    * @max_linewidth      max linewidth for sspp
>    * @pixel_ram_size     size of latency hiding and de-tiling buffer in bytes
>    * @max_hdeci_exp      max horizontal decimation supported (max is 2^value)
> @@ -364,6 +365,7 @@ struct dpu_caps {
>   	bool has_dim_layer;
>   	bool has_idle_pc;
>   	bool has_3d_merge;
> +	bool has_7xxx_intr;
>   	/* SSPP limits */
>   	u32 max_linewidth;
>   	u32 pixel_ram_size;
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c
> index 0776b0f6df4f..a03d826bb9ad 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c
> @@ -51,11 +51,9 @@ struct dpu_intr_reg {
>   };
>   
>   /*
> - * struct dpu_intr_reg -  List of DPU interrupt registers
> - *
> - * When making changes be sure to sync with dpu_hw_intr_reg
> + * dpu_intr_set_legacy -  List of DPU interrupt registers for DPU <= 6.x
>    */
> -static const struct dpu_intr_reg dpu_intr_set[] = {
> +static const struct dpu_intr_reg dpu_intr_set_legacy[] = {
>   	[MDP_SSPP_TOP0_INTR] = {
>   		INTR_CLEAR,
>   		INTR_EN,
> @@ -121,57 +119,78 @@ static const struct dpu_intr_reg dpu_intr_set[] = {
>   		MDP_AD4_INTR_EN_OFF(1),
>   		MDP_AD4_INTR_STATUS_OFF(1),
>   	},
> -	[MDP_INTF0_7xxx_INTR] = {
> +};
> +
> +/*
> + * dpu_intr_set_7xxx -  List of DPU interrupt registers for DPU >= 7.0
> + */
> +static const struct dpu_intr_reg dpu_intr_set_7xxx[] = {
> +	[MDP_SSPP_TOP0_INTR] = {
> +		INTR_CLEAR,
> +		INTR_EN,
> +		INTR_STATUS
> +	},
> +	[MDP_SSPP_TOP0_INTR2] = {
> +		INTR2_CLEAR,
> +		INTR2_EN,
> +		INTR2_STATUS
> +	},
> +	[MDP_SSPP_TOP0_HIST_INTR] = {
> +		HIST_INTR_CLEAR,
> +		HIST_INTR_EN,
> +		HIST_INTR_STATUS
> +	},
> +	[MDP_INTF0_INTR] = {
>   		MDP_INTF_REV_7xxx_INTR_CLEAR(0),
>   		MDP_INTF_REV_7xxx_INTR_EN(0),
>   		MDP_INTF_REV_7xxx_INTR_STATUS(0)
>   	},
> -	[MDP_INTF1_7xxx_INTR] = {
> +	[MDP_INTF1_INTR] = {
>   		MDP_INTF_REV_7xxx_INTR_CLEAR(1),
>   		MDP_INTF_REV_7xxx_INTR_EN(1),
>   		MDP_INTF_REV_7xxx_INTR_STATUS(1)
>   	},
> -	[MDP_INTF1_7xxx_TEAR_INTR] = {
> +	[MDP_INTF1_TEAR_INTR] = {
>   		MDP_INTF_REV_7xxx_INTR_TEAR_CLEAR(1),
>   		MDP_INTF_REV_7xxx_INTR_TEAR_EN(1),
>   		MDP_INTF_REV_7xxx_INTR_TEAR_STATUS(1)
>   	},
> -	[MDP_INTF2_7xxx_INTR] = {
> +	[MDP_INTF2_INTR] = {
>   		MDP_INTF_REV_7xxx_INTR_CLEAR(2),
>   		MDP_INTF_REV_7xxx_INTR_EN(2),
>   		MDP_INTF_REV_7xxx_INTR_STATUS(2)
>   	},
> -	[MDP_INTF2_7xxx_TEAR_INTR] = {
> +	[MDP_INTF2_TEAR_INTR] = {
>   		MDP_INTF_REV_7xxx_INTR_TEAR_CLEAR(2),
>   		MDP_INTF_REV_7xxx_INTR_TEAR_EN(2),
>   		MDP_INTF_REV_7xxx_INTR_TEAR_STATUS(2)
>   	},
> -	[MDP_INTF3_7xxx_INTR] = {
> +	[MDP_INTF3_INTR] = {
>   		MDP_INTF_REV_7xxx_INTR_CLEAR(3),
>   		MDP_INTF_REV_7xxx_INTR_EN(3),
>   		MDP_INTF_REV_7xxx_INTR_STATUS(3)
>   	},
> -	[MDP_INTF4_7xxx_INTR] = {
> +	[MDP_INTF4_INTR] = {
>   		MDP_INTF_REV_7xxx_INTR_CLEAR(4),
>   		MDP_INTF_REV_7xxx_INTR_EN(4),
>   		MDP_INTF_REV_7xxx_INTR_STATUS(4)
>   	},
> -	[MDP_INTF5_7xxx_INTR] = {
> +	[MDP_INTF5_INTR] = {
>   		MDP_INTF_REV_7xxx_INTR_CLEAR(5),
>   		MDP_INTF_REV_7xxx_INTR_EN(5),
>   		MDP_INTF_REV_7xxx_INTR_STATUS(5)
>   	},
> -	[MDP_INTF6_7xxx_INTR] = {
> +	[MDP_INTF6_INTR] = {
>   		MDP_INTF_REV_7xxx_INTR_CLEAR(6),
>   		MDP_INTF_REV_7xxx_INTR_EN(6),
>   		MDP_INTF_REV_7xxx_INTR_STATUS(6)
>   	},
> -	[MDP_INTF7_7xxx_INTR] = {
> +	[MDP_INTF7_INTR] = {
>   		MDP_INTF_REV_7xxx_INTR_CLEAR(7),
>   		MDP_INTF_REV_7xxx_INTR_EN(7),
>   		MDP_INTF_REV_7xxx_INTR_STATUS(7)
>   	},
> -	[MDP_INTF8_7xxx_INTR] = {
> +	[MDP_INTF8_INTR] = {
>   		MDP_INTF_REV_7xxx_INTR_CLEAR(8),
>   		MDP_INTF_REV_7xxx_INTR_EN(8),
>   		MDP_INTF_REV_7xxx_INTR_STATUS(8)
> @@ -216,19 +235,19 @@ irqreturn_t dpu_core_irq(struct msm_kms *kms)
>   		return IRQ_NONE;
>   
>   	spin_lock_irqsave(&intr->irq_lock, irq_flags);
> -	for (reg_idx = 0; reg_idx < ARRAY_SIZE(dpu_intr_set); reg_idx++) {
> +	for (reg_idx = 0; reg_idx < MDP_INTR_MAX; reg_idx++) {
>   		if (!test_bit(reg_idx, &intr->irq_mask))
>   			continue;
>   
>   		/* Read interrupt status */
> -		irq_status = DPU_REG_READ(&intr->hw, dpu_intr_set[reg_idx].status_off);
> +		irq_status = DPU_REG_READ(&intr->hw, intr->intr_set[reg_idx].status_off);
>   
>   		/* Read enable mask */
> -		enable_mask = DPU_REG_READ(&intr->hw, dpu_intr_set[reg_idx].en_off);
> +		enable_mask = DPU_REG_READ(&intr->hw, intr->intr_set[reg_idx].en_off);
>   
>   		/* and clear the interrupt */
>   		if (irq_status)
> -			DPU_REG_WRITE(&intr->hw, dpu_intr_set[reg_idx].clr_off,
> +			DPU_REG_WRITE(&intr->hw, intr->intr_set[reg_idx].clr_off,
>   				     irq_status);
>   
>   		/* Finally update IRQ status based on enable mask */
> @@ -285,7 +304,11 @@ static int dpu_hw_intr_enable_irq_locked(struct dpu_hw_intr *intr, int irq_idx)
>   	assert_spin_locked(&intr->irq_lock);
>   
>   	reg_idx = DPU_IRQ_REG(irq_idx);
> -	reg = &dpu_intr_set[reg_idx];
> +	reg = &intr->intr_set[reg_idx];
> +
> +	/* Is this interrupt register supported on the platform */
> +	if (WARN_ON(!reg->en_off))
> +		return -EINVAL;
>   
>   	cache_irq_mask = intr->cache_irq_mask[reg_idx];
>   	if (cache_irq_mask & DPU_IRQ_MASK(irq_idx)) {
> @@ -334,7 +357,7 @@ static int dpu_hw_intr_disable_irq_locked(struct dpu_hw_intr *intr, int irq_idx)
>   	assert_spin_locked(&intr->irq_lock);
>   
>   	reg_idx = DPU_IRQ_REG(irq_idx);
> -	reg = &dpu_intr_set[reg_idx];
> +	reg = &intr->intr_set[reg_idx];
>   
>   	cache_irq_mask = intr->cache_irq_mask[reg_idx];
>   	if ((cache_irq_mask & DPU_IRQ_MASK(irq_idx)) == 0) {
> @@ -368,10 +391,10 @@ static void dpu_clear_irqs(struct dpu_kms *dpu_kms)
>   	if (!intr)
>   		return;
>   
> -	for (i = 0; i < ARRAY_SIZE(dpu_intr_set); i++) {
> +	for (i = 0; i < MDP_INTR_MAX; i++) {
>   		if (test_bit(i, &intr->irq_mask))
>   			DPU_REG_WRITE(&intr->hw,
> -					dpu_intr_set[i].clr_off, 0xffffffff);
> +					intr->intr_set[i].clr_off, 0xffffffff);
>   	}
>   
>   	/* ensure register writes go through */
> @@ -386,10 +409,10 @@ static void dpu_disable_all_irqs(struct dpu_kms *dpu_kms)
>   	if (!intr)
>   		return;
>   
> -	for (i = 0; i < ARRAY_SIZE(dpu_intr_set); i++) {
> +	for (i = 0; i < MDP_INTR_MAX; i++) {
>   		if (test_bit(i, &intr->irq_mask))
>   			DPU_REG_WRITE(&intr->hw,
> -					dpu_intr_set[i].en_off, 0x00000000);
> +					intr->intr_set[i].en_off, 0x00000000);
>   	}
>   
>   	/* ensure register writes go through */
> @@ -421,10 +444,10 @@ u32 dpu_core_irq_read(struct dpu_kms *dpu_kms, int irq_idx)
>   
>   	reg_idx = DPU_IRQ_REG(irq_idx);
>   	intr_status = DPU_REG_READ(&intr->hw,
> -			dpu_intr_set[reg_idx].status_off) &
> +			intr->intr_set[reg_idx].status_off) &
>   		DPU_IRQ_MASK(irq_idx);
>   	if (intr_status)
> -		DPU_REG_WRITE(&intr->hw, dpu_intr_set[reg_idx].clr_off,
> +		DPU_REG_WRITE(&intr->hw, intr->intr_set[reg_idx].clr_off,
>   				intr_status);
>   
>   	/* ensure register writes go through */
> @@ -448,6 +471,11 @@ struct dpu_hw_intr *dpu_hw_intr_init(void __iomem *addr,
>   	if (!intr)
>   		return ERR_PTR(-ENOMEM);
>   
> +	if (m->caps->has_7xxx_intr)
> +		intr->intr_set = dpu_intr_set_7xxx;
> +	else
> +		intr->intr_set = dpu_intr_set_legacy;
> +
>   	intr->hw.blk_addr = addr + m->mdp[0].base;
>   
>   	intr->total_irqs = nirq;
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h
> index 1f2dabc54c22..f329d6d7f646 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h
> @@ -23,24 +23,29 @@ enum dpu_hw_intr_reg {
>   	MDP_INTF3_INTR,
>   	MDP_INTF4_INTR,
>   	MDP_INTF5_INTR,
> +	MDP_INTF6_INTR,
> +	MDP_INTF7_INTR,
> +	MDP_INTF8_INTR,
>   	MDP_INTF1_TEAR_INTR,
>   	MDP_INTF2_TEAR_INTR,
>   	MDP_AD4_0_INTR,
>   	MDP_AD4_1_INTR,
> -	MDP_INTF0_7xxx_INTR,
> -	MDP_INTF1_7xxx_INTR,
> -	MDP_INTF1_7xxx_TEAR_INTR,
> -	MDP_INTF2_7xxx_INTR,
> -	MDP_INTF2_7xxx_TEAR_INTR,
> -	MDP_INTF3_7xxx_INTR,
> -	MDP_INTF4_7xxx_INTR,
> -	MDP_INTF5_7xxx_INTR,
> -	MDP_INTF6_7xxx_INTR,
> -	MDP_INTF7_7xxx_INTR,
> -	MDP_INTF8_7xxx_INTR,
>   	MDP_INTR_MAX,
>   };
>   
> +/* compatibility */
> +#define MDP_INTF0_7xxx_INTR MDP_INTF0_INTR
> +#define MDP_INTF1_7xxx_INTR MDP_INTF1_INTR
> +#define MDP_INTF2_7xxx_INTR MDP_INTF2_INTR
> +#define MDP_INTF3_7xxx_INTR MDP_INTF3_INTR
> +#define MDP_INTF4_7xxx_INTR MDP_INTF4_INTR
> +#define MDP_INTF5_7xxx_INTR MDP_INTF5_INTR
> +#define MDP_INTF6_7xxx_INTR MDP_INTF6_INTR
> +#define MDP_INTF7_7xxx_INTR MDP_INTF7_INTR
> +#define MDP_INTF8_7xxx_INTR MDP_INTF8_INTR
> +#define MDP_INTF1_7xxx_TEAR_INTR MDP_INTF1_TEAR_INTR
> +#define MDP_INTF2_7xxx_TEAR_INTR MDP_INTF2_TEAR_INTR
> +
>   #define DPU_IRQ_IDX(reg_idx, offset)	(reg_idx * 32 + offset)
>   
>   /**
> @@ -60,6 +65,7 @@ struct dpu_hw_intr {
>   	u32 total_irqs;
>   	spinlock_t irq_lock;
>   	unsigned long irq_mask;
> +	const struct dpu_intr_reg *intr_set;
>   
>   	struct {
>   		void (*cb)(void *arg, int irq_idx);

Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>

[PATCH v2 4/6] drm/msm/dpu: autodetect supported interrupts

[Dmitry Baryshkov]

Declaring the mask of supported interrupts proved to be error-prone. It
is very easy to add a bit with no corresponding backing block or to miss
the INTF TE bit. Replace this with looping over the enabled INTF blocks
to setup the irq mask.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
 .../gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c | 20 ++++++++++++++++++-
 .../gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h |  6 ++++++
 2 files changed, 25 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c
index a03d826bb9ad..01f2660a2354 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c
@@ -463,6 +463,7 @@ struct dpu_hw_intr *dpu_hw_intr_init(void __iomem *addr,
 {
 	struct dpu_hw_intr *intr;
 	int nirq = MDP_INTR_MAX * 32;
+	unsigned int i;
 
 	if (!addr || !m)
 		return ERR_PTR(-EINVAL);
@@ -480,7 +481,24 @@ struct dpu_hw_intr *dpu_hw_intr_init(void __iomem *addr,
 
 	intr->total_irqs = nirq;
 
-	intr->irq_mask = m->mdss_irqs;
+	intr->irq_mask = BIT(MDP_SSPP_TOP0_INTR) |
+			 BIT(MDP_SSPP_TOP0_INTR2) |
+			 BIT(MDP_SSPP_TOP0_HIST_INTR);
+	for (i = 0; i < m->intf_count; i++) {
+		const struct dpu_intf_cfg *intf = &m->intf[i];
+
+		if (intf->type == INTF_NONE)
+			continue;
+
+		intr->irq_mask |= BIT(MDP_INTFn_INTR(intf->id));
+
+		if (test_bit(DPU_INTF_TE, &intf->features)) {
+			unsigned idx = MDP_INTFn_TEAR_INTR(intf->id);
+
+			if (!WARN_ON(idx == -1))
+				intr->irq_mask |= BIT(idx);
+		}
+	}
 
 	spin_lock_init(&intr->irq_lock);
 
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h
index f329d6d7f646..f0b92c9e3b09 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h
@@ -17,6 +17,7 @@ enum dpu_hw_intr_reg {
 	MDP_SSPP_TOP0_INTR,
 	MDP_SSPP_TOP0_INTR2,
 	MDP_SSPP_TOP0_HIST_INTR,
+	/* All MDP_INTFn_INTR should come sequentially */
 	MDP_INTF0_INTR,
 	MDP_INTF1_INTR,
 	MDP_INTF2_INTR,
@@ -33,6 +34,11 @@ enum dpu_hw_intr_reg {
 	MDP_INTR_MAX,
 };
 
+#define MDP_INTFn_INTR(intf)	(MDP_INTF0_INTR + (intf - INTF_0))
+#define MDP_INTFn_TEAR_INTR(intf) (intf == INTF_1 ? MDP_INTF1_TEAR_INTR : \
+				   intf == INTF_2 ? MDP_INTF2_TEAR_INTR : \
+				   -1)
+
 /* compatibility */
 #define MDP_INTF0_7xxx_INTR MDP_INTF0_INTR
 #define MDP_INTF1_7xxx_INTR MDP_INTF1_INTR
-- 
2.39.2

Re: [PATCH v2 4/6] drm/msm/dpu: autodetect supported interrupts

[Marijn Suijten]

On 2023-05-23 00:45:25, Dmitry Baryshkov wrote:
> Declaring the mask of supported interrupts proved to be error-prone. It
> is very easy to add a bit with no corresponding backing block or to miss
> the INTF TE bit. Replace this with looping over the enabled INTF blocks
> to setup the irq mask.
> 
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>

Reviewed-by: Marijn Suijten <marijn.suijten@somainline.org>

> ---
>  .../gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c | 20 ++++++++++++++++++-
>  .../gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h |  6 ++++++
>  2 files changed, 25 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c
> index a03d826bb9ad..01f2660a2354 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c
> @@ -463,6 +463,7 @@ struct dpu_hw_intr *dpu_hw_intr_init(void __iomem *addr,
>  {
>  	struct dpu_hw_intr *intr;
>  	int nirq = MDP_INTR_MAX * 32;
> +	unsigned int i;
>  
>  	if (!addr || !m)
>  		return ERR_PTR(-EINVAL);
> @@ -480,7 +481,24 @@ struct dpu_hw_intr *dpu_hw_intr_init(void __iomem *addr,
>  
>  	intr->total_irqs = nirq;
>  
> -	intr->irq_mask = m->mdss_irqs;
> +	intr->irq_mask = BIT(MDP_SSPP_TOP0_INTR) |
> +			 BIT(MDP_SSPP_TOP0_INTR2) |
> +			 BIT(MDP_SSPP_TOP0_HIST_INTR);
> +	for (i = 0; i < m->intf_count; i++) {
> +		const struct dpu_intf_cfg *intf = &m->intf[i];
> +
> +		if (intf->type == INTF_NONE)
> +			continue;
> +
> +		intr->irq_mask |= BIT(MDP_INTFn_INTR(intf->id));
> +
> +		if (test_bit(DPU_INTF_TE, &intf->features)) {
> +			unsigned idx = MDP_INTFn_TEAR_INTR(intf->id);
> +
> +			if (!WARN_ON(idx == -1))

We don't need to validate the catalog?  But warning users about this
(and accidentally turning on all interrupt bits hiding the issue anyway)
is a nice side effect though, as you showed it was already going wrong
in patch 1/6.

OTOH you might have inlined the macro and provided a more useful warning
message (DPU_INTF_TE can only be present on INTF1/2)... and then one
could assert on INTF_DSI etc etc etc...

- Marijn

> +				intr->irq_mask |= BIT(idx);
> +		}
> +	}
>  
>  	spin_lock_init(&intr->irq_lock);
>  
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h
> index f329d6d7f646..f0b92c9e3b09 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h
> @@ -17,6 +17,7 @@ enum dpu_hw_intr_reg {
>  	MDP_SSPP_TOP0_INTR,
>  	MDP_SSPP_TOP0_INTR2,
>  	MDP_SSPP_TOP0_HIST_INTR,
> +	/* All MDP_INTFn_INTR should come sequentially */
>  	MDP_INTF0_INTR,
>  	MDP_INTF1_INTR,
>  	MDP_INTF2_INTR,
> @@ -33,6 +34,11 @@ enum dpu_hw_intr_reg {
>  	MDP_INTR_MAX,
>  };
>  
> +#define MDP_INTFn_INTR(intf)	(MDP_INTF0_INTR + (intf - INTF_0))
> +#define MDP_INTFn_TEAR_INTR(intf) (intf == INTF_1 ? MDP_INTF1_TEAR_INTR : \
> +				   intf == INTF_2 ? MDP_INTF2_TEAR_INTR : \
> +				   -1)
> +
>  /* compatibility */
>  #define MDP_INTF0_7xxx_INTR MDP_INTF0_INTR
>  #define MDP_INTF1_7xxx_INTR MDP_INTF1_INTR
> -- 
> 2.39.2
> 

Re: [PATCH v2 4/6] drm/msm/dpu: autodetect supported interrupts

[Dmitry Baryshkov]

On Tue, 23 May 2023 at 01:12, Marijn Suijten
<marijn.suijten@somainline.org> wrote:
>
> On 2023-05-23 00:45:25, Dmitry Baryshkov wrote:
> > Declaring the mask of supported interrupts proved to be error-prone. It
> > is very easy to add a bit with no corresponding backing block or to miss
> > the INTF TE bit. Replace this with looping over the enabled INTF blocks
> > to setup the irq mask.
> >
> > Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
>
> Reviewed-by: Marijn Suijten <marijn.suijten@somainline.org>
>
> > ---
> >  .../gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c | 20 ++++++++++++++++++-
> >  .../gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h |  6 ++++++
> >  2 files changed, 25 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c
> > index a03d826bb9ad..01f2660a2354 100644
> > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c
> > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c
> > @@ -463,6 +463,7 @@ struct dpu_hw_intr *dpu_hw_intr_init(void __iomem *addr,
> >  {
> >       struct dpu_hw_intr *intr;
> >       int nirq = MDP_INTR_MAX * 32;
> > +     unsigned int i;
> >
> >       if (!addr || !m)
> >               return ERR_PTR(-EINVAL);
> > @@ -480,7 +481,24 @@ struct dpu_hw_intr *dpu_hw_intr_init(void __iomem *addr,
> >
> >       intr->total_irqs = nirq;
> >
> > -     intr->irq_mask = m->mdss_irqs;
> > +     intr->irq_mask = BIT(MDP_SSPP_TOP0_INTR) |
> > +                      BIT(MDP_SSPP_TOP0_INTR2) |
> > +                      BIT(MDP_SSPP_TOP0_HIST_INTR);
> > +     for (i = 0; i < m->intf_count; i++) {
> > +             const struct dpu_intf_cfg *intf = &m->intf[i];
> > +
> > +             if (intf->type == INTF_NONE)
> > +                     continue;
> > +
> > +             intr->irq_mask |= BIT(MDP_INTFn_INTR(intf->id));
> > +
> > +             if (test_bit(DPU_INTF_TE, &intf->features)) {
> > +                     unsigned idx = MDP_INTFn_TEAR_INTR(intf->id);
> > +
> > +                     if (!WARN_ON(idx == -1))
>
> We don't need to validate the catalog?  But warning users about this
> (and accidentally turning on all interrupt bits hiding the issue anyway)
> is a nice side effect though, as you showed it was already going wrong
> in patch 1/6.
>
> OTOH you might have inlined the macro and provided a more useful warning
> message (DPU_INTF_TE can only be present on INTF1/2)... and then one
> could assert on INTF_DSI etc etc etc...

I'd prefer to keep it, as a safeguard for submission being in
progress, newer generations gaining TE blocks on other interfaces,
etc.
I was selecting between having explicit intf->id == INTF_1 || ==
INTF_2 condition and this kind of macro.

>
> - Marijn
>
> > +                             intr->irq_mask |= BIT(idx);
> > +             }
> > +     }
> >
> >       spin_lock_init(&intr->irq_lock);
> >
> > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h
> > index f329d6d7f646..f0b92c9e3b09 100644
> > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h
> > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h
> > @@ -17,6 +17,7 @@ enum dpu_hw_intr_reg {
> >       MDP_SSPP_TOP0_INTR,
> >       MDP_SSPP_TOP0_INTR2,
> >       MDP_SSPP_TOP0_HIST_INTR,
> > +     /* All MDP_INTFn_INTR should come sequentially */
> >       MDP_INTF0_INTR,
> >       MDP_INTF1_INTR,
> >       MDP_INTF2_INTR,
> > @@ -33,6 +34,11 @@ enum dpu_hw_intr_reg {
> >       MDP_INTR_MAX,
> >  };
> >
> > +#define MDP_INTFn_INTR(intf) (MDP_INTF0_INTR + (intf - INTF_0))
> > +#define MDP_INTFn_TEAR_INTR(intf) (intf == INTF_1 ? MDP_INTF1_TEAR_INTR : \
> > +                                intf == INTF_2 ? MDP_INTF2_TEAR_INTR : \
> > +                                -1)
> > +
> >  /* compatibility */
> >  #define MDP_INTF0_7xxx_INTR MDP_INTF0_INTR
> >  #define MDP_INTF1_7xxx_INTR MDP_INTF1_INTR
> > --
> > 2.39.2
> >



-- 
With best wishes
Dmitry

Re: [PATCH v2 4/6] drm/msm/dpu: autodetect supported interrupts

[Marijn Suijten]

On 2023-05-23 01:17:50, Dmitry Baryshkov wrote:
> On Tue, 23 May 2023 at 01:12, Marijn Suijten
> <marijn.suijten@somainline.org> wrote:
> >
> > On 2023-05-23 00:45:25, Dmitry Baryshkov wrote:
> > > Declaring the mask of supported interrupts proved to be error-prone. It
> > > is very easy to add a bit with no corresponding backing block or to miss
> > > the INTF TE bit. Replace this with looping over the enabled INTF blocks
> > > to setup the irq mask.
> > >
> > > Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> >
> > Reviewed-by: Marijn Suijten <marijn.suijten@somainline.org>
> >
> > > ---
> > >  .../gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c | 20 ++++++++++++++++++-
> > >  .../gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h |  6 ++++++
> > >  2 files changed, 25 insertions(+), 1 deletion(-)
> > >
> > > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c
> > > index a03d826bb9ad..01f2660a2354 100644
> > > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c
> > > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.c
> > > @@ -463,6 +463,7 @@ struct dpu_hw_intr *dpu_hw_intr_init(void __iomem *addr,
> > >  {
> > >       struct dpu_hw_intr *intr;
> > >       int nirq = MDP_INTR_MAX * 32;
> > > +     unsigned int i;
> > >
> > >       if (!addr || !m)
> > >               return ERR_PTR(-EINVAL);
> > > @@ -480,7 +481,24 @@ struct dpu_hw_intr *dpu_hw_intr_init(void __iomem *addr,
> > >
> > >       intr->total_irqs = nirq;
> > >
> > > -     intr->irq_mask = m->mdss_irqs;
> > > +     intr->irq_mask = BIT(MDP_SSPP_TOP0_INTR) |
> > > +                      BIT(MDP_SSPP_TOP0_INTR2) |
> > > +                      BIT(MDP_SSPP_TOP0_HIST_INTR);
> > > +     for (i = 0; i < m->intf_count; i++) {
> > > +             const struct dpu_intf_cfg *intf = &m->intf[i];
> > > +
> > > +             if (intf->type == INTF_NONE)
> > > +                     continue;
> > > +
> > > +             intr->irq_mask |= BIT(MDP_INTFn_INTR(intf->id));
> > > +
> > > +             if (test_bit(DPU_INTF_TE, &intf->features)) {
> > > +                     unsigned idx = MDP_INTFn_TEAR_INTR(intf->id);
> > > +
> > > +                     if (!WARN_ON(idx == -1))
> >
> > We don't need to validate the catalog?  But warning users about this
> > (and accidentally turning on all interrupt bits hiding the issue anyway)
> > is a nice side effect though, as you showed it was already going wrong
> > in patch 1/6.
> >
> > OTOH you might have inlined the macro and provided a more useful warning
> > message (DPU_INTF_TE can only be present on INTF1/2)... and then one
> > could assert on INTF_DSI etc etc etc...
> 
> I'd prefer to keep it, as a safeguard for submission being in
> progress, newer generations gaining TE blocks on other interfaces,
> etc.
> I was selecting between having explicit intf->id == INTF_1 || ==
> INTF_2 condition and this kind of macro.

Being explicit in-line here has my preference.  Maybe the same for the
above bit, not sure about that one yet (e.g. have an upper bound on
INTF_8).

- Marijn

> 
> >
> > - Marijn
> >
> > > +                             intr->irq_mask |= BIT(idx);
> > > +             }
> > > +     }
> > >
> > >       spin_lock_init(&intr->irq_lock);
> > >
> > > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h
> > > index f329d6d7f646..f0b92c9e3b09 100644
> > > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h
> > > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h
> > > @@ -17,6 +17,7 @@ enum dpu_hw_intr_reg {
> > >       MDP_SSPP_TOP0_INTR,
> > >       MDP_SSPP_TOP0_INTR2,
> > >       MDP_SSPP_TOP0_HIST_INTR,
> > > +     /* All MDP_INTFn_INTR should come sequentially */
> > >       MDP_INTF0_INTR,
> > >       MDP_INTF1_INTR,
> > >       MDP_INTF2_INTR,
> > > @@ -33,6 +34,11 @@ enum dpu_hw_intr_reg {
> > >       MDP_INTR_MAX,
> > >  };
> > >
> > > +#define MDP_INTFn_INTR(intf) (MDP_INTF0_INTR + (intf - INTF_0))
> > > +#define MDP_INTFn_TEAR_INTR(intf) (intf == INTF_1 ? MDP_INTF1_TEAR_INTR : \
> > > +                                intf == INTF_2 ? MDP_INTF2_TEAR_INTR : \
> > > +                                -1)
> > > +
> > >  /* compatibility */
> > >  #define MDP_INTF0_7xxx_INTR MDP_INTF0_INTR
> > >  #define MDP_INTF1_7xxx_INTR MDP_INTF1_INTR
> > > --
> > > 2.39.2
> > >
> 
> 
> 
> -- 
> With best wishes
> Dmitry

[PATCH v2 5/6] drm/msm/dpu: drop now-unused mdss_irqs field from hw catalog

[Dmitry Baryshkov]

Now as the list of the interrupts is constructed from the catalog
data, drop the mdss_irqs field from catalog.

Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
 .../drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h    |  8 --------
 .../gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h |  9 ---------
 .../gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h | 11 -----------
 .../drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h    | 13 -------------
 .../gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h | 10 ----------
 .../gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h |  6 ------
 .../gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h |  5 -----
 .../drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h    |  5 -----
 .../gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h |  9 ---------
 .../gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h |  7 -------
 .../drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h   | 14 --------------
 .../gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h |  9 ---------
 .../gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h |  9 ---------
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h     |  3 ---
 14 files changed, 118 deletions(-)

diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h
index 3c732a0360c7..ff7c3d522046 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h
@@ -204,14 +204,6 @@ const struct dpu_mdss_cfg dpu_msm8998_cfg = {
 	.vbif_count = ARRAY_SIZE(msm8998_vbif),
 	.vbif = msm8998_vbif,
 	.perf = &msm8998_perf_data,
-	.mdss_irqs = BIT(MDP_SSPP_TOP0_INTR) | \
-		     BIT(MDP_SSPP_TOP0_INTR2) | \
-		     BIT(MDP_SSPP_TOP0_HIST_INTR) | \
-		     BIT(MDP_INTF0_INTR) | \
-		     BIT(MDP_INTF1_INTR) | \
-		     BIT(MDP_INTF2_INTR) | \
-		     BIT(MDP_INTF3_INTR) | \
-		     BIT(MDP_INTF4_INTR),
 };
 
 #endif
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h
index 36ea1af10894..c4ccd742690a 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h
@@ -202,15 +202,6 @@ const struct dpu_mdss_cfg dpu_sdm845_cfg = {
 	.vbif_count = ARRAY_SIZE(sdm845_vbif),
 	.vbif = sdm845_vbif,
 	.perf = &sdm845_perf_data,
-	.mdss_irqs = BIT(MDP_SSPP_TOP0_INTR) | \
-		     BIT(MDP_SSPP_TOP0_INTR2) | \
-		     BIT(MDP_SSPP_TOP0_HIST_INTR) | \
-		     BIT(MDP_INTF0_INTR) | \
-		     BIT(MDP_INTF1_INTR) | \
-		     BIT(MDP_INTF2_INTR) | \
-		     BIT(MDP_INTF3_INTR) | \
-		     BIT(MDP_AD4_0_INTR) | \
-		     BIT(MDP_AD4_1_INTR),
 };
 
 #endif
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h
index b5f751354267..fb7069d470ff 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h
@@ -231,17 +231,6 @@ const struct dpu_mdss_cfg dpu_sm8150_cfg = {
 	.vbif_count = ARRAY_SIZE(sdm845_vbif),
 	.vbif = sdm845_vbif,
 	.perf = &sm8150_perf_data,
-	.mdss_irqs = BIT(MDP_SSPP_TOP0_INTR) | \
-		     BIT(MDP_SSPP_TOP0_INTR2) | \
-		     BIT(MDP_SSPP_TOP0_HIST_INTR) | \
-		     BIT(MDP_INTF0_INTR) | \
-		     BIT(MDP_INTF1_INTR) | \
-		     BIT(MDP_INTF1_TEAR_INTR) | \
-		     BIT(MDP_INTF2_INTR) | \
-		     BIT(MDP_INTF2_TEAR_INTR) | \
-		     BIT(MDP_INTF3_INTR) | \
-		     BIT(MDP_AD4_0_INTR) | \
-		     BIT(MDP_AD4_1_INTR),
 };
 
 #endif
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h
index 8ed2b263c5ea..bd7422e597aa 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h
@@ -237,19 +237,6 @@ const struct dpu_mdss_cfg dpu_sc8180x_cfg = {
 	.vbif_count = ARRAY_SIZE(sdm845_vbif),
 	.vbif = sdm845_vbif,
 	.perf = &sc8180x_perf_data,
-	.mdss_irqs = BIT(MDP_SSPP_TOP0_INTR) | \
-		     BIT(MDP_SSPP_TOP0_INTR2) | \
-		     BIT(MDP_SSPP_TOP0_HIST_INTR) | \
-		     BIT(MDP_INTF0_INTR) | \
-		     BIT(MDP_INTF1_INTR) | \
-		     BIT(MDP_INTF1_TEAR_INTR) | \
-		     BIT(MDP_INTF2_INTR) | \
-		     BIT(MDP_INTF2_TEAR_INTR) | \
-		     BIT(MDP_INTF3_INTR) | \
-		     BIT(MDP_INTF4_INTR) | \
-		     BIT(MDP_INTF5_INTR) | \
-		     BIT(MDP_AD4_0_INTR) | \
-		     BIT(MDP_AD4_1_INTR),
 };
 
 #endif
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h
index daebd2170041..75a5c1b5a74a 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h
@@ -239,16 +239,6 @@ const struct dpu_mdss_cfg dpu_sm8250_cfg = {
 	.wb_count = ARRAY_SIZE(sm8250_wb),
 	.wb = sm8250_wb,
 	.perf = &sm8250_perf_data,
-	.mdss_irqs = BIT(MDP_SSPP_TOP0_INTR) | \
-		     BIT(MDP_SSPP_TOP0_INTR2) | \
-		     BIT(MDP_SSPP_TOP0_HIST_INTR) | \
-		     BIT(MDP_INTF0_INTR) | \
-		     BIT(MDP_INTF1_INTR) | \
-		     BIT(MDP_INTF1_TEAR_INTR) | \
-		     BIT(MDP_INTF2_INTR) | \
-		     BIT(MDP_INTF2_TEAR_INTR) | \
-		     BIT(MDP_INTF3_INTR) | \
-		     BIT(MDP_INTF4_INTR),
 };
 
 #endif
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h
index 0b05da2592c0..84be02ce9c9c 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h
@@ -149,12 +149,6 @@ const struct dpu_mdss_cfg dpu_sc7180_cfg = {
 	.vbif_count = ARRAY_SIZE(sdm845_vbif),
 	.vbif = sdm845_vbif,
 	.perf = &sc7180_perf_data,
-	.mdss_irqs = BIT(MDP_SSPP_TOP0_INTR) | \
-		     BIT(MDP_SSPP_TOP0_INTR2) | \
-		     BIT(MDP_SSPP_TOP0_HIST_INTR) | \
-		     BIT(MDP_INTF0_INTR) | \
-		     BIT(MDP_INTF1_INTR) | \
-		     BIT(MDP_INTF1_TEAR_INTR),
 };
 
 #endif
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h
index ba9de008519b..71d6e036a7a7 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h
@@ -122,11 +122,6 @@ const struct dpu_mdss_cfg dpu_sm6115_cfg = {
 	.vbif_count = ARRAY_SIZE(sdm845_vbif),
 	.vbif = sdm845_vbif,
 	.perf = &sm6115_perf_data,
-	.mdss_irqs = BIT(MDP_SSPP_TOP0_INTR) | \
-		     BIT(MDP_SSPP_TOP0_INTR2) | \
-		     BIT(MDP_SSPP_TOP0_HIST_INTR) | \
-		     BIT(MDP_INTF1_INTR) | \
-		     BIT(MDP_INTF1_TEAR_INTR),
 };
 
 #endif
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h
index 92ac348eea6b..d80b383d874d 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h
@@ -112,11 +112,6 @@ const struct dpu_mdss_cfg dpu_qcm2290_cfg = {
 	.vbif_count = ARRAY_SIZE(sdm845_vbif),
 	.vbif = sdm845_vbif,
 	.perf = &qcm2290_perf_data,
-	.mdss_irqs = BIT(MDP_SSPP_TOP0_INTR) | \
-		     BIT(MDP_SSPP_TOP0_INTR2) | \
-		     BIT(MDP_SSPP_TOP0_HIST_INTR) | \
-		     BIT(MDP_INTF1_INTR) | \
-		     BIT(MDP_INTF1_TEAR_INTR),
 };
 
 #endif
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h
index 320cfa4be633..649784aa6567 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h
@@ -223,15 +223,6 @@ const struct dpu_mdss_cfg dpu_sm8350_cfg = {
 	.vbif_count = ARRAY_SIZE(sdm845_vbif),
 	.vbif = sdm845_vbif,
 	.perf = &sm8350_perf_data,
-	.mdss_irqs = BIT(MDP_SSPP_TOP0_INTR) | \
-		     BIT(MDP_SSPP_TOP0_INTR2) | \
-		     BIT(MDP_SSPP_TOP0_HIST_INTR) | \
-		     BIT(MDP_INTF0_7xxx_INTR) | \
-		     BIT(MDP_INTF1_7xxx_INTR) | \
-		     BIT(MDP_INTF1_7xxx_TEAR_INTR) | \
-		     BIT(MDP_INTF2_7xxx_INTR) | \
-		     BIT(MDP_INTF2_7xxx_TEAR_INTR) | \
-		     BIT(MDP_INTF3_7xxx_INTR),
 };
 
 #endif
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h
index 9306c7a115e9..1e87c7f4775d 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h
@@ -163,13 +163,6 @@ const struct dpu_mdss_cfg dpu_sc7280_cfg = {
 	.vbif_count = ARRAY_SIZE(sdm845_vbif),
 	.vbif = sdm845_vbif,
 	.perf = &sc7280_perf_data,
-	.mdss_irqs = BIT(MDP_SSPP_TOP0_INTR) | \
-		     BIT(MDP_SSPP_TOP0_INTR2) | \
-		     BIT(MDP_SSPP_TOP0_HIST_INTR) | \
-		     BIT(MDP_INTF0_7xxx_INTR) | \
-		     BIT(MDP_INTF1_7xxx_INTR) | \
-		     BIT(MDP_INTF1_7xxx_TEAR_INTR) | \
-		     BIT(MDP_INTF5_7xxx_INTR),
 };
 
 #endif
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h
index fc1e17c495f0..3082657f06f2 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h
@@ -225,20 +225,6 @@ const struct dpu_mdss_cfg dpu_sc8280xp_cfg = {
 	.vbif_count = ARRAY_SIZE(sdm845_vbif),
 	.vbif = sdm845_vbif,
 	.perf = &sc8280xp_perf_data,
-	.mdss_irqs = BIT(MDP_SSPP_TOP0_INTR) | \
-		     BIT(MDP_SSPP_TOP0_INTR2) | \
-		     BIT(MDP_SSPP_TOP0_HIST_INTR) | \
-		     BIT(MDP_INTF0_7xxx_INTR) | \
-		     BIT(MDP_INTF1_7xxx_INTR) | \
-		     BIT(MDP_INTF1_7xxx_TEAR_INTR) | \
-		     BIT(MDP_INTF2_7xxx_INTR) | \
-		     BIT(MDP_INTF2_7xxx_TEAR_INTR) | \
-		     BIT(MDP_INTF3_7xxx_INTR) | \
-		     BIT(MDP_INTF4_7xxx_INTR) | \
-		     BIT(MDP_INTF5_7xxx_INTR) | \
-		     BIT(MDP_INTF6_7xxx_INTR) | \
-		     BIT(MDP_INTF7_7xxx_INTR) | \
-		     BIT(MDP_INTF8_7xxx_INTR),
 };
 
 #endif
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h
index eb72411c16db..ca5b82bc8322 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h
@@ -231,15 +231,6 @@ const struct dpu_mdss_cfg dpu_sm8450_cfg = {
 	.vbif_count = ARRAY_SIZE(sdm845_vbif),
 	.vbif = sdm845_vbif,
 	.perf = &sm8450_perf_data,
-	.mdss_irqs = BIT(MDP_SSPP_TOP0_INTR) | \
-		     BIT(MDP_SSPP_TOP0_INTR2) | \
-		     BIT(MDP_SSPP_TOP0_HIST_INTR) | \
-		     BIT(MDP_INTF0_7xxx_INTR) | \
-		     BIT(MDP_INTF1_7xxx_INTR) | \
-		     BIT(MDP_INTF1_7xxx_TEAR_INTR) | \
-		     BIT(MDP_INTF2_7xxx_INTR) | \
-		     BIT(MDP_INTF2_7xxx_TEAR_INTR) | \
-		     BIT(MDP_INTF3_7xxx_INTR),
 };
 
 #endif
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h
index 8209ca317bdc..dd7c87f772ea 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h
@@ -235,15 +235,6 @@ const struct dpu_mdss_cfg dpu_sm8550_cfg = {
 	.vbif_count = ARRAY_SIZE(sdm845_vbif),
 	.vbif = sdm845_vbif,
 	.perf = &sm8550_perf_data,
-	.mdss_irqs = BIT(MDP_SSPP_TOP0_INTR) | \
-		     BIT(MDP_SSPP_TOP0_INTR2) | \
-		     BIT(MDP_SSPP_TOP0_HIST_INTR) | \
-		     BIT(MDP_INTF0_7xxx_INTR) | \
-		     BIT(MDP_INTF1_7xxx_INTR) | \
-		     BIT(MDP_INTF1_7xxx_TEAR_INTR) | \
-		     BIT(MDP_INTF2_7xxx_INTR) | \
-		     BIT(MDP_INTF2_7xxx_TEAR_INTR) | \
-		     BIT(MDP_INTF3_7xxx_INTR),
 };
 
 #endif
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
index 72530ebb0ae6..6d8c2fa8558a 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
@@ -777,7 +777,6 @@ struct dpu_perf_cfg {
  * @dma_formats        Supported formats for dma pipe
  * @cursor_formats     Supported formats for cursor pipe
  * @vig_formats        Supported formats for vig pipe
- * @mdss_irqs:         Bitmap with the irqs supported by the target
  */
 struct dpu_mdss_cfg {
 	const struct dpu_caps *caps;
@@ -825,8 +824,6 @@ struct dpu_mdss_cfg {
 	const struct dpu_format_extended *dma_formats;
 	const struct dpu_format_extended *cursor_formats;
 	const struct dpu_format_extended *vig_formats;
-
-	unsigned long mdss_irqs;
 };
 
 extern const struct dpu_mdss_cfg dpu_msm8998_cfg;
-- 
2.39.2

Re: [PATCH v2 5/6] drm/msm/dpu: drop now-unused mdss_irqs field from hw catalog

[Marijn Suijten]

On 2023-05-23 00:45:26, Dmitry Baryshkov wrote:
> Now as the list of the interrupts is constructed from the catalog
> data, drop the mdss_irqs field from catalog.
> 
> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> ---
>  .../drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h    |  8 --------
>  .../gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h |  9 ---------
>  .../gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h | 11 -----------
>  .../drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h    | 13 -------------
>  .../gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h | 10 ----------
>  .../gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h |  6 ------
>  .../gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h |  5 -----
>  .../drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h    |  5 -----
>  .../gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h |  9 ---------
>  .../gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h |  7 -------
>  .../drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h   | 14 --------------
>  .../gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h |  9 ---------
>  .../gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h |  9 ---------
>  drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h     |  3 ---
>  14 files changed, 118 deletions(-)
> 
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h
> index 3c732a0360c7..ff7c3d522046 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h
> @@ -204,14 +204,6 @@ const struct dpu_mdss_cfg dpu_msm8998_cfg = {
>  	.vbif_count = ARRAY_SIZE(msm8998_vbif),
>  	.vbif = msm8998_vbif,
>  	.perf = &msm8998_perf_data,
> -	.mdss_irqs = BIT(MDP_SSPP_TOP0_INTR) | \
> -		     BIT(MDP_SSPP_TOP0_INTR2) | \
> -		     BIT(MDP_SSPP_TOP0_HIST_INTR) | \
> -		     BIT(MDP_INTF0_INTR) | \
> -		     BIT(MDP_INTF1_INTR) | \
> -		     BIT(MDP_INTF2_INTR) | \
> -		     BIT(MDP_INTF3_INTR) | \
> -		     BIT(MDP_INTF4_INTR),
>  };
>  
>  #endif
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h
> index 36ea1af10894..c4ccd742690a 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h
> @@ -202,15 +202,6 @@ const struct dpu_mdss_cfg dpu_sdm845_cfg = {
>  	.vbif_count = ARRAY_SIZE(sdm845_vbif),
>  	.vbif = sdm845_vbif,
>  	.perf = &sdm845_perf_data,
> -	.mdss_irqs = BIT(MDP_SSPP_TOP0_INTR) | \
> -		     BIT(MDP_SSPP_TOP0_INTR2) | \
> -		     BIT(MDP_SSPP_TOP0_HIST_INTR) | \
> -		     BIT(MDP_INTF0_INTR) | \
> -		     BIT(MDP_INTF1_INTR) | \
> -		     BIT(MDP_INTF2_INTR) | \
> -		     BIT(MDP_INTF3_INTR) | \
> -		     BIT(MDP_AD4_0_INTR) | \
> -		     BIT(MDP_AD4_1_INTR),

I don't think you're adding AD4 back anywhere?  Not that there is
any code handling AD4 (e.g. registering those interrupts) anywhere, but
that should be done and documented in a separate patch then.

After dropping that from this patch and describing it in a preliminary
one:

Reviewed-by: Marijn Suijten <marijn.suijten@somainline.org>

>  };
>  
>  #endif
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h
> index b5f751354267..fb7069d470ff 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h
> @@ -231,17 +231,6 @@ const struct dpu_mdss_cfg dpu_sm8150_cfg = {
>  	.vbif_count = ARRAY_SIZE(sdm845_vbif),
>  	.vbif = sdm845_vbif,
>  	.perf = &sm8150_perf_data,
> -	.mdss_irqs = BIT(MDP_SSPP_TOP0_INTR) | \
> -		     BIT(MDP_SSPP_TOP0_INTR2) | \
> -		     BIT(MDP_SSPP_TOP0_HIST_INTR) | \
> -		     BIT(MDP_INTF0_INTR) | \
> -		     BIT(MDP_INTF1_INTR) | \
> -		     BIT(MDP_INTF1_TEAR_INTR) | \
> -		     BIT(MDP_INTF2_INTR) | \
> -		     BIT(MDP_INTF2_TEAR_INTR) | \
> -		     BIT(MDP_INTF3_INTR) | \
> -		     BIT(MDP_AD4_0_INTR) | \
> -		     BIT(MDP_AD4_1_INTR),
>  };
>  
>  #endif
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h
> index 8ed2b263c5ea..bd7422e597aa 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h
> @@ -237,19 +237,6 @@ const struct dpu_mdss_cfg dpu_sc8180x_cfg = {
>  	.vbif_count = ARRAY_SIZE(sdm845_vbif),
>  	.vbif = sdm845_vbif,
>  	.perf = &sc8180x_perf_data,
> -	.mdss_irqs = BIT(MDP_SSPP_TOP0_INTR) | \
> -		     BIT(MDP_SSPP_TOP0_INTR2) | \
> -		     BIT(MDP_SSPP_TOP0_HIST_INTR) | \
> -		     BIT(MDP_INTF0_INTR) | \
> -		     BIT(MDP_INTF1_INTR) | \
> -		     BIT(MDP_INTF1_TEAR_INTR) | \
> -		     BIT(MDP_INTF2_INTR) | \
> -		     BIT(MDP_INTF2_TEAR_INTR) | \
> -		     BIT(MDP_INTF3_INTR) | \
> -		     BIT(MDP_INTF4_INTR) | \
> -		     BIT(MDP_INTF5_INTR) | \
> -		     BIT(MDP_AD4_0_INTR) | \
> -		     BIT(MDP_AD4_1_INTR),
>  };
>  
>  #endif
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h
> index daebd2170041..75a5c1b5a74a 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h
> @@ -239,16 +239,6 @@ const struct dpu_mdss_cfg dpu_sm8250_cfg = {
>  	.wb_count = ARRAY_SIZE(sm8250_wb),
>  	.wb = sm8250_wb,
>  	.perf = &sm8250_perf_data,
> -	.mdss_irqs = BIT(MDP_SSPP_TOP0_INTR) | \
> -		     BIT(MDP_SSPP_TOP0_INTR2) | \
> -		     BIT(MDP_SSPP_TOP0_HIST_INTR) | \
> -		     BIT(MDP_INTF0_INTR) | \
> -		     BIT(MDP_INTF1_INTR) | \
> -		     BIT(MDP_INTF1_TEAR_INTR) | \
> -		     BIT(MDP_INTF2_INTR) | \
> -		     BIT(MDP_INTF2_TEAR_INTR) | \
> -		     BIT(MDP_INTF3_INTR) | \
> -		     BIT(MDP_INTF4_INTR),
>  };
>  
>  #endif
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h
> index 0b05da2592c0..84be02ce9c9c 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h
> @@ -149,12 +149,6 @@ const struct dpu_mdss_cfg dpu_sc7180_cfg = {
>  	.vbif_count = ARRAY_SIZE(sdm845_vbif),
>  	.vbif = sdm845_vbif,
>  	.perf = &sc7180_perf_data,
> -	.mdss_irqs = BIT(MDP_SSPP_TOP0_INTR) | \
> -		     BIT(MDP_SSPP_TOP0_INTR2) | \
> -		     BIT(MDP_SSPP_TOP0_HIST_INTR) | \
> -		     BIT(MDP_INTF0_INTR) | \
> -		     BIT(MDP_INTF1_INTR) | \
> -		     BIT(MDP_INTF1_TEAR_INTR),
>  };
>  
>  #endif
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h
> index ba9de008519b..71d6e036a7a7 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h
> @@ -122,11 +122,6 @@ const struct dpu_mdss_cfg dpu_sm6115_cfg = {
>  	.vbif_count = ARRAY_SIZE(sdm845_vbif),
>  	.vbif = sdm845_vbif,
>  	.perf = &sm6115_perf_data,
> -	.mdss_irqs = BIT(MDP_SSPP_TOP0_INTR) | \
> -		     BIT(MDP_SSPP_TOP0_INTR2) | \
> -		     BIT(MDP_SSPP_TOP0_HIST_INTR) | \
> -		     BIT(MDP_INTF1_INTR) | \
> -		     BIT(MDP_INTF1_TEAR_INTR),
>  };
>  
>  #endif
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h
> index 92ac348eea6b..d80b383d874d 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h
> @@ -112,11 +112,6 @@ const struct dpu_mdss_cfg dpu_qcm2290_cfg = {
>  	.vbif_count = ARRAY_SIZE(sdm845_vbif),
>  	.vbif = sdm845_vbif,
>  	.perf = &qcm2290_perf_data,
> -	.mdss_irqs = BIT(MDP_SSPP_TOP0_INTR) | \
> -		     BIT(MDP_SSPP_TOP0_INTR2) | \
> -		     BIT(MDP_SSPP_TOP0_HIST_INTR) | \
> -		     BIT(MDP_INTF1_INTR) | \
> -		     BIT(MDP_INTF1_TEAR_INTR),
>  };
>  
>  #endif
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h
> index 320cfa4be633..649784aa6567 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h
> @@ -223,15 +223,6 @@ const struct dpu_mdss_cfg dpu_sm8350_cfg = {
>  	.vbif_count = ARRAY_SIZE(sdm845_vbif),
>  	.vbif = sdm845_vbif,
>  	.perf = &sm8350_perf_data,
> -	.mdss_irqs = BIT(MDP_SSPP_TOP0_INTR) | \
> -		     BIT(MDP_SSPP_TOP0_INTR2) | \
> -		     BIT(MDP_SSPP_TOP0_HIST_INTR) | \
> -		     BIT(MDP_INTF0_7xxx_INTR) | \
> -		     BIT(MDP_INTF1_7xxx_INTR) | \
> -		     BIT(MDP_INTF1_7xxx_TEAR_INTR) | \
> -		     BIT(MDP_INTF2_7xxx_INTR) | \
> -		     BIT(MDP_INTF2_7xxx_TEAR_INTR) | \
> -		     BIT(MDP_INTF3_7xxx_INTR),
>  };
>  
>  #endif
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h
> index 9306c7a115e9..1e87c7f4775d 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h
> @@ -163,13 +163,6 @@ const struct dpu_mdss_cfg dpu_sc7280_cfg = {
>  	.vbif_count = ARRAY_SIZE(sdm845_vbif),
>  	.vbif = sdm845_vbif,
>  	.perf = &sc7280_perf_data,
> -	.mdss_irqs = BIT(MDP_SSPP_TOP0_INTR) | \
> -		     BIT(MDP_SSPP_TOP0_INTR2) | \
> -		     BIT(MDP_SSPP_TOP0_HIST_INTR) | \
> -		     BIT(MDP_INTF0_7xxx_INTR) | \
> -		     BIT(MDP_INTF1_7xxx_INTR) | \
> -		     BIT(MDP_INTF1_7xxx_TEAR_INTR) | \
> -		     BIT(MDP_INTF5_7xxx_INTR),
>  };
>  
>  #endif
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h
> index fc1e17c495f0..3082657f06f2 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h
> @@ -225,20 +225,6 @@ const struct dpu_mdss_cfg dpu_sc8280xp_cfg = {
>  	.vbif_count = ARRAY_SIZE(sdm845_vbif),
>  	.vbif = sdm845_vbif,
>  	.perf = &sc8280xp_perf_data,
> -	.mdss_irqs = BIT(MDP_SSPP_TOP0_INTR) | \
> -		     BIT(MDP_SSPP_TOP0_INTR2) | \
> -		     BIT(MDP_SSPP_TOP0_HIST_INTR) | \
> -		     BIT(MDP_INTF0_7xxx_INTR) | \
> -		     BIT(MDP_INTF1_7xxx_INTR) | \
> -		     BIT(MDP_INTF1_7xxx_TEAR_INTR) | \
> -		     BIT(MDP_INTF2_7xxx_INTR) | \
> -		     BIT(MDP_INTF2_7xxx_TEAR_INTR) | \
> -		     BIT(MDP_INTF3_7xxx_INTR) | \
> -		     BIT(MDP_INTF4_7xxx_INTR) | \
> -		     BIT(MDP_INTF5_7xxx_INTR) | \
> -		     BIT(MDP_INTF6_7xxx_INTR) | \
> -		     BIT(MDP_INTF7_7xxx_INTR) | \
> -		     BIT(MDP_INTF8_7xxx_INTR),
>  };
>  
>  #endif
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h
> index eb72411c16db..ca5b82bc8322 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h
> @@ -231,15 +231,6 @@ const struct dpu_mdss_cfg dpu_sm8450_cfg = {
>  	.vbif_count = ARRAY_SIZE(sdm845_vbif),
>  	.vbif = sdm845_vbif,
>  	.perf = &sm8450_perf_data,
> -	.mdss_irqs = BIT(MDP_SSPP_TOP0_INTR) | \
> -		     BIT(MDP_SSPP_TOP0_INTR2) | \
> -		     BIT(MDP_SSPP_TOP0_HIST_INTR) | \
> -		     BIT(MDP_INTF0_7xxx_INTR) | \
> -		     BIT(MDP_INTF1_7xxx_INTR) | \
> -		     BIT(MDP_INTF1_7xxx_TEAR_INTR) | \
> -		     BIT(MDP_INTF2_7xxx_INTR) | \
> -		     BIT(MDP_INTF2_7xxx_TEAR_INTR) | \
> -		     BIT(MDP_INTF3_7xxx_INTR),
>  };
>  
>  #endif
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h
> index 8209ca317bdc..dd7c87f772ea 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h
> @@ -235,15 +235,6 @@ const struct dpu_mdss_cfg dpu_sm8550_cfg = {
>  	.vbif_count = ARRAY_SIZE(sdm845_vbif),
>  	.vbif = sdm845_vbif,
>  	.perf = &sm8550_perf_data,
> -	.mdss_irqs = BIT(MDP_SSPP_TOP0_INTR) | \
> -		     BIT(MDP_SSPP_TOP0_INTR2) | \
> -		     BIT(MDP_SSPP_TOP0_HIST_INTR) | \
> -		     BIT(MDP_INTF0_7xxx_INTR) | \
> -		     BIT(MDP_INTF1_7xxx_INTR) | \
> -		     BIT(MDP_INTF1_7xxx_TEAR_INTR) | \
> -		     BIT(MDP_INTF2_7xxx_INTR) | \
> -		     BIT(MDP_INTF2_7xxx_TEAR_INTR) | \
> -		     BIT(MDP_INTF3_7xxx_INTR),
>  };
>  
>  #endif
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
> index 72530ebb0ae6..6d8c2fa8558a 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
> @@ -777,7 +777,6 @@ struct dpu_perf_cfg {
>   * @dma_formats        Supported formats for dma pipe
>   * @cursor_formats     Supported formats for cursor pipe
>   * @vig_formats        Supported formats for vig pipe
> - * @mdss_irqs:         Bitmap with the irqs supported by the target
>   */
>  struct dpu_mdss_cfg {
>  	const struct dpu_caps *caps;
> @@ -825,8 +824,6 @@ struct dpu_mdss_cfg {
>  	const struct dpu_format_extended *dma_formats;
>  	const struct dpu_format_extended *cursor_formats;
>  	const struct dpu_format_extended *vig_formats;
> -
> -	unsigned long mdss_irqs;
>  };
>  
>  extern const struct dpu_mdss_cfg dpu_msm8998_cfg;
> -- 
> 2.39.2
> 

Re: [PATCH v2 5/6] drm/msm/dpu: drop now-unused mdss_irqs field from hw catalog

[Dmitry Baryshkov]

On Tue, 23 May 2023 at 01:15, Marijn Suijten
<marijn.suijten@somainline.org> wrote:
>
> On 2023-05-23 00:45:26, Dmitry Baryshkov wrote:
> > Now as the list of the interrupts is constructed from the catalog
> > data, drop the mdss_irqs field from catalog.
> >
> > Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
> > Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> > ---
> >  .../drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h    |  8 --------
> >  .../gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h |  9 ---------
> >  .../gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h | 11 -----------
> >  .../drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h    | 13 -------------
> >  .../gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h | 10 ----------
> >  .../gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h |  6 ------
> >  .../gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h |  5 -----
> >  .../drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h    |  5 -----
> >  .../gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h |  9 ---------
> >  .../gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h |  7 -------
> >  .../drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h   | 14 --------------
> >  .../gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h |  9 ---------
> >  .../gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h |  9 ---------
> >  drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h     |  3 ---
> >  14 files changed, 118 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h
> > index 3c732a0360c7..ff7c3d522046 100644
> > --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h
> > +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h
> > @@ -204,14 +204,6 @@ const struct dpu_mdss_cfg dpu_msm8998_cfg = {
> >       .vbif_count = ARRAY_SIZE(msm8998_vbif),
> >       .vbif = msm8998_vbif,
> >       .perf = &msm8998_perf_data,
> > -     .mdss_irqs = BIT(MDP_SSPP_TOP0_INTR) | \
> > -                  BIT(MDP_SSPP_TOP0_INTR2) | \
> > -                  BIT(MDP_SSPP_TOP0_HIST_INTR) | \
> > -                  BIT(MDP_INTF0_INTR) | \
> > -                  BIT(MDP_INTF1_INTR) | \
> > -                  BIT(MDP_INTF2_INTR) | \
> > -                  BIT(MDP_INTF3_INTR) | \
> > -                  BIT(MDP_INTF4_INTR),
> >  };
> >
> >  #endif
> > diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h
> > index 36ea1af10894..c4ccd742690a 100644
> > --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h
> > +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h
> > @@ -202,15 +202,6 @@ const struct dpu_mdss_cfg dpu_sdm845_cfg = {
> >       .vbif_count = ARRAY_SIZE(sdm845_vbif),
> >       .vbif = sdm845_vbif,
> >       .perf = &sdm845_perf_data,
> > -     .mdss_irqs = BIT(MDP_SSPP_TOP0_INTR) | \
> > -                  BIT(MDP_SSPP_TOP0_INTR2) | \
> > -                  BIT(MDP_SSPP_TOP0_HIST_INTR) | \
> > -                  BIT(MDP_INTF0_INTR) | \
> > -                  BIT(MDP_INTF1_INTR) | \
> > -                  BIT(MDP_INTF2_INTR) | \
> > -                  BIT(MDP_INTF3_INTR) | \
> > -                  BIT(MDP_AD4_0_INTR) | \
> > -                  BIT(MDP_AD4_1_INTR),
>
> I don't think you're adding AD4 back anywhere?  Not that there is
> any code handling AD4 (e.g. registering those interrupts) anywhere, but
> that should be done and documented in a separate patch then.
>
> After dropping that from this patch and describing it in a preliminary
> one:
>
> Reviewed-by: Marijn Suijten <marijn.suijten@somainline.org>

Good point.

>
> >  };
> >
> >  #endif
> > diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h
> > index b5f751354267..fb7069d470ff 100644
> > --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h
> > +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h
> > @@ -231,17 +231,6 @@ const struct dpu_mdss_cfg dpu_sm8150_cfg = {
> >       .vbif_count = ARRAY_SIZE(sdm845_vbif),
> >       .vbif = sdm845_vbif,
> >       .perf = &sm8150_perf_data,
> > -     .mdss_irqs = BIT(MDP_SSPP_TOP0_INTR) | \
> > -                  BIT(MDP_SSPP_TOP0_INTR2) | \
> > -                  BIT(MDP_SSPP_TOP0_HIST_INTR) | \
> > -                  BIT(MDP_INTF0_INTR) | \
> > -                  BIT(MDP_INTF1_INTR) | \
> > -                  BIT(MDP_INTF1_TEAR_INTR) | \
> > -                  BIT(MDP_INTF2_INTR) | \
> > -                  BIT(MDP_INTF2_TEAR_INTR) | \
> > -                  BIT(MDP_INTF3_INTR) | \
> > -                  BIT(MDP_AD4_0_INTR) | \
> > -                  BIT(MDP_AD4_1_INTR),
> >  };
> >
> >  #endif
> > diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h
> > index 8ed2b263c5ea..bd7422e597aa 100644
> > --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h
> > +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h
> > @@ -237,19 +237,6 @@ const struct dpu_mdss_cfg dpu_sc8180x_cfg = {
> >       .vbif_count = ARRAY_SIZE(sdm845_vbif),
> >       .vbif = sdm845_vbif,
> >       .perf = &sc8180x_perf_data,
> > -     .mdss_irqs = BIT(MDP_SSPP_TOP0_INTR) | \
> > -                  BIT(MDP_SSPP_TOP0_INTR2) | \
> > -                  BIT(MDP_SSPP_TOP0_HIST_INTR) | \
> > -                  BIT(MDP_INTF0_INTR) | \
> > -                  BIT(MDP_INTF1_INTR) | \
> > -                  BIT(MDP_INTF1_TEAR_INTR) | \
> > -                  BIT(MDP_INTF2_INTR) | \
> > -                  BIT(MDP_INTF2_TEAR_INTR) | \
> > -                  BIT(MDP_INTF3_INTR) | \
> > -                  BIT(MDP_INTF4_INTR) | \
> > -                  BIT(MDP_INTF5_INTR) | \
> > -                  BIT(MDP_AD4_0_INTR) | \
> > -                  BIT(MDP_AD4_1_INTR),
> >  };
> >
> >  #endif
> > diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h
> > index daebd2170041..75a5c1b5a74a 100644
> > --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h
> > +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h
> > @@ -239,16 +239,6 @@ const struct dpu_mdss_cfg dpu_sm8250_cfg = {
> >       .wb_count = ARRAY_SIZE(sm8250_wb),
> >       .wb = sm8250_wb,
> >       .perf = &sm8250_perf_data,
> > -     .mdss_irqs = BIT(MDP_SSPP_TOP0_INTR) | \
> > -                  BIT(MDP_SSPP_TOP0_INTR2) | \
> > -                  BIT(MDP_SSPP_TOP0_HIST_INTR) | \
> > -                  BIT(MDP_INTF0_INTR) | \
> > -                  BIT(MDP_INTF1_INTR) | \
> > -                  BIT(MDP_INTF1_TEAR_INTR) | \
> > -                  BIT(MDP_INTF2_INTR) | \
> > -                  BIT(MDP_INTF2_TEAR_INTR) | \
> > -                  BIT(MDP_INTF3_INTR) | \
> > -                  BIT(MDP_INTF4_INTR),
> >  };
> >
> >  #endif
> > diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h
> > index 0b05da2592c0..84be02ce9c9c 100644
> > --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h
> > +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h
> > @@ -149,12 +149,6 @@ const struct dpu_mdss_cfg dpu_sc7180_cfg = {
> >       .vbif_count = ARRAY_SIZE(sdm845_vbif),
> >       .vbif = sdm845_vbif,
> >       .perf = &sc7180_perf_data,
> > -     .mdss_irqs = BIT(MDP_SSPP_TOP0_INTR) | \
> > -                  BIT(MDP_SSPP_TOP0_INTR2) | \
> > -                  BIT(MDP_SSPP_TOP0_HIST_INTR) | \
> > -                  BIT(MDP_INTF0_INTR) | \
> > -                  BIT(MDP_INTF1_INTR) | \
> > -                  BIT(MDP_INTF1_TEAR_INTR),
> >  };
> >
> >  #endif
> > diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h
> > index ba9de008519b..71d6e036a7a7 100644
> > --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h
> > +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h
> > @@ -122,11 +122,6 @@ const struct dpu_mdss_cfg dpu_sm6115_cfg = {
> >       .vbif_count = ARRAY_SIZE(sdm845_vbif),
> >       .vbif = sdm845_vbif,
> >       .perf = &sm6115_perf_data,
> > -     .mdss_irqs = BIT(MDP_SSPP_TOP0_INTR) | \
> > -                  BIT(MDP_SSPP_TOP0_INTR2) | \
> > -                  BIT(MDP_SSPP_TOP0_HIST_INTR) | \
> > -                  BIT(MDP_INTF1_INTR) | \
> > -                  BIT(MDP_INTF1_TEAR_INTR),
> >  };
> >
> >  #endif
> > diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h
> > index 92ac348eea6b..d80b383d874d 100644
> > --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h
> > +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h
> > @@ -112,11 +112,6 @@ const struct dpu_mdss_cfg dpu_qcm2290_cfg = {
> >       .vbif_count = ARRAY_SIZE(sdm845_vbif),
> >       .vbif = sdm845_vbif,
> >       .perf = &qcm2290_perf_data,
> > -     .mdss_irqs = BIT(MDP_SSPP_TOP0_INTR) | \
> > -                  BIT(MDP_SSPP_TOP0_INTR2) | \
> > -                  BIT(MDP_SSPP_TOP0_HIST_INTR) | \
> > -                  BIT(MDP_INTF1_INTR) | \
> > -                  BIT(MDP_INTF1_TEAR_INTR),
> >  };
> >
> >  #endif
> > diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h
> > index 320cfa4be633..649784aa6567 100644
> > --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h
> > +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h
> > @@ -223,15 +223,6 @@ const struct dpu_mdss_cfg dpu_sm8350_cfg = {
> >       .vbif_count = ARRAY_SIZE(sdm845_vbif),
> >       .vbif = sdm845_vbif,
> >       .perf = &sm8350_perf_data,
> > -     .mdss_irqs = BIT(MDP_SSPP_TOP0_INTR) | \
> > -                  BIT(MDP_SSPP_TOP0_INTR2) | \
> > -                  BIT(MDP_SSPP_TOP0_HIST_INTR) | \
> > -                  BIT(MDP_INTF0_7xxx_INTR) | \
> > -                  BIT(MDP_INTF1_7xxx_INTR) | \
> > -                  BIT(MDP_INTF1_7xxx_TEAR_INTR) | \
> > -                  BIT(MDP_INTF2_7xxx_INTR) | \
> > -                  BIT(MDP_INTF2_7xxx_TEAR_INTR) | \
> > -                  BIT(MDP_INTF3_7xxx_INTR),
> >  };
> >
> >  #endif
> > diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h
> > index 9306c7a115e9..1e87c7f4775d 100644
> > --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h
> > +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h
> > @@ -163,13 +163,6 @@ const struct dpu_mdss_cfg dpu_sc7280_cfg = {
> >       .vbif_count = ARRAY_SIZE(sdm845_vbif),
> >       .vbif = sdm845_vbif,
> >       .perf = &sc7280_perf_data,
> > -     .mdss_irqs = BIT(MDP_SSPP_TOP0_INTR) | \
> > -                  BIT(MDP_SSPP_TOP0_INTR2) | \
> > -                  BIT(MDP_SSPP_TOP0_HIST_INTR) | \
> > -                  BIT(MDP_INTF0_7xxx_INTR) | \
> > -                  BIT(MDP_INTF1_7xxx_INTR) | \
> > -                  BIT(MDP_INTF1_7xxx_TEAR_INTR) | \
> > -                  BIT(MDP_INTF5_7xxx_INTR),
> >  };
> >
> >  #endif
> > diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h
> > index fc1e17c495f0..3082657f06f2 100644
> > --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h
> > +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h
> > @@ -225,20 +225,6 @@ const struct dpu_mdss_cfg dpu_sc8280xp_cfg = {
> >       .vbif_count = ARRAY_SIZE(sdm845_vbif),
> >       .vbif = sdm845_vbif,
> >       .perf = &sc8280xp_perf_data,
> > -     .mdss_irqs = BIT(MDP_SSPP_TOP0_INTR) | \
> > -                  BIT(MDP_SSPP_TOP0_INTR2) | \
> > -                  BIT(MDP_SSPP_TOP0_HIST_INTR) | \
> > -                  BIT(MDP_INTF0_7xxx_INTR) | \
> > -                  BIT(MDP_INTF1_7xxx_INTR) | \
> > -                  BIT(MDP_INTF1_7xxx_TEAR_INTR) | \
> > -                  BIT(MDP_INTF2_7xxx_INTR) | \
> > -                  BIT(MDP_INTF2_7xxx_TEAR_INTR) | \
> > -                  BIT(MDP_INTF3_7xxx_INTR) | \
> > -                  BIT(MDP_INTF4_7xxx_INTR) | \
> > -                  BIT(MDP_INTF5_7xxx_INTR) | \
> > -                  BIT(MDP_INTF6_7xxx_INTR) | \
> > -                  BIT(MDP_INTF7_7xxx_INTR) | \
> > -                  BIT(MDP_INTF8_7xxx_INTR),
> >  };
> >
> >  #endif
> > diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h
> > index eb72411c16db..ca5b82bc8322 100644
> > --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h
> > +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h
> > @@ -231,15 +231,6 @@ const struct dpu_mdss_cfg dpu_sm8450_cfg = {
> >       .vbif_count = ARRAY_SIZE(sdm845_vbif),
> >       .vbif = sdm845_vbif,
> >       .perf = &sm8450_perf_data,
> > -     .mdss_irqs = BIT(MDP_SSPP_TOP0_INTR) | \
> > -                  BIT(MDP_SSPP_TOP0_INTR2) | \
> > -                  BIT(MDP_SSPP_TOP0_HIST_INTR) | \
> > -                  BIT(MDP_INTF0_7xxx_INTR) | \
> > -                  BIT(MDP_INTF1_7xxx_INTR) | \
> > -                  BIT(MDP_INTF1_7xxx_TEAR_INTR) | \
> > -                  BIT(MDP_INTF2_7xxx_INTR) | \
> > -                  BIT(MDP_INTF2_7xxx_TEAR_INTR) | \
> > -                  BIT(MDP_INTF3_7xxx_INTR),
> >  };
> >
> >  #endif
> > diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h
> > index 8209ca317bdc..dd7c87f772ea 100644
> > --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h
> > +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h
> > @@ -235,15 +235,6 @@ const struct dpu_mdss_cfg dpu_sm8550_cfg = {
> >       .vbif_count = ARRAY_SIZE(sdm845_vbif),
> >       .vbif = sdm845_vbif,
> >       .perf = &sm8550_perf_data,
> > -     .mdss_irqs = BIT(MDP_SSPP_TOP0_INTR) | \
> > -                  BIT(MDP_SSPP_TOP0_INTR2) | \
> > -                  BIT(MDP_SSPP_TOP0_HIST_INTR) | \
> > -                  BIT(MDP_INTF0_7xxx_INTR) | \
> > -                  BIT(MDP_INTF1_7xxx_INTR) | \
> > -                  BIT(MDP_INTF1_7xxx_TEAR_INTR) | \
> > -                  BIT(MDP_INTF2_7xxx_INTR) | \
> > -                  BIT(MDP_INTF2_7xxx_TEAR_INTR) | \
> > -                  BIT(MDP_INTF3_7xxx_INTR),
> >  };
> >
> >  #endif
> > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
> > index 72530ebb0ae6..6d8c2fa8558a 100644
> > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
> > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
> > @@ -777,7 +777,6 @@ struct dpu_perf_cfg {
> >   * @dma_formats        Supported formats for dma pipe
> >   * @cursor_formats     Supported formats for cursor pipe
> >   * @vig_formats        Supported formats for vig pipe
> > - * @mdss_irqs:         Bitmap with the irqs supported by the target
> >   */
> >  struct dpu_mdss_cfg {
> >       const struct dpu_caps *caps;
> > @@ -825,8 +824,6 @@ struct dpu_mdss_cfg {
> >       const struct dpu_format_extended *dma_formats;
> >       const struct dpu_format_extended *cursor_formats;
> >       const struct dpu_format_extended *vig_formats;
> > -
> > -     unsigned long mdss_irqs;
> >  };
> >
> >  extern const struct dpu_mdss_cfg dpu_msm8998_cfg;
> > --
> > 2.39.2
> >



-- 
With best wishes
Dmitry

[PATCH v2 6/6] drm/msm/dpu: drop compatibility INTR defines

[Dmitry Baryshkov]

While reworking interrupts masks, it was easier to keep old
MDP_INTFn_7xxx_INTR and MDP_INTFn_7xxx_TEAR_INTR symbols. Now it is time
to drop them and use unified symbol names.

Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
 .../gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h  |  4 ++--
 .../gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h  |  2 +-
 .../drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h    |  4 ++--
 .../gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h  |  4 ++--
 .../gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h  |  4 ++--
 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h   | 13 -------------
 6 files changed, 9 insertions(+), 22 deletions(-)

diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h
index 649784aa6567..df88e3f2a548 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h
@@ -161,11 +161,11 @@ static const struct dpu_intf_cfg sm8350_intf[] = {
 	INTF_BLK_DSI_TE("intf_1", INTF_1, 0x35000, 0x2c4, INTF_DSI, 0, 24, INTF_SC7280_MASK,
 			DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26),
 			DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27),
-			DPU_IRQ_IDX(MDP_INTF1_7xxx_TEAR_INTR, 2)),
+			DPU_IRQ_IDX(MDP_INTF1_TEAR_INTR, 2)),
 	INTF_BLK_DSI_TE("intf_2", INTF_2, 0x36000, 0x2c4, INTF_DSI, 1, 24, INTF_SC7280_MASK,
 			DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 28),
 			DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 29),
-			DPU_IRQ_IDX(MDP_INTF2_7xxx_TEAR_INTR, 2)),
+			DPU_IRQ_IDX(MDP_INTF2_TEAR_INTR, 2)),
 	INTF_BLK("intf_3", INTF_3, 0x37000, 0x280, INTF_DP, MSM_DP_CONTROLLER_1, 24, INTF_SC7280_MASK,
 			DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 30),
 			DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 31)),
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h
index 1e87c7f4775d..4d9936d41464 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h
@@ -107,7 +107,7 @@ static const struct dpu_intf_cfg sc7280_intf[] = {
 	INTF_BLK_DSI_TE("intf_1", INTF_1, 0x35000, 0x2c4, INTF_DSI, 0, 24, INTF_SC7280_MASK,
 			DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26),
 			DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27),
-			DPU_IRQ_IDX(MDP_INTF1_7xxx_TEAR_INTR, 2)),
+			DPU_IRQ_IDX(MDP_INTF1_TEAR_INTR, 2)),
 	INTF_BLK("intf_5", INTF_5, 0x39000, 0x280, INTF_DP, MSM_DP_CONTROLLER_1, 24, INTF_SC7280_MASK,
 			DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 22),
 			DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 23)),
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h
index 3082657f06f2..65fa65b954db 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h
@@ -151,11 +151,11 @@ static const struct dpu_intf_cfg sc8280xp_intf[] = {
 	INTF_BLK_DSI_TE("intf_1", INTF_1, 0x35000, 0x300, INTF_DSI, 0, 24, INTF_SC7280_MASK,
 			DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26),
 			DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27),
-			DPU_IRQ_IDX(MDP_INTF1_7xxx_TEAR_INTR, 2)),
+			DPU_IRQ_IDX(MDP_INTF1_TEAR_INTR, 2)),
 	INTF_BLK_DSI_TE("intf_2", INTF_2, 0x36000, 0x300, INTF_DSI, 1, 24, INTF_SC7280_MASK,
 			DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 28),
 			DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 29),
-			DPU_IRQ_IDX(MDP_INTF2_7xxx_TEAR_INTR, 2)),
+			DPU_IRQ_IDX(MDP_INTF2_TEAR_INTR, 2)),
 	INTF_BLK("intf_3", INTF_3, 0x37000, 0x280, INTF_NONE, MSM_DP_CONTROLLER_0, 24, INTF_SC7280_MASK,
 			DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 30),
 			DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 31)),
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h
index ca5b82bc8322..b8158ed94845 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h
@@ -169,11 +169,11 @@ static const struct dpu_intf_cfg sm8450_intf[] = {
 	INTF_BLK_DSI_TE("intf_1", INTF_1, 0x35000, 0x300, INTF_DSI, 0, 24, INTF_SC7280_MASK,
 			DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26),
 			DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27),
-			DPU_IRQ_IDX(MDP_INTF1_7xxx_TEAR_INTR, 2)),
+			DPU_IRQ_IDX(MDP_INTF1_TEAR_INTR, 2)),
 	INTF_BLK_DSI_TE("intf_2", INTF_2, 0x36000, 0x300, INTF_DSI, 1, 24, INTF_SC7280_MASK,
 			DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 28),
 			DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 29),
-			DPU_IRQ_IDX(MDP_INTF2_7xxx_TEAR_INTR, 2)),
+			DPU_IRQ_IDX(MDP_INTF2_TEAR_INTR, 2)),
 	INTF_BLK("intf_3", INTF_3, 0x37000, 0x280, INTF_DP, MSM_DP_CONTROLLER_1, 24, INTF_SC7280_MASK,
 			DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 30),
 			DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 31)),
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h
index dd7c87f772ea..6a12e882b5b8 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h
@@ -173,11 +173,11 @@ static const struct dpu_intf_cfg sm8550_intf[] = {
 	INTF_BLK_DSI_TE("intf_1", INTF_1, 0x35000, 0x300, INTF_DSI, 0, 24, INTF_SC7280_MASK,
 			DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26),
 			DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27),
-			DPU_IRQ_IDX(MDP_INTF1_7xxx_TEAR_INTR, 2)),
+			DPU_IRQ_IDX(MDP_INTF1_TEAR_INTR, 2)),
 	INTF_BLK_DSI_TE("intf_2", INTF_2, 0x36000, 0x300, INTF_DSI, 1, 24, INTF_SC7280_MASK,
 			DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 28),
 			DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 29),
-			DPU_IRQ_IDX(MDP_INTF2_7xxx_TEAR_INTR, 2)),
+			DPU_IRQ_IDX(MDP_INTF2_TEAR_INTR, 2)),
 	INTF_BLK("intf_3", INTF_3, 0x37000, 0x280, INTF_DP, MSM_DP_CONTROLLER_1, 24, INTF_SC7280_MASK,
 			DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 30),
 			DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 31)),
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h
index f0b92c9e3b09..4a46c0900e04 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h
@@ -39,19 +39,6 @@ enum dpu_hw_intr_reg {
 				   intf == INTF_2 ? MDP_INTF2_TEAR_INTR : \
 				   -1)
 
-/* compatibility */
-#define MDP_INTF0_7xxx_INTR MDP_INTF0_INTR
-#define MDP_INTF1_7xxx_INTR MDP_INTF1_INTR
-#define MDP_INTF2_7xxx_INTR MDP_INTF2_INTR
-#define MDP_INTF3_7xxx_INTR MDP_INTF3_INTR
-#define MDP_INTF4_7xxx_INTR MDP_INTF4_INTR
-#define MDP_INTF5_7xxx_INTR MDP_INTF5_INTR
-#define MDP_INTF6_7xxx_INTR MDP_INTF6_INTR
-#define MDP_INTF7_7xxx_INTR MDP_INTF7_INTR
-#define MDP_INTF8_7xxx_INTR MDP_INTF8_INTR
-#define MDP_INTF1_7xxx_TEAR_INTR MDP_INTF1_TEAR_INTR
-#define MDP_INTF2_7xxx_TEAR_INTR MDP_INTF2_TEAR_INTR
-
 #define DPU_IRQ_IDX(reg_idx, offset)	(reg_idx * 32 + offset)
 
 /**
-- 
2.39.2

Re: [PATCH v2 6/6] drm/msm/dpu: drop compatibility INTR defines

[Marijn Suijten]

On 2023-05-23 00:45:27, Dmitry Baryshkov wrote:
> While reworking interrupts masks, it was easier to keep old
> MDP_INTFn_7xxx_INTR and MDP_INTFn_7xxx_TEAR_INTR symbols. Now it is time
> to drop them and use unified symbol names.
> 
> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>

Reviewed-by: Marijn Suijten <marijn.suijten@somainline.org>

> ---
>  .../gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h  |  4 ++--
>  .../gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h  |  2 +-
>  .../drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h    |  4 ++--
>  .../gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h  |  4 ++--
>  .../gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h  |  4 ++--
>  drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h   | 13 -------------
>  6 files changed, 9 insertions(+), 22 deletions(-)
> 
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h
> index 649784aa6567..df88e3f2a548 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h
> @@ -161,11 +161,11 @@ static const struct dpu_intf_cfg sm8350_intf[] = {
>  	INTF_BLK_DSI_TE("intf_1", INTF_1, 0x35000, 0x2c4, INTF_DSI, 0, 24, INTF_SC7280_MASK,
>  			DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26),
>  			DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27),
> -			DPU_IRQ_IDX(MDP_INTF1_7xxx_TEAR_INTR, 2)),
> +			DPU_IRQ_IDX(MDP_INTF1_TEAR_INTR, 2)),
>  	INTF_BLK_DSI_TE("intf_2", INTF_2, 0x36000, 0x2c4, INTF_DSI, 1, 24, INTF_SC7280_MASK,
>  			DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 28),
>  			DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 29),
> -			DPU_IRQ_IDX(MDP_INTF2_7xxx_TEAR_INTR, 2)),
> +			DPU_IRQ_IDX(MDP_INTF2_TEAR_INTR, 2)),
>  	INTF_BLK("intf_3", INTF_3, 0x37000, 0x280, INTF_DP, MSM_DP_CONTROLLER_1, 24, INTF_SC7280_MASK,
>  			DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 30),
>  			DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 31)),
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h
> index 1e87c7f4775d..4d9936d41464 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h
> @@ -107,7 +107,7 @@ static const struct dpu_intf_cfg sc7280_intf[] = {
>  	INTF_BLK_DSI_TE("intf_1", INTF_1, 0x35000, 0x2c4, INTF_DSI, 0, 24, INTF_SC7280_MASK,
>  			DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26),
>  			DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27),
> -			DPU_IRQ_IDX(MDP_INTF1_7xxx_TEAR_INTR, 2)),
> +			DPU_IRQ_IDX(MDP_INTF1_TEAR_INTR, 2)),
>  	INTF_BLK("intf_5", INTF_5, 0x39000, 0x280, INTF_DP, MSM_DP_CONTROLLER_1, 24, INTF_SC7280_MASK,
>  			DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 22),
>  			DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 23)),
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h
> index 3082657f06f2..65fa65b954db 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h
> @@ -151,11 +151,11 @@ static const struct dpu_intf_cfg sc8280xp_intf[] = {
>  	INTF_BLK_DSI_TE("intf_1", INTF_1, 0x35000, 0x300, INTF_DSI, 0, 24, INTF_SC7280_MASK,
>  			DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26),
>  			DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27),
> -			DPU_IRQ_IDX(MDP_INTF1_7xxx_TEAR_INTR, 2)),
> +			DPU_IRQ_IDX(MDP_INTF1_TEAR_INTR, 2)),
>  	INTF_BLK_DSI_TE("intf_2", INTF_2, 0x36000, 0x300, INTF_DSI, 1, 24, INTF_SC7280_MASK,
>  			DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 28),
>  			DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 29),
> -			DPU_IRQ_IDX(MDP_INTF2_7xxx_TEAR_INTR, 2)),
> +			DPU_IRQ_IDX(MDP_INTF2_TEAR_INTR, 2)),
>  	INTF_BLK("intf_3", INTF_3, 0x37000, 0x280, INTF_NONE, MSM_DP_CONTROLLER_0, 24, INTF_SC7280_MASK,
>  			DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 30),
>  			DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 31)),
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h
> index ca5b82bc8322..b8158ed94845 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h
> @@ -169,11 +169,11 @@ static const struct dpu_intf_cfg sm8450_intf[] = {
>  	INTF_BLK_DSI_TE("intf_1", INTF_1, 0x35000, 0x300, INTF_DSI, 0, 24, INTF_SC7280_MASK,
>  			DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26),
>  			DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27),
> -			DPU_IRQ_IDX(MDP_INTF1_7xxx_TEAR_INTR, 2)),
> +			DPU_IRQ_IDX(MDP_INTF1_TEAR_INTR, 2)),
>  	INTF_BLK_DSI_TE("intf_2", INTF_2, 0x36000, 0x300, INTF_DSI, 1, 24, INTF_SC7280_MASK,
>  			DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 28),
>  			DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 29),
> -			DPU_IRQ_IDX(MDP_INTF2_7xxx_TEAR_INTR, 2)),
> +			DPU_IRQ_IDX(MDP_INTF2_TEAR_INTR, 2)),
>  	INTF_BLK("intf_3", INTF_3, 0x37000, 0x280, INTF_DP, MSM_DP_CONTROLLER_1, 24, INTF_SC7280_MASK,
>  			DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 30),
>  			DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 31)),
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h
> index dd7c87f772ea..6a12e882b5b8 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h
> @@ -173,11 +173,11 @@ static const struct dpu_intf_cfg sm8550_intf[] = {
>  	INTF_BLK_DSI_TE("intf_1", INTF_1, 0x35000, 0x300, INTF_DSI, 0, 24, INTF_SC7280_MASK,
>  			DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26),
>  			DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27),
> -			DPU_IRQ_IDX(MDP_INTF1_7xxx_TEAR_INTR, 2)),
> +			DPU_IRQ_IDX(MDP_INTF1_TEAR_INTR, 2)),
>  	INTF_BLK_DSI_TE("intf_2", INTF_2, 0x36000, 0x300, INTF_DSI, 1, 24, INTF_SC7280_MASK,
>  			DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 28),
>  			DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 29),
> -			DPU_IRQ_IDX(MDP_INTF2_7xxx_TEAR_INTR, 2)),
> +			DPU_IRQ_IDX(MDP_INTF2_TEAR_INTR, 2)),
>  	INTF_BLK("intf_3", INTF_3, 0x37000, 0x280, INTF_DP, MSM_DP_CONTROLLER_1, 24, INTF_SC7280_MASK,
>  			DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 30),
>  			DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 31)),
> diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h
> index f0b92c9e3b09..4a46c0900e04 100644
> --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h
> +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_interrupts.h
> @@ -39,19 +39,6 @@ enum dpu_hw_intr_reg {
>  				   intf == INTF_2 ? MDP_INTF2_TEAR_INTR : \
>  				   -1)
>  
> -/* compatibility */
> -#define MDP_INTF0_7xxx_INTR MDP_INTF0_INTR
> -#define MDP_INTF1_7xxx_INTR MDP_INTF1_INTR
> -#define MDP_INTF2_7xxx_INTR MDP_INTF2_INTR
> -#define MDP_INTF3_7xxx_INTR MDP_INTF3_INTR
> -#define MDP_INTF4_7xxx_INTR MDP_INTF4_INTR
> -#define MDP_INTF5_7xxx_INTR MDP_INTF5_INTR
> -#define MDP_INTF6_7xxx_INTR MDP_INTF6_INTR
> -#define MDP_INTF7_7xxx_INTR MDP_INTF7_INTR
> -#define MDP_INTF8_7xxx_INTR MDP_INTF8_INTR
> -#define MDP_INTF1_7xxx_TEAR_INTR MDP_INTF1_TEAR_INTR
> -#define MDP_INTF2_7xxx_TEAR_INTR MDP_INTF2_TEAR_INTR
> -
>  #define DPU_IRQ_IDX(reg_idx, offset)	(reg_idx * 32 + offset)
>  
>  /**
> -- 
> 2.39.2
>