From: Adam Skladowski <a39.skl@gmail.com>
To: unlisted-recipients:; (no To-header on input)
Cc: phone-devel@vger.kernel.org,
~postmarketos/upstreaming@lists.sr.ht,
Adam Skladowski <a39.skl@gmail.com>,
Bjorn Andersson <andersson@kernel.org>,
Andy Gross <agross@kernel.org>,
Konrad Dybcio <konrad.dybcio@linaro.org>,
Michael Turquette <mturquette@baylibre.com>,
Stephen Boyd <sboyd@kernel.org>, Rob Herring <robh+dt@kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
Conor Dooley <conor+dt@kernel.org>,
AngeloGioacchino Del Regno
<angelogioacchino.delregno@collabora.com>,
Marijn Suijten <marijn.suijten@somainline.org>,
linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org
Subject: [PATCH 5/7] clk: qcom: hfpll: Add MSM8976 PLL data
Date: Sun, 23 Jul 2023 16:06:52 +0200 [thread overview]
Message-ID: <20230723140712.9438-6-a39.skl@gmail.com> (raw)
In-Reply-To: <20230723140712.9438-1-a39.skl@gmail.com>
Add PLL configuration for MSM8976 SoC, this SoC offers 3 HFPLL.
Small cluster offers two presets for 652-902Mhz range and 902Mhz-1.47Ghz.
For simplicity only add second range as smaller frequencies can be obtained
via apcs divider or safe parent this also saves us
a hassle of reconfiguring VCO bit and config_val.
A72 and CCI cluster only use single frequency range with their
outputs/post_dividers/vco_bits being static.
Signed-off-by: Adam Skladowski <a39.skl@gmail.com>
---
drivers/clk/qcom/hfpll.c | 54 ++++++++++++++++++++++++++++++++++++++++
1 file changed, 54 insertions(+)
diff --git a/drivers/clk/qcom/hfpll.c b/drivers/clk/qcom/hfpll.c
index ec18bc8f0089..a9c4c77e0f50 100644
--- a/drivers/clk/qcom/hfpll.c
+++ b/drivers/clk/qcom/hfpll.c
@@ -32,8 +32,62 @@ static const struct hfpll_data hdata = {
.max_rate = 2900000000UL,
};
+static const struct hfpll_data msm8976_a53 = {
+ .mode_reg = 0x00,
+ .l_reg = 0x04,
+ .m_reg = 0x08,
+ .n_reg = 0x0c,
+ .user_reg = 0x10,
+ .config_reg = 0x14,
+ .config_val = 0x341600,
+ .status_reg = 0x1c,
+ .lock_bit = 16,
+
+ .l_val = 0x35,
+ .user_val = 0x109,
+ .min_rate = 902400000UL,
+ .max_rate = 1478400000UL,
+};
+
+static const struct hfpll_data msm8976_a72 = {
+ .mode_reg = 0x00,
+ .l_reg = 0x04,
+ .m_reg = 0x08,
+ .n_reg = 0x0c,
+ .user_reg = 0x10,
+ .config_reg = 0x14,
+ .config_val = 0x4e0405d,
+ .status_reg = 0x1c,
+ .lock_bit = 16,
+
+ .l_val = 0x3e,
+ .user_val = 0x100109,
+ .min_rate = 940800000UL,
+ .max_rate = 1843200000UL,
+};
+
+static const struct hfpll_data msm8976_cci = {
+ .mode_reg = 0x00,
+ .l_reg = 0x04,
+ .m_reg = 0x08,
+ .n_reg = 0x0c,
+ .user_reg = 0x10,
+ .config_reg = 0x14,
+ .config_val = 0x141400,
+ .status_reg = 0x1c,
+ .lock_bit = 16,
+
+ .l_val = 0x20,
+ .user_val = 0x100109,
+ .min_rate = 556800000UL,
+ .max_rate = 902400000UL,
+};
+
static const struct of_device_id qcom_hfpll_match_table[] = {
{ .compatible = "qcom,hfpll", &hdata },
+ { .compatible = "qcom,hfpll-msm8976-a53", &msm8976_a53 },
+ { .compatible = "qcom,hfpll-msm8976-a72", &msm8976_a72 },
+ { .compatible = "qcom,hfpll-msm8976-cci", &msm8976_cci },
{ }
};
MODULE_DEVICE_TABLE(of, qcom_hfpll_match_table);
--
2.41.0
next prev parent reply other threads:[~2023-07-23 14:07 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-07-23 14:06 [PATCH 0/7] MSM8976 PLL,RPMPD and DTS changes Adam Skladowski
2023-07-23 14:06 ` [PATCH 1/7] drivers: soc: qcom: rpmpd: Fix MSM8976 power domains setup Adam Skladowski
2023-07-24 8:48 ` AngeloGioacchino Del Regno
2023-07-23 14:06 ` [PATCH 2/7] clk: qcom: clk-hfpll: Configure l_val in init when required Adam Skladowski
2023-07-23 14:06 ` [PATCH 3/7] clk: qcom: hfpll: Allow matching pdata Adam Skladowski
2023-07-24 8:51 ` AngeloGioacchino Del Regno
2023-07-23 14:06 ` [PATCH 4/7] dt-bindings: clock: qcom,hfpll: Document MSM8976 compatibles Adam Skladowski
2023-07-23 14:34 ` Krzysztof Kozlowski
2023-07-23 14:06 ` Adam Skladowski [this message]
2023-07-23 14:06 ` [PATCH 6/7] arm64: dts: qcom: msm8976: Split lpass region Adam Skladowski
2023-07-24 8:54 ` AngeloGioacchino Del Regno
2023-07-23 14:06 ` [PATCH 7/7] arm64: dts: qcom: msm8976: Fix smsm ipc bit shifts Adam Skladowski
2023-07-23 16:28 ` Marijn Suijten
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20230723140712.9438-6-a39.skl@gmail.com \
--to=a39.skl@gmail.com \
--cc=agross@kernel.org \
--cc=andersson@kernel.org \
--cc=angelogioacchino.delregno@collabora.com \
--cc=conor+dt@kernel.org \
--cc=devicetree@vger.kernel.org \
--cc=konrad.dybcio@linaro.org \
--cc=krzysztof.kozlowski+dt@linaro.org \
--cc=linux-arm-msm@vger.kernel.org \
--cc=linux-clk@vger.kernel.org \
--cc=linux-kernel@vger.kernel.org \
--cc=marijn.suijten@somainline.org \
--cc=mturquette@baylibre.com \
--cc=phone-devel@vger.kernel.org \
--cc=robh+dt@kernel.org \
--cc=sboyd@kernel.org \
--cc=~postmarketos/upstreaming@lists.sr.ht \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).