From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id EEADFC001DF for ; Sun, 22 Oct 2023 10:49:12 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229472AbjJVKtN (ORCPT ); Sun, 22 Oct 2023 06:49:13 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39412 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231297AbjJVKtL (ORCPT ); Sun, 22 Oct 2023 06:49:11 -0400 Received: from mgamail.intel.com (mgamail.intel.com [134.134.136.20]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 30CC2BE for ; Sun, 22 Oct 2023 03:49:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1697971750; x=1729507750; h=date:from:to:cc:subject:message-id:references: mime-version:in-reply-to; bh=BAzFzoEFjtpbdJFYOHSqY0/W0jpaLu4m/w/mAzU3BHs=; b=I+7Lj3OOXb6tYniGd+4n0BcbcfxBNBUjHH6UexiZElh/f31Nm+Q4Y0Z/ ZxtuXJoVABXu6dM61gi4LNjkRnjRLOgF0dPZ/LVF71GLe6AWy0OtaJ9RD Ig+y0QyFWF0GXl3GM4fGvCKtHHzQpjQ7QysFb8++8+ExxLWaMjwpOlfnf Nq101c1z8aB0YMdd4dq6yDwG1BqWuO5dz9Ha6a7IlBMuC28Ed5LMnl+/o P6yhBWQqthAZ+YbMWOphj3oSQJK/oeMhMoPpHraLIwKu0NMJYkmHURLLE m6uhETBMqHzp5ENswyeHIbqIvflnnxhM+NNwHzeEUTTEO3VCJzY5AoY1O A==; X-IronPort-AV: E=McAfee;i="6600,9927,10870"; a="377070367" X-IronPort-AV: E=Sophos;i="6.03,242,1694761200"; d="scan'208";a="377070367" Received: from orviesa001.jf.intel.com ([10.64.159.141]) by orsmga101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Oct 2023 03:49:09 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.03,242,1694761200"; d="scan'208";a="5524281" Received: from joe-255.igk.intel.com (HELO localhost) ([10.91.220.57]) by smtpauth.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Oct 2023 03:47:54 -0700 Date: Sun, 22 Oct 2023 12:49:05 +0200 From: Stanislaw Gruszka To: Jeffrey Hugo Cc: quic_ajitpals@quicinc.com, quic_carlv@quicinc.com, quic_pkanojiy@quicinc.com, ogabbay@kernel.org, linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org Subject: Re: [PATCH v2] accel/qaic: Enable 1 MSI fallback mode Message-ID: <20231022104905.GA704032@linux.intel.com> References: <20231016170036.5409-1-quic_jhugo@quicinc.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20231016170036.5409-1-quic_jhugo@quicinc.com> Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org On Mon, Oct 16, 2023 at 11:00:36AM -0600, Jeffrey Hugo wrote: > From: Carl Vanderlip > > Several virtualization use-cases either don't support 32 MultiMSIs > (Xen/VMware) or have significant drawbacks to their use (KVM's vIOMMU, > which is required to support 32 MSI, needs to allocate an alternate > system memory space for each device using vIOMMU (e.g. 8GB VM mem and > 2 cards => 8 + 2 * 8 = 24GB host memory required)). Support these > cases by enabling a 1 MSI fallback mode. > > Whenever all 32 MSIs requested are not available, a second request for > a single MSI is made. Its success is the initiator of single MSI mode. > This mode causes all interrupts generated by the device to be directed > to the 0th MSI (firmware >=v1.10 will do this as a response to the PCIe > MSI capability configuration). Likewise, all interrupt handlers for the > device are registered to the 0th MSI. > > Since the DBC interrupt handler checks if the DBC is in use or if > there is any pending changes, the 'spurious' interrupts are > disregarded. If there is work to be done, the standard threaded IRQ > handler is dispatched. > > On every interrupt, the MHI handler wakes up its threaded interrupt > handler, and attempts to wake any waiters for MHI state events. > > Performance is within +-0.6% for test cases that typify real world > use. Larger differences ([-4,+132]%, avg +47%) exist for very simple > tasks (e.g. addition) compiled for single NSPs. It is assumed that the > small work and many interrupts typically cause contention (e.g. 16 NSPs > vs 4 CPUs), as evidenced by the standard deviation between runs also > decreasing (r=-0.48 between delta(Performace_test) and > delta(StdDev_test/Avg_test)) > > Signed-off-by: Carl Vanderlip > Reviewed-by: Pranjal Ramajor Asha Kanojiya > Reviewed-by: Jeffrey Hugo > Signed-off-by: Jeffrey Hugo Reviewed-by: Stanislaw Gruszka