From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7FFD410A2B; Tue, 28 Nov 2023 06:03:15 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="fjNI1v+1" Received: by smtp.kernel.org (Postfix) with ESMTPSA id A2A30C433C8; Tue, 28 Nov 2023 06:03:08 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1701151395; bh=6/I3P+1MAnM92zerCNmuL/B5JxuHenKJfYrnnhGo+BU=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=fjNI1v+14a4SfKBRn0I/ojEVo9TBuXbC/h03uJc2BiB7ojy3o/nB0UHjKfeQwtzCJ QAGkF0JKCNvOr5yB8I/zMsGShWuctJwLnOwTlIBhlK/XFIQRNarQD6v10vCqPmMIYt wqDpnBzZNL6DEkFAvJ5st9uxbIJEpjOiTug5QycI6UVFCjAaRR7+bLmG4aww6xVJUQ Lou/1rWB/srjKHLU2c8KMQloy6ear0QcQ+krm4aNJGJ/rlxATFp+lSQ+RvStddQymZ TAHmqiYSXHFjZJV4TR39qsPVQM4sOAmdelBJkDPNHcywVCvGQu/bY7elTPq8tzxg3W e2R7Au/JgGQtQ== Date: Tue, 28 Nov 2023 11:32:57 +0530 From: Manivannan Sadhasivam To: Can Guo Cc: bvanassche@acm.org, adrian.hunter@intel.com, beanhuo@micron.com, avri.altman@wdc.com, junwoo80.lee@samsung.com, martin.petersen@oracle.com, linux-scsi@vger.kernel.org, linux-arm-msm@vger.kernel.org, Andy Gross , Bjorn Andersson , Konrad Dybcio , Vinod Koul , Kishon Vijay Abraham I , Dmitry Baryshkov , Johan Hovold , Abel Vesa , "open list:GENERIC PHY FRAMEWORK" , open list Subject: Re: [PATCH v5 08/10] phy: qualcomm: phy-qcom-qmp-ufs: Rectify SM8550 UFS HS-G4 PHY Settings Message-ID: <20231128060257.GI3088@thinkpad> References: <1700729190-17268-1-git-send-email-quic_cang@quicinc.com> <1700729190-17268-9-git-send-email-quic_cang@quicinc.com> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <1700729190-17268-9-git-send-email-quic_cang@quicinc.com> On Thu, Nov 23, 2023 at 12:46:28AM -0800, Can Guo wrote: > The registers, which are being touched in current SM8550 UFS PHY settings, > and the values being programmed are mainly the ones working for HS-G4 mode, > meanwhile, there are also a few ones somehow taken from HS-G5 PHY settings. > However, even consider HS-G4 mode only, some of them are incorrect and some > are missing. Rectify the HS-G4 PHY settings by strictly aligning with the > SM8550 UFS PHY Hardware Programming Guide suggested HS-G4 PHY settings. > > Fixes: 1679bfef906f ("phy: qcom-qmp-ufs: Add SM8550 support") > Reviewed-by: Dmitry Baryshkov > Reviewed-by: Abel Vesa > Signed-off-by: Can Guo Reviewed-by: Manivannan Sadhasivam - Mani > --- > .../qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v6.h | 3 +++ > drivers/phy/qualcomm/phy-qcom-qmp-ufs.c | 28 +++++++++++++++------- > 2 files changed, 22 insertions(+), 9 deletions(-) > > diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v6.h b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v6.h > index 15bcb4b..674f158 100644 > --- a/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v6.h > +++ b/drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-ufs-v6.h > @@ -10,9 +10,12 @@ > #define QSERDES_UFS_V6_TX_RES_CODE_LANE_RX 0x2c > #define QSERDES_UFS_V6_TX_RES_CODE_LANE_OFFSET_TX 0x30 > #define QSERDES_UFS_V6_TX_RES_CODE_LANE_OFFSET_RX 0x34 > +#define QSERDES_UFS_V6_TX_LANE_MODE_1 0x7c > +#define QSERDES_UFS_V6_TX_FR_DCC_CTRL 0x108 > > #define QSERDES_UFS_V6_RX_UCDR_FASTLOCK_FO_GAIN_RATE2 0x08 > #define QSERDES_UFS_V6_RX_UCDR_FASTLOCK_FO_GAIN_RATE4 0x10 > +#define QSERDES_UFS_V6_RX_UCDR_FO_GAIN_RATE2 0xd4 > #define QSERDES_UFS_V6_RX_VGA_CAL_MAN_VAL 0x178 > #define QSERDES_UFS_V6_RX_MODE_RATE_0_1_B0 0x208 > #define QSERDES_UFS_V6_RX_MODE_RATE_0_1_B1 0x20c > diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c > index 3927eba..ad91f92 100644 > --- a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c > +++ b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c > @@ -658,22 +658,26 @@ static const struct qmp_phy_init_tbl sm8550_ufsphy_serdes[] = { > QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE0, 0x14), > QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x7f), > QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x06), > - QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x4c), > - QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x0a), > - QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE0, 0x18), > - QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE0, 0x14), > - QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x99), > - QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x07), > + QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE1, 0x4c), > + QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE1, 0x0a), > + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE1, 0x18), > + QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE1, 0x14), > + QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE1, 0x99), > + QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE1, 0x07), > +}; > + > +static const struct qmp_phy_init_tbl sm8550_ufsphy_hs_b_serdes[] = { > + QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x44), > }; > > static const struct qmp_phy_init_tbl sm8550_ufsphy_tx[] = { > - QMP_PHY_INIT_CFG(QSERDES_V6_TX_LANE_MODE_1, 0x05), > + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_TX_LANE_MODE_1, 0x05), > QMP_PHY_INIT_CFG(QSERDES_UFS_V6_TX_RES_CODE_LANE_OFFSET_TX, 0x07), > + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_TX_FR_DCC_CTRL, 0x4c), > }; > > static const struct qmp_phy_init_tbl sm8550_ufsphy_rx[] = { > - QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_FASTLOCK_FO_GAIN_RATE2, 0x0c), > - QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_FASTLOCK_FO_GAIN_RATE4, 0x0f), > + QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_UCDR_FO_GAIN_RATE2, 0x0c), > QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_VGA_CAL_MAN_VAL, 0x0e), > > QMP_PHY_INIT_CFG(QSERDES_UFS_V6_RX_MODE_RATE_0_1_B0, 0xc2), > @@ -696,6 +700,8 @@ static const struct qmp_phy_init_tbl sm8550_ufsphy_pcs[] = { > QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_TX_MID_TERM_CTRL1, 0x43), > QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_PLL_CNTL, 0x2b), > QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_MULTI_LANE_CTRL1, 0x02), > + QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_TX_HSGEAR_CAPABILITY, 0x04), > + QMP_PHY_INIT_CFG(QPHY_V6_PCS_UFS_RX_HSGEAR_CAPABILITY, 0x04), > }; > > struct qmp_ufs_offsets { > @@ -1157,6 +1163,10 @@ static const struct qmp_phy_cfg sm8550_ufsphy_cfg = { > .pcs = sm8550_ufsphy_pcs, > .pcs_num = ARRAY_SIZE(sm8550_ufsphy_pcs), > }, > + .tbls_hs_b = { > + .serdes = sm8550_ufsphy_hs_b_serdes, > + .serdes_num = ARRAY_SIZE(sm8550_ufsphy_hs_b_serdes), > + }, > .clk_list = sdm845_ufs_phy_clk_l, > .num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l), > .vreg_list = qmp_phy_vreg_l, > -- > 2.7.4 > -- மணிவண்ணன் சதாசிவம்