From: Jessica Zhang <quic_jesszhan@quicinc.com>
To: Rob Clark <robdclark@gmail.com>,
Dmitry Baryshkov <dmitry.baryshkov@linaro.org>,
Sean Paul <sean@poorly.run>,
Marijn Suijten <marijn.suijten@somainline.org>,
David Airlie <airlied@gmail.com>,
"Daniel Vetter" <daniel@ffwll.ch>
Cc: <quic_abhinavk@quicinc.com>, <linux-arm-msm@vger.kernel.org>,
<dri-devel@lists.freedesktop.org>,
<freedreno@lists.freedesktop.org>, <linux-kernel@vger.kernel.org>,
Jessica Zhang <quic_jesszhan@quicinc.com>
Subject: [PATCH v3 0/2] drm/msm/dpu: INTF CRC configuration cleanups and fix
Date: Wed, 13 Dec 2023 13:22:18 -0800 [thread overview]
Message-ID: <20231213-encoder-fixup-v3-0-b5cd2cda6bf5@quicinc.com> (raw)
This series drops the frame_count and enable parameters (as they're always
set to the same value). It also sets input_sel=0x1 for INTF.
---
Changes in v3:
- Changed input_sel to u8
- Link to v2: https://lore.kernel.org/r/20231213-encoder-fixup-v2-0-b11a4ad35e5e@quicinc.com
Changes in v2:
- Switched patch order
- Changed input_sel parameter from bool to u8
- Link to v1: https://lore.kernel.org/r/20231130-encoder-fixup-v1-0-585c54cd046e@quicinc.com
---
Jessica Zhang (2):
drm/msm/dpu: Set input_sel bit for INTF
drm/msm/dpu: Drop enable and frame_count parameters from dpu_hw_setup_misr()
drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 4 ++--
drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 4 ++--
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c | 6 +++---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h | 4 ++--
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c | 6 +++---
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.h | 3 ++-
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c | 20 ++++++++------------
drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h | 8 +++-----
8 files changed, 25 insertions(+), 30 deletions(-)
---
base-commit: 0d9372c346d4cdf347354382e0659de8c1cc0236
change-id: 20231122-encoder-fixup-61c190b16085
Best regards,
--
Jessica Zhang <quic_jesszhan@quicinc.com>
next reply other threads:[~2023-12-13 21:22 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-12-13 21:22 Jessica Zhang [this message]
2023-12-13 21:22 ` [PATCH v3 1/2] drm/msm/dpu: Set input_sel bit for INTF Jessica Zhang
2023-12-13 21:22 ` [PATCH v3 2/2] drm/msm/dpu: Drop enable and frame_count parameters from dpu_hw_setup_misr() Jessica Zhang
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