* [PATCH v6 01/11] arm64: dts: qcom: x1e80100: Add IPCC node
2024-01-29 12:45 [PATCH v6 00/11] arm64: dts: qcom: Add more support to X1E80100 base dtsi, CRD and QCP boards Abel Vesa
@ 2024-01-29 12:45 ` Abel Vesa
2024-01-29 12:45 ` [PATCH v6 02/11] arm64: dts: qcom: x1e80100: Add SMP2P nodes Abel Vesa
` (10 subsequent siblings)
11 siblings, 0 replies; 14+ messages in thread
From: Abel Vesa @ 2024-01-29 12:45 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Konrad Dybcio, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Sibi Sankar, Rajendra Nayak
Cc: linux-arm-msm, devicetree, linux-kernel, Abel Vesa
From: Sibi Sankar <quic_sibis@quicinc.com>
Add the IPCC node, used to send and receive IPC signals with
remoteprocs.
Signed-off-by: Sibi Sankar <quic_sibis@quicinc.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
---
arch/arm64/boot/dts/qcom/x1e80100.dtsi | 11 +++++++++++
1 file changed, 11 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/x1e80100.dtsi b/arch/arm64/boot/dts/qcom/x1e80100.dtsi
index 6f75fc342ceb..954f2bd9b1de 100644
--- a/arch/arm64/boot/dts/qcom/x1e80100.dtsi
+++ b/arch/arm64/boot/dts/qcom/x1e80100.dtsi
@@ -691,6 +691,17 @@ gcc: clock-controller@100000 {
#power-domain-cells = <1>;
};
+ ipcc: mailbox@408000 {
+ compatible = "qcom,x1e80100-ipcc", "qcom,ipcc";
+ reg = <0 0x00408000 0 0x1000>;
+
+ interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-controller;
+ #interrupt-cells = <3>;
+
+ #mbox-cells = <2>;
+ };
+
gpi_dma2: dma-controller@800000 {
compatible = "qcom,x1e80100-gpi-dma", "qcom,sm6350-gpi-dma";
reg = <0 0x00800000 0 0x60000>;
--
2.34.1
^ permalink raw reply related [flat|nested] 14+ messages in thread* [PATCH v6 02/11] arm64: dts: qcom: x1e80100: Add SMP2P nodes
2024-01-29 12:45 [PATCH v6 00/11] arm64: dts: qcom: Add more support to X1E80100 base dtsi, CRD and QCP boards Abel Vesa
2024-01-29 12:45 ` [PATCH v6 01/11] arm64: dts: qcom: x1e80100: Add IPCC node Abel Vesa
@ 2024-01-29 12:45 ` Abel Vesa
2024-01-29 12:45 ` [PATCH v6 03/11] arm64: dts: qcom: x1e80100: Add QMP AOSS node Abel Vesa
` (9 subsequent siblings)
11 siblings, 0 replies; 14+ messages in thread
From: Abel Vesa @ 2024-01-29 12:45 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Konrad Dybcio, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Sibi Sankar, Rajendra Nayak
Cc: linux-arm-msm, devicetree, linux-kernel, Abel Vesa
From: Sibi Sankar <quic_sibis@quicinc.com>
SMP2P is used for interrupting and being interrupted about remoteproc
state changes related to the audio, compute and sensor subsystems.
Signed-off-by: Sibi Sankar <quic_sibis@quicinc.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
---
arch/arm64/boot/dts/qcom/x1e80100.dtsi | 53 ++++++++++++++++++++++++++++++++++
1 file changed, 53 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/x1e80100.dtsi b/arch/arm64/boot/dts/qcom/x1e80100.dtsi
index 954f2bd9b1de..1210351b6538 100644
--- a/arch/arm64/boot/dts/qcom/x1e80100.dtsi
+++ b/arch/arm64/boot/dts/qcom/x1e80100.dtsi
@@ -9,6 +9,7 @@
#include <dt-bindings/interconnect/qcom,icc.h>
#include <dt-bindings/interconnect/qcom,x1e80100-rpmh.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/mailbox/qcom-ipcc.h>
#include <dt-bindings/power/qcom,rpmhpd.h>
#include <dt-bindings/power/qcom-rpmpd.h>
#include <dt-bindings/soc/qcom,rpmh-rsc.h>
@@ -662,6 +663,58 @@ smem_mem: smem@ffe00000 {
};
};
+ smp2p-adsp {
+ compatible = "qcom,smp2p";
+
+ interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
+ IPCC_MPROC_SIGNAL_SMP2P
+ IRQ_TYPE_EDGE_RISING>;
+
+ mboxes = <&ipcc IPCC_CLIENT_LPASS
+ IPCC_MPROC_SIGNAL_SMP2P>;
+
+ qcom,smem = <443>, <429>;
+ qcom,local-pid = <0>;
+ qcom,remote-pid = <2>;
+
+ smp2p_adsp_out: master-kernel {
+ qcom,entry-name = "master-kernel";
+ #qcom,smem-state-cells = <1>;
+ };
+
+ smp2p_adsp_in: slave-kernel {
+ qcom,entry-name = "slave-kernel";
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+ };
+
+ smp2p-cdsp {
+ compatible = "qcom,smp2p";
+
+ interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
+ IPCC_MPROC_SIGNAL_SMP2P
+ IRQ_TYPE_EDGE_RISING>;
+
+ mboxes = <&ipcc IPCC_CLIENT_CDSP
+ IPCC_MPROC_SIGNAL_SMP2P>;
+
+ qcom,smem = <94>, <432>;
+ qcom,local-pid = <0>;
+ qcom,remote-pid = <5>;
+
+ smp2p_cdsp_out: master-kernel {
+ qcom,entry-name = "master-kernel";
+ #qcom,smem-state-cells = <1>;
+ };
+
+ smp2p_cdsp_in: slave-kernel {
+ qcom,entry-name = "slave-kernel";
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+ };
+
soc: soc@0 {
compatible = "simple-bus";
--
2.34.1
^ permalink raw reply related [flat|nested] 14+ messages in thread* [PATCH v6 03/11] arm64: dts: qcom: x1e80100: Add QMP AOSS node
2024-01-29 12:45 [PATCH v6 00/11] arm64: dts: qcom: Add more support to X1E80100 base dtsi, CRD and QCP boards Abel Vesa
2024-01-29 12:45 ` [PATCH v6 01/11] arm64: dts: qcom: x1e80100: Add IPCC node Abel Vesa
2024-01-29 12:45 ` [PATCH v6 02/11] arm64: dts: qcom: x1e80100: Add SMP2P nodes Abel Vesa
@ 2024-01-29 12:45 ` Abel Vesa
2024-01-29 12:45 ` [PATCH v6 04/11] arm64: dts: qcom: x1e80100: Add ADSP/CDSP remoteproc nodes Abel Vesa
` (8 subsequent siblings)
11 siblings, 0 replies; 14+ messages in thread
From: Abel Vesa @ 2024-01-29 12:45 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Konrad Dybcio, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Sibi Sankar, Rajendra Nayak
Cc: linux-arm-msm, devicetree, linux-kernel, Abel Vesa
From: Sibi Sankar <quic_sibis@quicinc.com>
Add a node for the QMP AOSS.
Signed-off-by: Sibi Sankar <quic_sibis@quicinc.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
---
arch/arm64/boot/dts/qcom/x1e80100.dtsi | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/x1e80100.dtsi b/arch/arm64/boot/dts/qcom/x1e80100.dtsi
index 1210351b6538..3790d99eb298 100644
--- a/arch/arm64/boot/dts/qcom/x1e80100.dtsi
+++ b/arch/arm64/boot/dts/qcom/x1e80100.dtsi
@@ -2663,6 +2663,18 @@ pdc: interrupt-controller@b220000 {
interrupt-controller;
};
+ aoss_qmp: power-management@c300000 {
+ compatible = "qcom,x1e80100-aoss-qmp", "qcom,aoss-qmp";
+ reg = <0 0x0c300000 0 0x400>;
+ interrupt-parent = <&ipcc>;
+ interrupts-extended = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP
+ IRQ_TYPE_EDGE_RISING>;
+ mboxes = <&ipcc IPCC_CLIENT_AOP IPCC_MPROC_SIGNAL_GLINK_QMP>;
+
+ #clock-cells = <0>;
+ };
+
+
tlmm: pinctrl@f100000 {
compatible = "qcom,x1e80100-tlmm";
reg = <0 0x0f100000 0 0xf00000>;
--
2.34.1
^ permalink raw reply related [flat|nested] 14+ messages in thread* [PATCH v6 04/11] arm64: dts: qcom: x1e80100: Add ADSP/CDSP remoteproc nodes
2024-01-29 12:45 [PATCH v6 00/11] arm64: dts: qcom: Add more support to X1E80100 base dtsi, CRD and QCP boards Abel Vesa
` (2 preceding siblings ...)
2024-01-29 12:45 ` [PATCH v6 03/11] arm64: dts: qcom: x1e80100: Add QMP AOSS node Abel Vesa
@ 2024-01-29 12:45 ` Abel Vesa
2024-01-29 12:45 ` [PATCH v6 05/11] arm64: dts: qcom: x1e80100: Add TCSR node Abel Vesa
` (7 subsequent siblings)
11 siblings, 0 replies; 14+ messages in thread
From: Abel Vesa @ 2024-01-29 12:45 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Konrad Dybcio, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Sibi Sankar, Rajendra Nayak
Cc: linux-arm-msm, devicetree, linux-kernel, Abel Vesa
From: Sibi Sankar <quic_sibis@quicinc.com>
Add ADSP and CDSP remoteproc nodes on X1E80100 platforms.
Signed-off-by: Sibi Sankar <quic_sibis@quicinc.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
---
arch/arm64/boot/dts/qcom/x1e80100.dtsi | 98 ++++++++++++++++++++++++++++++++++
1 file changed, 98 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/x1e80100.dtsi b/arch/arm64/boot/dts/qcom/x1e80100.dtsi
index 3790d99eb298..be69e71b7f53 100644
--- a/arch/arm64/boot/dts/qcom/x1e80100.dtsi
+++ b/arch/arm64/boot/dts/qcom/x1e80100.dtsi
@@ -3590,6 +3590,104 @@ system-cache-controller@25000000 {
"llcc_broadcast_base";
interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>;
};
+
+ remoteproc_adsp: remoteproc@30000000 {
+ compatible = "qcom,x1e80100-adsp-pas";
+ reg = <0 0x30000000 0 0x100>;
+
+ interrupts-extended = <&pdc 6 IRQ_TYPE_EDGE_RISING>,
+ <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>,
+ <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>,
+ <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>,
+ <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "wdog",
+ "fatal",
+ "ready",
+ "handover",
+ "stop-ack";
+
+ clocks = <&rpmhcc RPMH_CXO_CLK>;
+ clock-names = "xo";
+
+ power-domains = <&rpmhpd RPMHPD_LCX>,
+ <&rpmhpd RPMHPD_LMX>;
+ power-domain-names = "lcx",
+ "lmx";
+
+ interconnects = <&lpass_lpicx_noc MASTER_LPASS_PROC QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+
+ memory-region = <&adspslpi_mem>,
+ <&q6_adsp_dtb_mem>;
+
+ qcom,qmp = <&aoss_qmp>;
+
+ qcom,smem-states = <&smp2p_adsp_out 0>;
+ qcom,smem-state-names = "stop";
+
+ status = "disabled";
+
+ glink-edge {
+ interrupts-extended = <&ipcc IPCC_CLIENT_LPASS
+ IPCC_MPROC_SIGNAL_GLINK_QMP
+ IRQ_TYPE_EDGE_RISING>;
+ mboxes = <&ipcc IPCC_CLIENT_LPASS
+ IPCC_MPROC_SIGNAL_GLINK_QMP>;
+
+ label = "lpass";
+ qcom,remote-pid = <2>;
+ };
+ };
+
+ remoteproc_cdsp: remoteproc@32300000 {
+ compatible = "qcom,x1e80100-cdsp-pas";
+ reg = <0 0x32300000 0 0x1400000>;
+
+ interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>,
+ <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>,
+ <&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>,
+ <&smp2p_cdsp_in 2 IRQ_TYPE_EDGE_RISING>,
+ <&smp2p_cdsp_in 3 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "wdog",
+ "fatal",
+ "ready",
+ "handover",
+ "stop-ack";
+
+ clocks = <&rpmhcc RPMH_CXO_CLK>;
+ clock-names = "xo";
+
+ power-domains = <&rpmhpd RPMHPD_CX>,
+ <&rpmhpd RPMHPD_MXC>,
+ <&rpmhpd RPMHPD_NSP>;
+ power-domain-names = "cx",
+ "mxc",
+ "nsp";
+
+ interconnects = <&nsp_noc MASTER_CDSP_PROC QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
+
+ memory-region = <&cdsp_mem>,
+ <&q6_cdsp_dtb_mem>;
+
+ qcom,qmp = <&aoss_qmp>;
+
+ qcom,smem-states = <&smp2p_cdsp_out 0>;
+ qcom,smem-state-names = "stop";
+
+ status = "disabled";
+
+ glink-edge {
+ interrupts-extended = <&ipcc IPCC_CLIENT_CDSP
+ IPCC_MPROC_SIGNAL_GLINK_QMP
+ IRQ_TYPE_EDGE_RISING>;
+ mboxes = <&ipcc IPCC_CLIENT_CDSP
+ IPCC_MPROC_SIGNAL_GLINK_QMP>;
+
+ label = "cdsp";
+ qcom,remote-pid = <5>;
+ };
+ };
};
timer {
--
2.34.1
^ permalink raw reply related [flat|nested] 14+ messages in thread* [PATCH v6 05/11] arm64: dts: qcom: x1e80100: Add TCSR node
2024-01-29 12:45 [PATCH v6 00/11] arm64: dts: qcom: Add more support to X1E80100 base dtsi, CRD and QCP boards Abel Vesa
` (3 preceding siblings ...)
2024-01-29 12:45 ` [PATCH v6 04/11] arm64: dts: qcom: x1e80100: Add ADSP/CDSP remoteproc nodes Abel Vesa
@ 2024-01-29 12:45 ` Abel Vesa
2024-02-01 19:19 ` Konrad Dybcio
2024-01-29 12:45 ` [PATCH v6 06/11] arm64: dts: qcom: x1e80100: Add USB nodes Abel Vesa
` (6 subsequent siblings)
11 siblings, 1 reply; 14+ messages in thread
From: Abel Vesa @ 2024-01-29 12:45 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Konrad Dybcio, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Sibi Sankar, Rajendra Nayak
Cc: linux-arm-msm, devicetree, linux-kernel, Abel Vesa
Add the TCSR clock controller and register space node.
Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
---
arch/arm64/boot/dts/qcom/x1e80100.dtsi | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/x1e80100.dtsi b/arch/arm64/boot/dts/qcom/x1e80100.dtsi
index be69e71b7f53..2b6c55a486b2 100644
--- a/arch/arm64/boot/dts/qcom/x1e80100.dtsi
+++ b/arch/arm64/boot/dts/qcom/x1e80100.dtsi
@@ -2606,6 +2606,14 @@ tcsr_mutex: hwlock@1f40000 {
#hwlock-cells = <1>;
};
+ tcsr: clock-controller@1fc0000 {
+ compatible = "qcom,x1e80100-tcsr", "syscon";
+ reg = <0 0x01fc0000 0 0x30000>;
+ clocks = <&rpmhcc RPMH_CXO_CLK>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
+
gem_noc: interconnect@26400000 {
compatible = "qcom,x1e80100-gem-noc";
reg = <0 0x26400000 0 0x311200>;
--
2.34.1
^ permalink raw reply related [flat|nested] 14+ messages in thread* Re: [PATCH v6 05/11] arm64: dts: qcom: x1e80100: Add TCSR node
2024-01-29 12:45 ` [PATCH v6 05/11] arm64: dts: qcom: x1e80100: Add TCSR node Abel Vesa
@ 2024-02-01 19:19 ` Konrad Dybcio
0 siblings, 0 replies; 14+ messages in thread
From: Konrad Dybcio @ 2024-02-01 19:19 UTC (permalink / raw)
To: Abel Vesa, Andy Gross, Bjorn Andersson, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Sibi Sankar, Rajendra Nayak
Cc: linux-arm-msm, devicetree, linux-kernel
On 29.01.2024 13:45, Abel Vesa wrote:
> Add the TCSR clock controller and register space node.
>
> Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
> ---
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Konrad
^ permalink raw reply [flat|nested] 14+ messages in thread
* [PATCH v6 06/11] arm64: dts: qcom: x1e80100: Add USB nodes
2024-01-29 12:45 [PATCH v6 00/11] arm64: dts: qcom: Add more support to X1E80100 base dtsi, CRD and QCP boards Abel Vesa
` (4 preceding siblings ...)
2024-01-29 12:45 ` [PATCH v6 05/11] arm64: dts: qcom: x1e80100: Add TCSR node Abel Vesa
@ 2024-01-29 12:45 ` Abel Vesa
2024-01-29 12:45 ` [PATCH v6 07/11] arm64: dts: qcom: x1e80100: Add PCIe nodes Abel Vesa
` (5 subsequent siblings)
11 siblings, 0 replies; 14+ messages in thread
From: Abel Vesa @ 2024-01-29 12:45 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Konrad Dybcio, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Sibi Sankar, Rajendra Nayak
Cc: linux-arm-msm, devicetree, linux-kernel, Abel Vesa
Add nodes for all USB controllers and their PHYs for X1E80100 platform.
Co-developed-by: Sibi Sankar <quic_sibis@quicinc.com>
Signed-off-by: Sibi Sankar <quic_sibis@quicinc.com>
Co-developed-by: Rajendra Nayak <quic_rjendra@quicinc.com>
Signed-off-by: Rajendra Nayak <quic_rjendra@quicinc.com>
Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
---
arch/arm64/boot/dts/qcom/x1e80100.dtsi | 453 ++++++++++++++++++++++++++++++++-
1 file changed, 450 insertions(+), 3 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/x1e80100.dtsi b/arch/arm64/boot/dts/qcom/x1e80100.dtsi
index 2b6c55a486b2..ee61e1cbc5af 100644
--- a/arch/arm64/boot/dts/qcom/x1e80100.dtsi
+++ b/arch/arm64/boot/dts/qcom/x1e80100.dtsi
@@ -5,11 +5,13 @@
#include <dt-bindings/clock/qcom,rpmh.h>
#include <dt-bindings/clock/qcom,x1e80100-gcc.h>
+#include <dt-bindings/clock/qcom,x1e80100-tcsr.h>
#include <dt-bindings/dma/qcom-gpi.h>
#include <dt-bindings/interconnect/qcom,icc.h>
#include <dt-bindings/interconnect/qcom,x1e80100-rpmh.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/mailbox/qcom-ipcc.h>
+#include <dt-bindings/phy/phy-qcom-qmp.h>
#include <dt-bindings/power/qcom,rpmhpd.h>
#include <dt-bindings/power/qcom-rpmpd.h>
#include <dt-bindings/soc/qcom,rpmh-rsc.h>
@@ -734,9 +736,9 @@ gcc: clock-controller@100000 {
<0>,
<0>,
<0>,
- <0>,
- <0>,
- <0>;
+ <&usb_1_ss0_qmpphy QMP_USB43DP_USB3_PIPE_CLK>,
+ <&usb_1_ss1_qmpphy QMP_USB43DP_USB3_PIPE_CLK>,
+ <&usb_1_ss2_qmpphy QMP_USB43DP_USB3_PIPE_CLK>;
power-domains = <&rpmhpd RPMHPD_CX>;
#clock-cells = <1>;
@@ -2492,6 +2494,126 @@ &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>,
};
};
+ usb_1_ss0_hsphy: phy@fd3000 {
+ compatible = "qcom,x1e80100-snps-eusb2-phy",
+ "qcom,sm8550-snps-eusb2-phy";
+ reg = <0 0x00fd3000 0 0x154>;
+ #phy-cells = <0>;
+
+ clocks = <&tcsr TCSR_USB2_1_CLKREF_EN>;
+ clock-names = "ref";
+
+ resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
+
+ status = "disabled";
+ };
+
+ usb_1_ss0_qmpphy: phy@fd5000 {
+ compatible = "qcom,x1e80100-qmp-usb3-dp-phy";
+ reg = <0 0x00fd5000 0 0x4000>;
+
+ clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
+ <&rpmhcc RPMH_CXO_CLK>,
+ <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>,
+ <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
+ clock-names = "aux",
+ "ref",
+ "com_aux",
+ "usb3_pipe";
+
+ power-domains = <&gcc GCC_USB_0_PHY_GDSC>;
+
+ resets = <&gcc GCC_USB3_PHY_PRIM_BCR>,
+ <&gcc GCC_USB4_0_DP0_PHY_PRIM_BCR>;
+ reset-names = "phy",
+ "common";
+
+ #clock-cells = <1>;
+ #phy-cells = <1>;
+
+ status = "disabled";
+ };
+
+ usb_1_ss1_hsphy: phy@fd9000 {
+ compatible = "qcom,x1e80100-snps-eusb2-phy",
+ "qcom,sm8550-snps-eusb2-phy";
+ reg = <0 0x00fd9000 0 0x154>;
+ #phy-cells = <0>;
+
+ clocks = <&tcsr TCSR_USB2_1_CLKREF_EN>;
+ clock-names = "ref";
+
+ resets = <&gcc GCC_QUSB2PHY_SEC_BCR>;
+
+ status = "disabled";
+ };
+
+ usb_1_ss1_qmpphy: phy@fda000 {
+ compatible = "qcom,x1e80100-qmp-usb3-dp-phy";
+ reg = <0 0x00fda000 0 0x4000>;
+
+ clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>,
+ <&rpmhcc RPMH_CXO_CLK>,
+ <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>,
+ <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>;
+ clock-names = "aux",
+ "ref",
+ "com_aux",
+ "usb3_pipe";
+
+ power-domains = <&gcc GCC_USB_1_PHY_GDSC>;
+
+ resets = <&gcc GCC_USB3_PHY_SEC_BCR>,
+ <&gcc GCC_USB4_1_DP0_PHY_SEC_BCR>;
+ reset-names = "phy",
+ "common";
+
+ #clock-cells = <1>;
+ #phy-cells = <1>;
+
+ status = "disabled";
+ };
+
+ usb_1_ss2_hsphy: phy@fde000 {
+ compatible = "qcom,x1e80100-snps-eusb2-phy",
+ "qcom,sm8550-snps-eusb2-phy";
+ reg = <0 0x00fde000 0 0x154>;
+ #phy-cells = <0>;
+
+ clocks = <&tcsr TCSR_USB2_1_CLKREF_EN>;
+ clock-names = "ref";
+
+ resets = <&gcc GCC_QUSB2PHY_TERT_BCR>;
+
+ status = "disabled";
+ };
+
+ usb_1_ss2_qmpphy: phy@fdf000 {
+ compatible = "qcom,x1e80100-qmp-usb3-dp-phy";
+ reg = <0 0x00fdf000 0 0x4000>;
+
+ clocks = <&gcc GCC_USB3_TERT_PHY_AUX_CLK>,
+ <&rpmhcc RPMH_CXO_CLK>,
+ <&gcc GCC_USB3_TERT_PHY_COM_AUX_CLK>,
+ <&gcc GCC_USB3_TERT_PHY_PIPE_CLK>;
+ clock-names = "aux",
+ "ref",
+ "com_aux",
+ "usb3_pipe";
+
+ power-domains = <&gcc GCC_USB_2_PHY_GDSC>;
+
+ resets = <&gcc GCC_USB3_PHY_TERT_BCR>,
+ <&gcc GCC_USB4_2_DP0_PHY_TERT_BCR>;
+ reset-names = "phy",
+ "common";
+
+ #clock-cells = <1>;
+ #phy-cells = <1>;
+
+ status = "disabled";
+ };
+
cnoc_main: interconnect@1500000 {
compatible = "qcom,x1e80100-cnoc-main";
reg = <0 0x1500000 0 0x14400>;
@@ -2659,6 +2781,331 @@ lpass_lpicx_noc: interconnect@7430000 {
#interconnect-cells = <2>;
};
+ usb_2_hsphy: phy@88e0000 {
+ compatible = "qcom,x1e80100-snps-eusb2-phy",
+ "qcom,sm8550-snps-eusb2-phy";
+ reg = <0 0x088e0000 0 0x154>;
+ #phy-cells = <0>;
+
+ clocks = <&tcsr TCSR_USB2_2_CLKREF_EN>;
+ clock-names = "ref";
+
+ resets = <&gcc GCC_QUSB2PHY_USB20_HS_BCR>;
+
+ status = "disabled";
+ };
+
+ usb_1_ss2: usb@a0f8800 {
+ compatible = "qcom,x1e80100-dwc3", "qcom,dwc3";
+ reg = <0 0x0a0f8800 0 0x400>;
+
+ clocks = <&gcc GCC_CFG_NOC_USB3_TERT_AXI_CLK>,
+ <&gcc GCC_USB30_TERT_MASTER_CLK>,
+ <&gcc GCC_AGGRE_USB3_TERT_AXI_CLK>,
+ <&gcc GCC_USB30_TERT_SLEEP_CLK>,
+ <&gcc GCC_USB30_TERT_MOCK_UTMI_CLK>,
+ <&gcc GCC_AGGRE_USB_NOC_AXI_CLK>,
+ <&gcc GCC_AGGRE_NOC_USB_NORTH_AXI_CLK>,
+ <&gcc GCC_AGGRE_NOC_USB_SOUTH_AXI_CLK>,
+ <&gcc GCC_SYS_NOC_USB_AXI_CLK>;
+ clock-names = "cfg_noc",
+ "core",
+ "iface",
+ "sleep",
+ "mock_utmi",
+ "noc_aggr",
+ "noc_aggr_north",
+ "noc_aggr_south",
+ "noc_sys";
+
+ assigned-clocks = <&gcc GCC_USB30_TERT_MOCK_UTMI_CLK>,
+ <&gcc GCC_USB30_TERT_MASTER_CLK>;
+ assigned-clock-rates = <19200000>,
+ <200000000>;
+
+ interrupts-extended = <&intc GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>,
+ <&pdc 58 IRQ_TYPE_EDGE_BOTH>,
+ <&pdc 57 IRQ_TYPE_EDGE_BOTH>,
+ <&pdc 10 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "pwr_event",
+ "dp_hs_phy_irq",
+ "dm_hs_phy_irq",
+ "ss_phy_irq";
+
+ power-domains = <&gcc GCC_USB30_TERT_GDSC>;
+ required-opps = <&rpmhpd_opp_nom>;
+
+ resets = <&gcc GCC_USB30_TERT_BCR>;
+
+ interconnects = <&usb_south_anoc MASTER_USB3_2 QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+ &config_noc SLAVE_USB3_2 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "usb-ddr",
+ "apps-usb";
+
+ wakeup-source;
+
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ status = "disabled";
+
+ usb_1_ss2_dwc3: usb@a000000 {
+ compatible = "snps,dwc3";
+ reg = <0 0x0a000000 0 0xcd00>;
+
+ interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
+
+ iommus = <&apps_smmu 0x14a0 0x0>;
+
+ phys = <&usb_1_ss2_hsphy>,
+ <&usb_1_ss2_qmpphy QMP_USB43DP_USB3_PHY>;
+ phy-names = "usb2-phy",
+ "usb3-phy";
+
+ snps,dis_u2_susphy_quirk;
+ snps,dis_enblslpm_quirk;
+ snps,usb3_lpm_capable;
+
+ dma-coherent;
+
+ port {
+ usb_1_ss2_role_switch: endpoint {
+ };
+ };
+ };
+ };
+
+ usb_2: usb@a2f8800 {
+ compatible = "qcom,x1e80100-dwc3", "qcom,dwc3";
+ reg = <0 0x0a2f8800 0 0x400>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ clocks = <&gcc GCC_CFG_NOC_USB2_PRIM_AXI_CLK>,
+ <&gcc GCC_USB20_MASTER_CLK>,
+ <&gcc GCC_AGGRE_USB2_PRIM_AXI_CLK>,
+ <&gcc GCC_USB20_SLEEP_CLK>,
+ <&gcc GCC_USB20_MOCK_UTMI_CLK>,
+ <&gcc GCC_AGGRE_USB_NOC_AXI_CLK>,
+ <&gcc GCC_AGGRE_NOC_USB_NORTH_AXI_CLK>,
+ <&gcc GCC_AGGRE_NOC_USB_SOUTH_AXI_CLK>,
+ <&gcc GCC_SYS_NOC_USB_AXI_CLK>;
+ clock-names = "cfg_noc",
+ "core",
+ "iface",
+ "sleep",
+ "mock_utmi",
+ "noc_aggr",
+ "noc_aggr_north",
+ "noc_aggr_south",
+ "noc_sys";
+
+ assigned-clocks = <&gcc GCC_USB20_MOCK_UTMI_CLK>,
+ <&gcc GCC_USB20_MASTER_CLK>;
+ assigned-clock-rates = <19200000>, <200000000>;
+
+ interrupts-extended = <&intc GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>,
+ <&pdc 50 IRQ_TYPE_EDGE_BOTH>,
+ <&pdc 49 IRQ_TYPE_EDGE_BOTH>;
+ interrupt-names = "pwr_event",
+ "dp_hs_phy_irq",
+ "dm_hs_phy_irq";
+
+ power-domains = <&gcc GCC_USB20_PRIM_GDSC>;
+ required-opps = <&rpmhpd_opp_nom>;
+
+ resets = <&gcc GCC_USB20_PRIM_BCR>;
+
+ interconnects = <&usb_north_anoc MASTER_USB2 QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+ &config_noc SLAVE_USB2 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "usb-ddr",
+ "apps-usb";
+
+ wakeup-source;
+
+ status = "disabled";
+
+ usb_2_dwc3: usb@a200000 {
+ compatible = "snps,dwc3";
+ reg = <0 0x0a200000 0 0xcd00>;
+ interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>;
+ iommus = <&apps_smmu 0x14e0 0x0>;
+ phys = <&usb_2_hsphy>;
+ phy-names = "usb2-phy";
+ maximum-speed = "high-speed";
+
+ port {
+ usb_2_role_switch: endpoint {
+ };
+ };
+ };
+ };
+
+ usb_1_ss0: usb@a6f8800 {
+ compatible = "qcom,x1e80100-dwc3", "qcom,dwc3";
+ reg = <0 0x0a6f8800 0 0x400>;
+
+ clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
+ <&gcc GCC_USB30_PRIM_MASTER_CLK>,
+ <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
+ <&gcc GCC_USB30_PRIM_SLEEP_CLK>,
+ <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
+ <&gcc GCC_AGGRE_USB_NOC_AXI_CLK>,
+ <&gcc GCC_CFG_NOC_USB_ANOC_NORTH_AHB_CLK>,
+ <&gcc GCC_CFG_NOC_USB_ANOC_SOUTH_AHB_CLK>,
+ <&gcc GCC_SYS_NOC_USB_AXI_CLK>;
+ clock-names = "cfg_noc",
+ "core",
+ "iface",
+ "sleep",
+ "mock_utmi",
+ "noc_aggr",
+ "noc_aggr_north",
+ "noc_aggr_south",
+ "noc_sys";
+
+ assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
+ <&gcc GCC_USB30_PRIM_MASTER_CLK>;
+ assigned-clock-rates = <19200000>,
+ <200000000>;
+
+ interrupts-extended = <&intc GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>,
+ <&pdc 61 IRQ_TYPE_EDGE_BOTH>,
+ <&pdc 15 IRQ_TYPE_EDGE_BOTH>,
+ <&pdc 17 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "pwr_event",
+ "dp_hs_phy_irq",
+ "dm_hs_phy_irq",
+ "ss_phy_irq";
+
+ power-domains = <&gcc GCC_USB30_PRIM_GDSC>;
+ required-opps = <&rpmhpd_opp_nom>;
+
+ resets = <&gcc GCC_USB30_PRIM_BCR>;
+
+ wakeup-source;
+
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ status = "disabled";
+
+ usb_1_ss0_dwc3: usb@a600000 {
+ compatible = "snps,dwc3";
+ reg = <0 0x0a600000 0 0xcd00>;
+
+ interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
+
+ iommus = <&apps_smmu 0x1420 0x0>;
+
+ phys = <&usb_1_ss0_hsphy>,
+ <&usb_1_ss0_qmpphy QMP_USB43DP_USB3_PHY>;
+ phy-names = "usb2-phy",
+ "usb3-phy";
+
+ snps,dis_u2_susphy_quirk;
+ snps,dis_enblslpm_quirk;
+ snps,usb3_lpm_capable;
+
+ dma-coherent;
+
+ port {
+ usb_1_ss0_role_switch: endpoint {
+ };
+ };
+ };
+ };
+
+ usb_1_ss1: usb@a8f8800 {
+ compatible = "qcom,x1e80100-dwc3", "qcom,dwc3";
+ reg = <0 0x0a8f8800 0 0x400>;
+
+ clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>,
+ <&gcc GCC_USB30_SEC_MASTER_CLK>,
+ <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>,
+ <&gcc GCC_USB30_SEC_SLEEP_CLK>,
+ <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
+ <&gcc GCC_AGGRE_USB_NOC_AXI_CLK>,
+ <&gcc GCC_AGGRE_NOC_USB_NORTH_AXI_CLK>,
+ <&gcc GCC_AGGRE_NOC_USB_SOUTH_AXI_CLK>,
+ <&gcc GCC_SYS_NOC_USB_AXI_CLK>;
+ clock-names = "cfg_noc",
+ "core",
+ "iface",
+ "sleep",
+ "mock_utmi",
+ "noc_aggr",
+ "noc_aggr_north",
+ "noc_aggr_south",
+ "noc_sys";
+
+ assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>,
+ <&gcc GCC_USB30_SEC_MASTER_CLK>;
+ assigned-clock-rates = <19200000>,
+ <200000000>;
+
+ interrupts-extended = <&intc GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>,
+ <&pdc 60 IRQ_TYPE_EDGE_BOTH>,
+ <&pdc 11 IRQ_TYPE_EDGE_BOTH>,
+ <&pdc 47 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "pwr_event",
+ "dp_hs_phy_irq",
+ "dm_hs_phy_irq",
+ "ss_phy_irq";
+
+ power-domains = <&gcc GCC_USB30_SEC_GDSC>;
+ required-opps = <&rpmhpd_opp_nom>;
+
+ resets = <&gcc GCC_USB30_SEC_BCR>;
+
+ interconnects = <&usb_south_anoc MASTER_USB3_1 QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+ &config_noc SLAVE_USB3_1 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "usb-ddr",
+ "apps-usb";
+
+ wakeup-source;
+
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ status = "disabled";
+
+ usb_1_ss1_dwc3: usb@a800000 {
+ compatible = "snps,dwc3";
+ reg = <0 0x0a800000 0 0xcd00>;
+
+ interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
+
+ iommus = <&apps_smmu 0x1460 0x0>;
+
+ phys = <&usb_1_ss1_hsphy>,
+ <&usb_1_ss1_qmpphy QMP_USB43DP_USB3_PHY>;
+ phy-names = "usb2-phy",
+ "usb3-phy";
+
+ snps,dis_u2_susphy_quirk;
+ snps,dis_enblslpm_quirk;
+ snps,usb3_lpm_capable;
+
+ dma-coherent;
+
+ port {
+ usb_1_ss1_role_switch: endpoint {
+ };
+ };
+ };
+ };
+
pdc: interrupt-controller@b220000 {
compatible = "qcom,x1e80100-pdc", "qcom,pdc";
reg = <0 0x0b220000 0 0x30000>, <0 0x174000f0 0 0x64>;
--
2.34.1
^ permalink raw reply related [flat|nested] 14+ messages in thread* [PATCH v6 07/11] arm64: dts: qcom: x1e80100: Add PCIe nodes
2024-01-29 12:45 [PATCH v6 00/11] arm64: dts: qcom: Add more support to X1E80100 base dtsi, CRD and QCP boards Abel Vesa
` (5 preceding siblings ...)
2024-01-29 12:45 ` [PATCH v6 06/11] arm64: dts: qcom: x1e80100: Add USB nodes Abel Vesa
@ 2024-01-29 12:45 ` Abel Vesa
2024-01-29 12:45 ` [PATCH v6 08/11] arm64: dts: qcom: x1e80100: Add display nodes Abel Vesa
` (4 subsequent siblings)
11 siblings, 0 replies; 14+ messages in thread
From: Abel Vesa @ 2024-01-29 12:45 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Konrad Dybcio, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Sibi Sankar, Rajendra Nayak
Cc: linux-arm-msm, devicetree, linux-kernel, Abel Vesa
Add nodes for PCIe 4 and 6 controllers and their PHYs for X1E80100 platform.
Co-developed-by: Sibi Sankar <quic_sibis@quicinc.com>
Signed-off-by: Sibi Sankar <quic_sibis@quicinc.com>
Co-developed-by: Rajendra Nayak <quic_rjendra@quicinc.com>
Signed-off-by: Rajendra Nayak <quic_rjendra@quicinc.com>
Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
---
arch/arm64/boot/dts/qcom/x1e80100.dtsi | 242 ++++++++++++++++++++++++++++++++-
1 file changed, 240 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/x1e80100.dtsi b/arch/arm64/boot/dts/qcom/x1e80100.dtsi
index ee61e1cbc5af..20aa04aa80f7 100644
--- a/arch/arm64/boot/dts/qcom/x1e80100.dtsi
+++ b/arch/arm64/boot/dts/qcom/x1e80100.dtsi
@@ -732,9 +732,9 @@ gcc: clock-controller@100000 {
clocks = <&bi_tcxo_div2>,
<&sleep_clk>,
<0>,
+ <&pcie4_phy>,
<0>,
- <0>,
- <0>,
+ <&pcie6a_phy>,
<0>,
<&usb_1_ss0_qmpphy QMP_USB43DP_USB3_PIPE_CLK>,
<&usb_1_ss1_qmpphy QMP_USB43DP_USB3_PIPE_CLK>,
@@ -2722,6 +2722,244 @@ mmss_noc: interconnect@1780000 {
#interconnect-cells = <2>;
};
+ pcie6a: pci@1bf8000 {
+ device_type = "pci";
+ compatible = "qcom,pcie-x1e80100";
+ reg = <0 0x01bf8000 0 0x3000>,
+ <0 0x70000000 0 0xf1d>,
+ <0 0x70000f20 0 0xa8>,
+ <0 0x70001000 0 0x1000>,
+ <0 0x70100000 0 0x100000>;
+ reg-names = "parf",
+ "dbi",
+ "elbi",
+ "atu",
+ "config";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges = <0x01000000 0 0x00000000 0 0x70200000 0 0x100000>,
+ <0x02000000 0 0x70300000 0 0x70300000 0 0x3d00000>;
+ bus-range = <0 0xff>;
+
+ dma-coherent;
+
+ linux,pci-domain = <7>;
+ num-lanes = <2>;
+
+ interrupts = <GIC_SPI 773 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 774 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 837 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 838 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 839 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 840 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 841 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 842 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "msi0",
+ "msi1",
+ "msi2",
+ "msi3",
+ "msi4",
+ "msi5",
+ "msi6",
+ "msi7";
+
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 0x7>;
+ interrupt-map = <0 0 0 1 &intc 0 0 0 843 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 2 &intc 0 0 0 844 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 3 &intc 0 0 0 845 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 4 &intc 0 0 0 772 IRQ_TYPE_LEVEL_HIGH>;
+
+ clocks = <&gcc GCC_PCIE_6A_AUX_CLK>,
+ <&gcc GCC_PCIE_6A_CFG_AHB_CLK>,
+ <&gcc GCC_PCIE_6A_MSTR_AXI_CLK>,
+ <&gcc GCC_PCIE_6A_SLV_AXI_CLK>,
+ <&gcc GCC_PCIE_6A_SLV_Q2A_AXI_CLK>,
+ <&gcc GCC_CFG_NOC_PCIE_ANOC_SOUTH_AHB_CLK>,
+ <&gcc GCC_CNOC_PCIE_SOUTH_SF_AXI_CLK>;
+ clock-names = "aux",
+ "cfg",
+ "bus_master",
+ "bus_slave",
+ "slave_q2a",
+ "noc_aggr",
+ "cnoc_sf_axi";
+
+ assigned-clocks = <&gcc GCC_PCIE_6A_AUX_CLK>;
+ assigned-clock-rates = <19200000>;
+
+ interconnects = <&pcie_south_anoc MASTER_PCIE_6A QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+ &cnoc_main SLAVE_PCIE_6A QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "pcie-mem",
+ "cpu-pcie";
+
+ resets = <&gcc GCC_PCIE_6A_BCR>,
+ <&gcc GCC_PCIE_6A_LINK_DOWN_BCR>;
+ reset-names = "pci",
+ "link_down";
+
+ power-domains = <&gcc GCC_PCIE_6A_GDSC>;
+
+ phys = <&pcie6a_phy>;
+ phy-names = "pciephy";
+
+ status = "disabled";
+ };
+
+ pcie6a_phy: phy@1bfc000 {
+ compatible = "qcom,x1e80100-qmp-gen4x2-pcie-phy";
+ reg = <0 0x01bfc000 0 0x2000>;
+
+ clocks = <&gcc GCC_PCIE_6A_PHY_AUX_CLK>,
+ <&gcc GCC_PCIE_6A_CFG_AHB_CLK>,
+ <&rpmhcc RPMH_CXO_CLK>,
+ <&gcc GCC_PCIE_6A_PHY_RCHNG_CLK>,
+ <&gcc GCC_PCIE_6A_PIPE_CLK>;
+ clock-names = "aux",
+ "cfg_ahb",
+ "ref",
+ "rchng",
+ "pipe";
+
+ resets = <&gcc GCC_PCIE_6A_PHY_BCR>,
+ <&gcc GCC_PCIE_6A_NOCSR_COM_PHY_BCR>;
+ reset-names = "phy",
+ "phy_nocsr";
+
+ assigned-clocks = <&gcc GCC_PCIE_6A_PHY_RCHNG_CLK>;
+ assigned-clock-rates = <100000000>;
+
+ power-domains = <&gcc GCC_PCIE_6_PHY_GDSC>;
+
+ #clock-cells = <0>;
+ clock-output-names = "pcie6a_pipe_clk";
+
+ #phy-cells = <0>;
+
+ status = "disabled";
+ };
+
+ pcie4: pci@1c08000 {
+ device_type = "pci";
+ compatible = "qcom,pcie-x1e80100";
+ reg = <0 0x01c08000 0 0x3000>,
+ <0 0x7c000000 0 0xf1d>,
+ <0 0x7c000f40 0 0xa8>,
+ <0 0x7c001000 0 0x1000>,
+ <0 0x7c100000 0 0x100000>,
+ <0 0x01c0b000 0 0x1000>;
+ reg-names = "parf",
+ "dbi",
+ "elbi",
+ "atu",
+ "config",
+ "mhi";
+ #address-cells = <3>;
+ #size-cells = <2>;
+ ranges = <0x01000000 0 0x00000000 0 0x7c200000 0 0x100000>,
+ <0x02000000 0 0x7c300000 0 0x7c300000 0 0x3d00000>;
+ bus-range = <0x00 0xff>;
+
+ dma-coherent;
+
+ linux,pci-domain = <5>;
+ num-lanes = <2>;
+
+ interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "msi0",
+ "msi1",
+ "msi2",
+ "msi3",
+ "msi4",
+ "msi5",
+ "msi6",
+ "msi7";
+
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0 0 0 0x7>;
+ interrupt-map = <0 0 0 1 &intc 0 0 0 149 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 2 &intc 0 0 0 150 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 3 &intc 0 0 0 151 IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 4 &intc 0 0 0 152 IRQ_TYPE_LEVEL_HIGH>;
+
+ clocks = <&gcc GCC_PCIE_4_AUX_CLK>,
+ <&gcc GCC_PCIE_4_CFG_AHB_CLK>,
+ <&gcc GCC_PCIE_4_MSTR_AXI_CLK>,
+ <&gcc GCC_PCIE_4_SLV_AXI_CLK>,
+ <&gcc GCC_PCIE_4_SLV_Q2A_AXI_CLK>,
+ <&gcc GCC_CFG_NOC_PCIE_ANOC_NORTH_AHB_CLK>,
+ <&gcc GCC_CNOC_PCIE_NORTH_SF_AXI_CLK>;
+ clock-names = "aux",
+ "cfg",
+ "bus_master",
+ "bus_slave",
+ "slave_q2a",
+ "noc_aggr",
+ "cnoc_sf_axi";
+
+ assigned-clocks = <&gcc GCC_PCIE_4_AUX_CLK>;
+ assigned-clock-rates = <19200000>;
+
+ interconnects = <&pcie_south_anoc MASTER_PCIE_4 QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS
+ &cnoc_main SLAVE_PCIE_4 QCOM_ICC_TAG_ALWAYS>;
+ interconnect-names = "pcie-mem",
+ "cpu-pcie";
+
+ resets = <&gcc GCC_PCIE_4_BCR>,
+ <&gcc GCC_PCIE_4_LINK_DOWN_BCR>;
+ reset-names = "pci",
+ "link_down";
+
+ power-domains = <&gcc GCC_PCIE_4_GDSC>;
+
+ phys = <&pcie4_phy>;
+ phy-names = "pciephy";
+
+ status = "disabled";
+ };
+
+ pcie4_phy: phy@1c0e000 {
+ compatible = "qcom,x1e80100-qmp-gen3x2-pcie-phy";
+ reg = <0 0x01c0e000 0 0x2000>;
+
+ clocks = <&gcc GCC_PCIE_4_AUX_CLK>,
+ <&gcc GCC_PCIE_4_CFG_AHB_CLK>,
+ <&rpmhcc RPMH_CXO_CLK>,
+ <&gcc GCC_PCIE_4_PHY_RCHNG_CLK>,
+ <&gcc GCC_PCIE_4_PIPE_CLK>;
+ clock-names = "aux",
+ "cfg_ahb",
+ "ref",
+ "rchng",
+ "pipe";
+
+ resets = <&gcc GCC_PCIE_4_PHY_BCR>;
+ reset-names = "phy";
+
+ assigned-clocks = <&gcc GCC_PCIE_4_PHY_RCHNG_CLK>;
+ assigned-clock-rates = <100000000>;
+
+ power-domains = <&gcc GCC_PCIE_4_PHY_GDSC>;
+
+ #clock-cells = <0>;
+ clock-output-names = "pcie4_pipe_clk";
+
+ #phy-cells = <0>;
+
+ status = "disabled";
+ };
+
tcsr_mutex: hwlock@1f40000 {
compatible = "qcom,tcsr-mutex";
reg = <0 0x01f40000 0 0x20000>;
--
2.34.1
^ permalink raw reply related [flat|nested] 14+ messages in thread* [PATCH v6 08/11] arm64: dts: qcom: x1e80100: Add display nodes
2024-01-29 12:45 [PATCH v6 00/11] arm64: dts: qcom: Add more support to X1E80100 base dtsi, CRD and QCP boards Abel Vesa
` (6 preceding siblings ...)
2024-01-29 12:45 ` [PATCH v6 07/11] arm64: dts: qcom: x1e80100: Add PCIe nodes Abel Vesa
@ 2024-01-29 12:45 ` Abel Vesa
2024-01-29 12:45 ` [PATCH v6 09/11] arm64: dts: qcom: x1e80100-crd: Enable more support Abel Vesa
` (3 subsequent siblings)
11 siblings, 0 replies; 14+ messages in thread
From: Abel Vesa @ 2024-01-29 12:45 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Konrad Dybcio, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Sibi Sankar, Rajendra Nayak
Cc: linux-arm-msm, devicetree, linux-kernel, Abel Vesa
Add the required nodes to support display on X1E80100.
Co-developed-by: Sibi Sankar <quic_sibis@quicinc.com>
Signed-off-by: Sibi Sankar <quic_sibis@quicinc.com>
Co-developed-by: Rajendra Nayak <quic_rjendra@quicinc.com>
Signed-off-by: Rajendra Nayak <quic_rjendra@quicinc.com>
Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
---
arch/arm64/boot/dts/qcom/x1e80100.dtsi | 519 +++++++++++++++++++++++++++++++++
1 file changed, 519 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/x1e80100.dtsi b/arch/arm64/boot/dts/qcom/x1e80100.dtsi
index 20aa04aa80f7..7fc5883bf593 100644
--- a/arch/arm64/boot/dts/qcom/x1e80100.dtsi
+++ b/arch/arm64/boot/dts/qcom/x1e80100.dtsi
@@ -4,6 +4,7 @@
*/
#include <dt-bindings/clock/qcom,rpmh.h>
+#include <dt-bindings/clock/qcom,x1e80100-dispcc.h>
#include <dt-bindings/clock/qcom,x1e80100-gcc.h>
#include <dt-bindings/clock/qcom,x1e80100-tcsr.h>
#include <dt-bindings/dma/qcom-gpi.h>
@@ -3344,6 +3345,524 @@ usb_1_ss1_role_switch: endpoint {
};
};
+ mdss: display-subsystem@ae00000 {
+ compatible = "qcom,x1e80100-mdss";
+ reg = <0 0x0ae00000 0 0x1000>;
+ reg-names = "mdss";
+
+ interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
+
+ clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
+ <&gcc GCC_DISP_HF_AXI_CLK>,
+ <&dispcc DISP_CC_MDSS_MDP_CLK>;
+
+ resets = <&dispcc DISP_CC_MDSS_CORE_BCR>;
+
+ interconnects = <&mmss_noc MASTER_MDP QCOM_ICC_TAG_ALWAYS
+ &gem_noc SLAVE_LLCC QCOM_ICC_TAG_ALWAYS>,
+ <&mc_virt MASTER_LLCC QCOM_ICC_TAG_ALWAYS
+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,
+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
+ &config_noc SLAVE_DISPLAY_CFG QCOM_ICC_TAG_ACTIVE_ONLY>;
+ interconnect-names = "mdp0-mem",
+ "mdp1-mem",
+ "cpu-cfg";
+
+ power-domains = <&dispcc MDSS_GDSC>;
+
+ iommus = <&apps_smmu 0x1c00 0x2>;
+
+ interrupt-controller;
+ #interrupt-cells = <1>;
+
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ status = "disabled";
+
+ mdss_mdp: display-controller@ae01000 {
+ compatible = "qcom,x1e80100-dpu";
+ reg = <0 0x0ae01000 0 0x8f000>,
+ <0 0x0aeb0000 0 0x2008>;
+ reg-names = "mdp",
+ "vbif";
+
+ interrupts-extended = <&mdss 0>;
+
+ clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
+ <&dispcc DISP_CC_MDSS_AHB_CLK>,
+ <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
+ <&dispcc DISP_CC_MDSS_MDP_CLK>,
+ <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
+ clock-names = "nrt_bus",
+ "iface",
+ "lut",
+ "core",
+ "vsync";
+
+ operating-points-v2 = <&mdp_opp_table>;
+
+ power-domains = <&rpmhpd RPMHPD_MMCX>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ mdss_intf0_out: endpoint {
+ remote-endpoint = <&mdss_dp0_in>;
+ };
+ };
+
+ port@4 {
+ reg = <4>;
+
+ mdss_intf4_out: endpoint {
+ remote-endpoint = <&mdss_dp1_in>;
+ };
+ };
+
+ port@5 {
+ reg = <5>;
+
+ mdss_intf5_out: endpoint {
+ remote-endpoint = <&mdss_dp3_in>;
+ };
+ };
+
+ port@6 {
+ reg = <6>;
+
+ mdss_intf6_out: endpoint {
+ remote-endpoint = <&mdss_dp2_in>;
+ };
+ };
+ };
+
+ mdp_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ opp-200000000 {
+ opp-hz = /bits/ 64 <200000000>;
+ required-opps = <&rpmhpd_opp_low_svs>;
+ };
+
+ opp-325000000 {
+ opp-hz = /bits/ 64 <325000000>;
+ required-opps = <&rpmhpd_opp_svs>;
+ };
+
+ opp-375000000 {
+ opp-hz = /bits/ 64 <375000000>;
+ required-opps = <&rpmhpd_opp_svs_l1>;
+ };
+
+ opp-514000000 {
+ opp-hz = /bits/ 64 <514000000>;
+ required-opps = <&rpmhpd_opp_nom>;
+ };
+
+ opp-575000000 {
+ opp-hz = /bits/ 64 <575000000>;
+ required-opps = <&rpmhpd_opp_nom_l1>;
+ };
+ };
+ };
+
+ mdss_dp0: displayport-controller@ae90000 {
+ compatible = "qcom,x1e80100-dp";
+ reg = <0 0xae90000 0 0x200>,
+ <0 0xae90200 0 0x200>,
+ <0 0xae90400 0 0x600>,
+ <0 0xae91000 0 0x400>,
+ <0 0xae91400 0 0x400>;
+
+ interrupts-extended = <&mdss 12>;
+
+ clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
+ <&dispcc DISP_CC_MDSS_DPTX0_AUX_CLK>,
+ <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK>,
+ <&dispcc DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>,
+ <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK>;
+ clock-names = "core_iface",
+ "core_aux",
+ "ctrl_link",
+ "ctrl_link_iface",
+ "stream_pixel";
+
+ assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>,
+ <&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>;
+ assigned-clock-parents = <&usb_1_ss0_qmpphy QMP_USB43DP_DP_LINK_CLK>,
+ <&usb_1_ss0_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>;
+
+ operating-points-v2 = <&mdss_dp0_opp_table>;
+
+ power-domains = <&rpmhpd RPMHPD_MMCX>;
+
+ phys = <&usb_1_ss0_qmpphy QMP_USB43DP_DP_PHY>;
+ phy-names = "dp";
+
+ #sound-dai-cells = <0>;
+
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ mdss_dp0_in: endpoint {
+ remote-endpoint = <&mdss_intf0_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ mdss_dp0_out: endpoint {
+ };
+ };
+ };
+
+ mdss_dp0_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ opp-160000000 {
+ opp-hz = /bits/ 64 <160000000>;
+ required-opps = <&rpmhpd_opp_low_svs>;
+ };
+
+ opp-270000000 {
+ opp-hz = /bits/ 64 <270000000>;
+ required-opps = <&rpmhpd_opp_svs>;
+ };
+
+ opp-540000000 {
+ opp-hz = /bits/ 64 <540000000>;
+ required-opps = <&rpmhpd_opp_svs_l1>;
+ };
+
+ opp-810000000 {
+ opp-hz = /bits/ 64 <810000000>;
+ required-opps = <&rpmhpd_opp_nom>;
+ };
+ };
+ };
+
+ mdss_dp1: displayport-controller@ae98000 {
+ compatible = "qcom,x1e80100-dp";
+ reg = <0 0xae98000 0 0x200>,
+ <0 0xae98200 0 0x200>,
+ <0 0xae98400 0 0x600>,
+ <0 0xae99000 0 0x400>,
+ <0 0xae99400 0 0x400>;
+
+ interrupts-extended = <&mdss 13>;
+
+ clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
+ <&dispcc DISP_CC_MDSS_DPTX1_AUX_CLK>,
+ <&dispcc DISP_CC_MDSS_DPTX1_LINK_CLK>,
+ <&dispcc DISP_CC_MDSS_DPTX1_LINK_INTF_CLK>,
+ <&dispcc DISP_CC_MDSS_DPTX1_PIXEL0_CLK>;
+ clock-names = "core_iface",
+ "core_aux",
+ "ctrl_link",
+ "ctrl_link_iface",
+ "stream_pixel";
+
+ assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX1_LINK_CLK_SRC>,
+ <&dispcc DISP_CC_MDSS_DPTX1_PIXEL0_CLK_SRC>;
+ assigned-clock-parents = <&usb_1_ss1_qmpphy QMP_USB43DP_DP_LINK_CLK>,
+ <&usb_1_ss1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>;
+
+ operating-points-v2 = <&mdss_dp1_opp_table>;
+
+ power-domains = <&rpmhpd RPMHPD_MMCX>;
+
+ phys = <&usb_1_ss1_qmpphy QMP_USB43DP_DP_PHY>;
+ phy-names = "dp";
+
+ #sound-dai-cells = <0>;
+
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ mdss_dp1_in: endpoint {
+ remote-endpoint = <&mdss_intf4_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+
+ mdss_dp1_out: endpoint {
+ };
+ };
+ };
+
+ mdss_dp1_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ opp-160000000 {
+ opp-hz = /bits/ 64 <160000000>;
+ required-opps = <&rpmhpd_opp_low_svs>;
+ };
+
+ opp-270000000 {
+ opp-hz = /bits/ 64 <270000000>;
+ required-opps = <&rpmhpd_opp_svs>;
+ };
+
+ opp-540000000 {
+ opp-hz = /bits/ 64 <540000000>;
+ required-opps = <&rpmhpd_opp_svs_l1>;
+ };
+
+ opp-810000000 {
+ opp-hz = /bits/ 64 <810000000>;
+ required-opps = <&rpmhpd_opp_nom>;
+ };
+ };
+ };
+
+ mdss_dp2: displayport-controller@ae9a000 {
+ compatible = "qcom,x1e80100-dp";
+ reg = <0 0xae9a000 0 0x200>,
+ <0 0xae9a200 0 0x200>,
+ <0 0xae9a400 0 0x600>,
+ <0 0xae9b000 0 0x400>,
+ <0 0xae9b400 0 0x400>;
+
+ interrupts-extended = <&mdss 14>;
+
+ clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
+ <&dispcc DISP_CC_MDSS_DPTX2_AUX_CLK>,
+ <&dispcc DISP_CC_MDSS_DPTX2_LINK_CLK>,
+ <&dispcc DISP_CC_MDSS_DPTX2_LINK_INTF_CLK>,
+ <&dispcc DISP_CC_MDSS_DPTX2_PIXEL0_CLK>;
+ clock-names = "core_iface",
+ "core_aux",
+ "ctrl_link",
+ "ctrl_link_iface",
+ "stream_pixel";
+
+ assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX2_LINK_CLK_SRC>,
+ <&dispcc DISP_CC_MDSS_DPTX2_PIXEL0_CLK_SRC>;
+ assigned-clock-parents = <&mdss_dp2_phy 0>,
+ <&mdss_dp2_phy 1>;
+
+ operating-points-v2 = <&mdss_dp2_opp_table>;
+
+ power-domains = <&rpmhpd RPMHPD_MMCX>;
+
+ phys = <&mdss_dp2_phy>;
+ phy-names = "dp";
+
+ #sound-dai-cells = <0>;
+
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ mdss_dp2_in: endpoint {
+ remote-endpoint = <&mdss_intf6_out>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ };
+ };
+
+ mdss_dp2_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ opp-160000000 {
+ opp-hz = /bits/ 64 <160000000>;
+ required-opps = <&rpmhpd_opp_low_svs>;
+ };
+
+ opp-270000000 {
+ opp-hz = /bits/ 64 <270000000>;
+ required-opps = <&rpmhpd_opp_svs>;
+ };
+
+ opp-540000000 {
+ opp-hz = /bits/ 64 <540000000>;
+ required-opps = <&rpmhpd_opp_svs_l1>;
+ };
+
+ opp-810000000 {
+ opp-hz = /bits/ 64 <810000000>;
+ required-opps = <&rpmhpd_opp_nom>;
+ };
+ };
+ };
+
+ mdss_dp3: displayport-controller@aea0000 {
+ compatible = "qcom,x1e80100-dp";
+ reg = <0 0xaea0000 0 0x200>,
+ <0 0xaea0200 0 0x200>,
+ <0 0xaea0400 0 0x600>,
+ <0 0xaea1000 0 0x400>,
+ <0 0xaea1400 0 0x400>;
+
+ interrupts-extended = <&mdss 15>;
+
+ clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
+ <&dispcc DISP_CC_MDSS_DPTX3_AUX_CLK>,
+ <&dispcc DISP_CC_MDSS_DPTX3_LINK_CLK>,
+ <&dispcc DISP_CC_MDSS_DPTX3_LINK_INTF_CLK>,
+ <&dispcc DISP_CC_MDSS_DPTX3_PIXEL0_CLK>;
+ clock-names = "core_iface",
+ "core_aux",
+ "ctrl_link",
+ "ctrl_link_iface",
+ "stream_pixel";
+
+ assigned-clocks = <&dispcc DISP_CC_MDSS_DPTX3_LINK_CLK_SRC>,
+ <&dispcc DISP_CC_MDSS_DPTX3_PIXEL0_CLK_SRC>;
+ assigned-clock-parents = <&mdss_dp3_phy 0>,
+ <&mdss_dp3_phy 1>;
+
+ operating-points-v2 = <&mdss_dp3_opp_table>;
+
+ power-domains = <&rpmhpd RPMHPD_MMCX>;
+
+ phys = <&mdss_dp3_phy>;
+ phy-names = "dp";
+
+ #sound-dai-cells = <0>;
+
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+
+ mdss_dp3_in: endpoint {
+ remote-endpoint = <&mdss_intf5_out>;
+
+ link-frequencies = /bits/ 64 <8100000000>;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ };
+ };
+
+ mdss_dp3_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ opp-160000000 {
+ opp-hz = /bits/ 64 <160000000>;
+ required-opps = <&rpmhpd_opp_low_svs>;
+ };
+
+ opp-270000000 {
+ opp-hz = /bits/ 64 <270000000>;
+ required-opps = <&rpmhpd_opp_svs>;
+ };
+
+ opp-540000000 {
+ opp-hz = /bits/ 64 <540000000>;
+ required-opps = <&rpmhpd_opp_svs_l1>;
+ };
+
+ opp-810000000 {
+ opp-hz = /bits/ 64 <810000000>;
+ required-opps = <&rpmhpd_opp_nom>;
+ };
+ };
+ };
+
+ };
+
+ mdss_dp2_phy: phy@aec2a00 {
+ compatible = "qcom,x1e80100-dp-phy";
+ reg = <0 0x0aec2a00 0 0x19c>,
+ <0 0x0aec2200 0 0xec>,
+ <0 0x0aec2600 0 0xec>,
+ <0 0x0aec2000 0 0x1c8>;
+
+ clocks = <&dispcc DISP_CC_MDSS_DPTX2_AUX_CLK>,
+ <&dispcc DISP_CC_MDSS_AHB_CLK>;
+ clock-names = "aux",
+ "cfg_ahb";
+
+ power-domains = <&rpmhpd RPMHPD_MX>;
+
+ #clock-cells = <1>;
+ #phy-cells = <0>;
+
+ status = "disabled";
+ };
+
+ mdss_dp3_phy: phy@aec5a00 {
+ compatible = "qcom,x1e80100-dp-phy";
+ reg = <0 0x0aec5a00 0 0x19c>,
+ <0 0x0aec5200 0 0xec>,
+ <0 0x0aec5600 0 0xec>,
+ <0 0x0aec5000 0 0x1c8>;
+
+ clocks = <&dispcc DISP_CC_MDSS_DPTX3_AUX_CLK>,
+ <&dispcc DISP_CC_MDSS_AHB_CLK>;
+ clock-names = "aux",
+ "cfg_ahb";
+
+ power-domains = <&rpmhpd RPMHPD_MX>;
+
+ #clock-cells = <1>;
+ #phy-cells = <0>;
+
+ status = "disabled";
+ };
+
+ dispcc: clock-controller@af00000 {
+ compatible = "qcom,x1e80100-dispcc";
+ reg = <0 0x0af00000 0 0x20000>;
+ clocks = <&bi_tcxo_div2>,
+ <&bi_tcxo_ao_div2>,
+ <&gcc GCC_DISP_AHB_CLK>,
+ <&sleep_clk>,
+ <0>, /* dsi0 */
+ <0>,
+ <0>, /* dsi1 */
+ <0>,
+ <&usb_1_ss0_qmpphy QMP_USB43DP_DP_LINK_CLK>, /* dp0 */
+ <&usb_1_ss0_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>,
+ <&usb_1_ss1_qmpphy QMP_USB43DP_DP_LINK_CLK>, /* dp1 */
+ <&usb_1_ss1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>,
+ <&mdss_dp2_phy 0>, /* dp2 */
+ <&mdss_dp2_phy 1>,
+ <&mdss_dp3_phy 0>, /* dp3 */
+ <&mdss_dp3_phy 1>;
+ power-domains = <&rpmhpd RPMHPD_MMCX>;
+ required-opps = <&rpmhpd_opp_low_svs>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ #power-domain-cells = <1>;
+ };
+
pdc: interrupt-controller@b220000 {
compatible = "qcom,x1e80100-pdc", "qcom,pdc";
reg = <0 0x0b220000 0 0x30000>, <0 0x174000f0 0 0x64>;
--
2.34.1
^ permalink raw reply related [flat|nested] 14+ messages in thread* [PATCH v6 09/11] arm64: dts: qcom: x1e80100-crd: Enable more support
2024-01-29 12:45 [PATCH v6 00/11] arm64: dts: qcom: Add more support to X1E80100 base dtsi, CRD and QCP boards Abel Vesa
` (7 preceding siblings ...)
2024-01-29 12:45 ` [PATCH v6 08/11] arm64: dts: qcom: x1e80100: Add display nodes Abel Vesa
@ 2024-01-29 12:45 ` Abel Vesa
2024-01-29 12:45 ` [PATCH v6 10/11] arm64: dts: qcom: x1e80100-qcp: " Abel Vesa
` (2 subsequent siblings)
11 siblings, 0 replies; 14+ messages in thread
From: Abel Vesa @ 2024-01-29 12:45 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Konrad Dybcio, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Sibi Sankar, Rajendra Nayak
Cc: linux-arm-msm, devicetree, linux-kernel, Abel Vesa
Enable touchscreen, touchpad, keyboard, display, pcie and usb
support.
Co-developed-by: Sibi Sankar <quic_sibis@quicinc.com>
Signed-off-by: Sibi Sankar <quic_sibis@quicinc.com>
Co-developed-by: Rajendra Nayak <quic_rjendra@quicinc.com>
Signed-off-by: Rajendra Nayak <quic_rjendra@quicinc.com>
Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
---
arch/arm64/boot/dts/qcom/x1e80100-crd.dts | 222 ++++++++++++++++++++++++++++++
1 file changed, 222 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/x1e80100-crd.dts b/arch/arm64/boot/dts/qcom/x1e80100-crd.dts
index 7532d8eca2de..7e7cc8e43f87 100644
--- a/arch/arm64/boot/dts/qcom/x1e80100-crd.dts
+++ b/arch/arm64/boot/dts/qcom/x1e80100-crd.dts
@@ -401,10 +401,145 @@ vreg_l3j_0p8: ldo3 {
};
};
+&i2c0 {
+ clock-frequency = <400000>;
+
+ status = "okay";
+
+ touchpad@15 {
+ compatible = "hid-over-i2c";
+ reg = <0x15>;
+
+ hid-descr-addr = <0x1>;
+ interrupts-extended = <&tlmm 3 IRQ_TYPE_LEVEL_LOW>;
+
+ pinctrl-0 = <&tpad_default>;
+ pinctrl-names = "default";
+
+ wakeup-source;
+ };
+
+ keyboard@3a {
+ compatible = "hid-over-i2c";
+ reg = <0x3a>;
+
+ hid-descr-addr = <0x1>;
+ interrupts-extended = <&tlmm 67 IRQ_TYPE_LEVEL_LOW>;
+
+ pinctrl-0 = <&kybd_default>;
+ pinctrl-names = "default";
+
+ wakeup-source;
+ };
+};
+
+&i2c8 {
+ clock-frequency = <400000>;
+
+ status = "okay";
+
+ touchscreen@10 {
+ compatible = "hid-over-i2c";
+ reg = <0x10>;
+
+ hid-descr-addr = <0x1>;
+ interrupts-extended = <&tlmm 51 IRQ_TYPE_LEVEL_LOW>;
+
+ pinctrl-0 = <&ts0_default>;
+ pinctrl-names = "default";
+ };
+};
+
+&mdss {
+ status = "okay";
+};
+
+&mdss_dp3 {
+ compatible = "qcom,x1e80100-dp";
+ /delete-property/ #sound-dai-cells;
+
+ data-lanes = <0 1 2 3>;
+
+ status = "okay";
+
+ aux-bus {
+ panel {
+ compatible = "edp-panel";
+ power-supply = <&vreg_edp_3p3>;
+
+ port {
+ edp_panel_in: endpoint {
+ remote-endpoint = <&mdss_dp3_out>;
+ };
+ };
+ };
+ };
+
+ ports {
+ port@1 {
+ reg = <1>;
+ mdss_dp3_out: endpoint {
+ remote-endpoint = <&edp_panel_in>;
+ };
+ };
+ };
+};
+
+&mdss_dp3_phy {
+ vdda-phy-supply = <&vreg_l3j_0p8>;
+ vdda-pll-supply = <&vreg_l2j_1p2>;
+
+ status = "okay";
+};
+
+&pcie4 {
+ status = "okay";
+};
+
+&pcie4_phy {
+ vdda-phy-supply = <&vreg_l3j_0p8>;
+ vdda-pll-supply = <&vreg_l3e_1p2>;
+
+ status = "okay";
+};
+
+&pcie6a {
+ status = "okay";
+};
+
+&pcie6a_phy {
+ vdda-phy-supply = <&vreg_l3j_0p8>;
+ vdda-pll-supply = <&vreg_l2j_1p2>;
+
+ status = "okay";
+};
+
+&qupv3_0 {
+ status = "okay";
+};
+
+&qupv3_1 {
+ status = "okay";
+};
+
&qupv3_2 {
status = "okay";
};
+&remoteproc_adsp {
+ firmware-name = "qcom/x1e80100/adsp.mbn",
+ "qcom/x1e80100/adsp_dtb.mbn";
+
+ status = "okay";
+};
+
+&remoteproc_cdsp {
+ firmware-name = "qcom/x1e80100/cdsp.mbn",
+ "qcom/x1e80100/cdsp_dtb.mbn";
+
+ status = "okay";
+};
+
&tlmm {
gpio-reserved-ranges = <34 2>, /* Unused */
<44 4>, /* SPI (TPM) */
@@ -416,9 +551,96 @@ edp_reg_en: edp-reg-en-state {
drive-strength = <16>;
bias-disable;
};
+
+ kybd_default: kybd-default-state {
+ pins = "gpio67";
+ function = "gpio";
+ bias-disable;
+ };
+
+ tpad_default: tpad-default-state {
+ pins = "gpio3";
+ function = "gpio";
+ bias-disable;
+ };
+
+ ts0_default: ts0-default-state {
+ int-n-pins {
+ pins = "gpio51";
+ function = "gpio";
+ bias-disable;
+ };
+
+ reset-n-pins {
+ pins = "gpio48";
+ function = "gpio";
+ output-high;
+ drive-strength = <16>;
+ };
+ };
};
&uart21 {
compatible = "qcom,geni-debug-uart";
status = "okay";
};
+
+&usb_1_ss0_hsphy {
+ vdd-supply = <&vreg_l2e_0p8>;
+ vdda12-supply = <&vreg_l3e_1p2>;
+
+ status = "okay";
+};
+
+&usb_1_ss0_qmpphy {
+ status = "okay";
+};
+
+&usb_1_ss0 {
+ status = "okay";
+};
+
+&usb_1_ss0_dwc3 {
+ dr_mode = "host";
+ usb-role-switch;
+};
+
+&usb_1_ss1_hsphy {
+ vdd-supply = <&vreg_l2e_0p8>;
+ vdda12-supply = <&vreg_l3e_1p2>;
+
+ status = "okay";
+};
+
+&usb_1_ss1_qmpphy {
+ status = "okay";
+};
+
+&usb_1_ss1 {
+ status = "okay";
+};
+
+&usb_1_ss1_dwc3 {
+ dr_mode = "host";
+ usb-role-switch;
+};
+
+&usb_1_ss2_hsphy {
+ vdd-supply = <&vreg_l2e_0p8>;
+ vdda12-supply = <&vreg_l3e_1p2>;
+
+ status = "okay";
+};
+
+&usb_1_ss2_qmpphy {
+ status = "okay";
+};
+
+&usb_1_ss2 {
+ status = "okay";
+};
+
+&usb_1_ss2_dwc3 {
+ dr_mode = "host";
+ usb-role-switch;
+};
--
2.34.1
^ permalink raw reply related [flat|nested] 14+ messages in thread* [PATCH v6 10/11] arm64: dts: qcom: x1e80100-qcp: Enable more support
2024-01-29 12:45 [PATCH v6 00/11] arm64: dts: qcom: Add more support to X1E80100 base dtsi, CRD and QCP boards Abel Vesa
` (8 preceding siblings ...)
2024-01-29 12:45 ` [PATCH v6 09/11] arm64: dts: qcom: x1e80100-crd: Enable more support Abel Vesa
@ 2024-01-29 12:45 ` Abel Vesa
2024-01-29 12:45 ` [PATCH v6 11/11] arm64: dts: qcom: x1e80100-qcp: Fix supplies for LDOs 3E and 2J Abel Vesa
2024-02-07 4:46 ` [PATCH v6 00/11] arm64: dts: qcom: Add more support to X1E80100 base dtsi, CRD and QCP boards Bjorn Andersson
11 siblings, 0 replies; 14+ messages in thread
From: Abel Vesa @ 2024-01-29 12:45 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Konrad Dybcio, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Sibi Sankar, Rajendra Nayak
Cc: linux-arm-msm, devicetree, linux-kernel, Abel Vesa
Enable display, pcie and usb support.
Co-developed-by: Sibi Sankar <quic_sibis@quicinc.com>
Signed-off-by: Sibi Sankar <quic_sibis@quicinc.com>
Co-developed-by: Rajendra Nayak <quic_rjendra@quicinc.com>
Signed-off-by: Rajendra Nayak <quic_rjendra@quicinc.com>
Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
---
arch/arm64/boot/dts/qcom/x1e80100-qcp.dts | 171 ++++++++++++++++++++++++++++++
1 file changed, 171 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/x1e80100-qcp.dts b/arch/arm64/boot/dts/qcom/x1e80100-qcp.dts
index a37ad9475c90..8dbf6d0eaac3 100644
--- a/arch/arm64/boot/dts/qcom/x1e80100-qcp.dts
+++ b/arch/arm64/boot/dts/qcom/x1e80100-qcp.dts
@@ -5,6 +5,7 @@
/dts-v1/;
+#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/regulator/qcom,rpmh-regulator.h>
#include "x1e80100.dtsi"
@@ -31,6 +32,23 @@ vph_pwr: vph-pwr-regulator {
regulator-always-on;
regulator-boot-on;
};
+
+ vreg_edp_3p3: regulator-edp-3p3 {
+ compatible = "regulator-fixed";
+
+ regulator-name = "VREG_EDP_3P3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+
+ gpio = <&tlmm 70 GPIO_ACTIVE_HIGH>;
+ enable-active-high;
+
+ pinctrl-0 = <&edp_reg_en>;
+ pinctrl-names = "default";
+
+ regulator-always-on;
+ regulator-boot-on;
+ };
};
&apps_rsc {
@@ -383,17 +401,170 @@ vreg_l3j_0p8: ldo3 {
};
};
+&mdss {
+ status = "okay";
+};
+
+&mdss_dp3 {
+ compatible = "qcom,x1e80100-dp";
+ /delete-property/ #sound-dai-cells;
+
+ data-lanes = <0 1 2 3>;
+
+ status = "okay";
+
+ aux-bus {
+ panel {
+ compatible = "edp-panel";
+ power-supply = <&vreg_edp_3p3>;
+
+ port {
+ edp_panel_in: endpoint {
+ remote-endpoint = <&mdss_dp3_out>;
+ };
+ };
+ };
+ };
+
+ ports {
+ port@1 {
+ reg = <1>;
+ mdss_dp3_out: endpoint {
+ remote-endpoint = <&edp_panel_in>;
+ };
+ };
+ };
+};
+
+&mdss_dp3_phy {
+ vdda-phy-supply = <&vreg_l3j_0p8>;
+ vdda-pll-supply = <&vreg_l2j_1p2>;
+
+ status = "okay";
+};
+
+&pcie4 {
+ status = "okay";
+};
+
+&pcie4_phy {
+ vdda-phy-supply = <&vreg_l3j_0p8>;
+ vdda-pll-supply = <&vreg_l3e_1p2>;
+
+ status = "okay";
+};
+
+&pcie6a {
+ status = "okay";
+};
+
+&pcie6a_phy {
+ vdda-phy-supply = <&vreg_l3j_0p8>;
+ vdda-pll-supply = <&vreg_l2j_1p2>;
+
+ status = "okay";
+};
+
+&qupv3_0 {
+ status = "okay";
+};
+
+&qupv3_1 {
+ status = "okay";
+};
+
&qupv3_2 {
status = "okay";
};
+&remoteproc_adsp {
+ firmware-name = "qcom/x1e80100/adsp.mbn",
+ "qcom/x1e80100/adsp_dtb.mbn";
+
+ status = "okay";
+};
+
+&remoteproc_cdsp {
+ firmware-name = "qcom/x1e80100/cdsp.mbn",
+ "qcom/x1e80100/cdsp_dtb.mbn";
+
+ status = "okay";
+};
+
&tlmm {
gpio-reserved-ranges = <33 3>, /* Unused */
<44 4>, /* SPI (TPM) */
<238 1>; /* UFS Reset */
+
+ edp_reg_en: edp-reg-en-state {
+ pins = "gpio70";
+ function = "gpio";
+ drive-strength = <16>;
+ bias-disable;
+ };
};
&uart21 {
compatible = "qcom,geni-debug-uart";
status = "okay";
};
+
+&usb_1_ss0_hsphy {
+ vdd-supply = <&vreg_l2e_0p8>;
+ vdda12-supply = <&vreg_l3e_1p2>;
+
+ status = "okay";
+};
+
+&usb_1_ss0_qmpphy {
+ status = "okay";
+};
+
+&usb_1_ss0 {
+ status = "okay";
+};
+
+&usb_1_ss0_dwc3 {
+ dr_mode = "host";
+ usb-role-switch;
+};
+
+&usb_1_ss1_hsphy {
+ vdd-supply = <&vreg_l2e_0p8>;
+ vdda12-supply = <&vreg_l3e_1p2>;
+
+ status = "okay";
+};
+
+&usb_1_ss1_qmpphy {
+ status = "okay";
+};
+
+&usb_1_ss1 {
+ status = "okay";
+};
+
+&usb_1_ss1_dwc3 {
+ dr_mode = "host";
+ usb-role-switch;
+};
+
+&usb_1_ss2_hsphy {
+ vdd-supply = <&vreg_l2e_0p8>;
+ vdda12-supply = <&vreg_l3e_1p2>;
+
+ status = "okay";
+};
+
+&usb_1_ss2_qmpphy {
+ status = "okay";
+};
+
+&usb_1_ss2 {
+ status = "okay";
+};
+
+&usb_1_ss2_dwc3 {
+ dr_mode = "host";
+ usb-role-switch;
+};
--
2.34.1
^ permalink raw reply related [flat|nested] 14+ messages in thread* [PATCH v6 11/11] arm64: dts: qcom: x1e80100-qcp: Fix supplies for LDOs 3E and 2J
2024-01-29 12:45 [PATCH v6 00/11] arm64: dts: qcom: Add more support to X1E80100 base dtsi, CRD and QCP boards Abel Vesa
` (9 preceding siblings ...)
2024-01-29 12:45 ` [PATCH v6 10/11] arm64: dts: qcom: x1e80100-qcp: " Abel Vesa
@ 2024-01-29 12:45 ` Abel Vesa
2024-02-07 4:46 ` [PATCH v6 00/11] arm64: dts: qcom: Add more support to X1E80100 base dtsi, CRD and QCP boards Bjorn Andersson
11 siblings, 0 replies; 14+ messages in thread
From: Abel Vesa @ 2024-01-29 12:45 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Konrad Dybcio, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Sibi Sankar, Rajendra Nayak
Cc: linux-arm-msm, devicetree, linux-kernel, Abel Vesa
The LDOs 3E and 2J are actually supplied by SMPS 5J. Fix accordingly.
Fixes: af16b00578a7 ("arm64: dts: qcom: Add base X1E80100 dtsi and the QCP dts")
Acked-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
---
arch/arm64/boot/dts/qcom/x1e80100-qcp.dts | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/x1e80100-qcp.dts b/arch/arm64/boot/dts/qcom/x1e80100-qcp.dts
index 8dbf6d0eaac3..e76d29053d79 100644
--- a/arch/arm64/boot/dts/qcom/x1e80100-qcp.dts
+++ b/arch/arm64/boot/dts/qcom/x1e80100-qcp.dts
@@ -261,7 +261,7 @@ regulators-3 {
qcom,pmic-id = "e";
vdd-l2-supply = <&vreg_s1f_0p7>;
- vdd-l3-supply = <&vph_pwr>;
+ vdd-l3-supply = <&vreg_s5j_1p2>;
vreg_l2e_0p8: ldo2 {
regulator-name = "vreg_l2e_0p8";
@@ -367,7 +367,7 @@ regulators-7 {
qcom,pmic-id = "j";
vdd-l1-supply = <&vreg_s1f_0p7>;
- vdd-l2-supply = <&vph_pwr>;
+ vdd-l2-supply = <&vreg_s5j_1p2>;
vdd-l3-supply = <&vreg_s1f_0p7>;
vdd-s5-supply = <&vph_pwr>;
--
2.34.1
^ permalink raw reply related [flat|nested] 14+ messages in thread* Re: [PATCH v6 00/11] arm64: dts: qcom: Add more support to X1E80100 base dtsi, CRD and QCP boards
2024-01-29 12:45 [PATCH v6 00/11] arm64: dts: qcom: Add more support to X1E80100 base dtsi, CRD and QCP boards Abel Vesa
` (10 preceding siblings ...)
2024-01-29 12:45 ` [PATCH v6 11/11] arm64: dts: qcom: x1e80100-qcp: Fix supplies for LDOs 3E and 2J Abel Vesa
@ 2024-02-07 4:46 ` Bjorn Andersson
11 siblings, 0 replies; 14+ messages in thread
From: Bjorn Andersson @ 2024-02-07 4:46 UTC (permalink / raw)
To: Andy Gross, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Sibi Sankar, Rajendra Nayak, Abel Vesa
Cc: linux-arm-msm, devicetree, linux-kernel
On Mon, 29 Jan 2024 14:45:32 +0200, Abel Vesa wrote:
> This patchset adds every node necessary for both the CRD and QCP to boot
> with PCIe, USB and embedded DisplayPort.
>
> This patchset depends on the Disp CC and TCSR CC bindings:
> https://lore.kernel.org/all/20240129-x1e80100-clock-controllers-v3-0-d96dacfed104@linaro.org/
>
>
> [...]
Applied, thanks!
[01/11] arm64: dts: qcom: x1e80100: Add IPCC node
commit: 6a07a4f3f509c370c4f2644c2f576d1e8029354c
[02/11] arm64: dts: qcom: x1e80100: Add SMP2P nodes
commit: 0b6ae7364b1133f55eec027e358eec09d3bdc2ff
[03/11] arm64: dts: qcom: x1e80100: Add QMP AOSS node
commit: 2661646f5934c9e6a4067ac325ef023eef611423
[04/11] arm64: dts: qcom: x1e80100: Add ADSP/CDSP remoteproc nodes
commit: 5f2a9cd4b1042ade3824cfe324aa02a3c17430a8
[05/11] arm64: dts: qcom: x1e80100: Add TCSR node
commit: 8b6e2bf94b278c69746358425daae2a75041f7dc
[06/11] arm64: dts: qcom: x1e80100: Add USB nodes
commit: 4af46b7bd66fa3ad9bd87e2ded26599d11562d52
[07/11] arm64: dts: qcom: x1e80100: Add PCIe nodes
commit: 5eb83fc10289db0c13ceaea601151883c0da43f4
[08/11] arm64: dts: qcom: x1e80100: Add display nodes
commit: 1940c25eaa63f65942e6149715e17a61438e2162
[09/11] arm64: dts: qcom: x1e80100-crd: Enable more support
commit: d7e03cce0400cb42d79088a3bb0a59f63bdf50b3
[10/11] arm64: dts: qcom: x1e80100-qcp: Enable more support
commit: f9a9c11471da32133ea6ee8763f932b91018e256
[11/11] arm64: dts: qcom: x1e80100-qcp: Fix supplies for LDOs 3E and 2J
commit: 7eac281cbedbd71d777eabca3a52d97983c61692
Best regards,
--
Bjorn Andersson <andersson@kernel.org>
^ permalink raw reply [flat|nested] 14+ messages in thread