Linux ARM-MSM sub-architecture
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From: Will Deacon <will@kernel.org>
To: Rob Clark <robdclark@gmail.com>
Cc: iommu@lists.linux.dev, linux-arm-msm@vger.kernel.org,
	Robin Murphy <robin.murphy@arm.com>,
	Rob Clark <robdclark@chromium.org>,
	Joerg Roedel <joro@8bytes.org>, Jason Gunthorpe <jgg@ziepe.ca>,
	Steven Price <steven.price@arm.com>,
	Boris Brezillon <boris.brezillon@collabora.com>,
	Kevin Tian <kevin.tian@intel.com>,
	Joao Martins <joao.m.martins@oracle.com>,
	"moderated list:ARM SMMU DRIVERS"
	<linux-arm-kernel@lists.infradead.org>,
	open list <linux-kernel@vger.kernel.org>
Subject: Re: [PATCH v5 1/2] iommu/io-pgtable-arm: Add way to debug pgtable walk
Date: Wed, 3 Jul 2024 16:02:05 +0100	[thread overview]
Message-ID: <20240703150205.GA6012@willie-the-truck> (raw)
In-Reply-To: <20240626204033.255813-2-robdclark@gmail.com>

Hi Rob,

On Wed, Jun 26, 2024 at 01:40:26PM -0700, Rob Clark wrote:
> From: Rob Clark <robdclark@chromium.org>
> 
> Add an io-pgtable method to walk the pgtable returning the raw PTEs that
> would be traversed for a given iova access.
> 
> Signed-off-by: Rob Clark <robdclark@chromium.org>
> ---
>  drivers/iommu/io-pgtable-arm.c | 34 +++++++++++++++++++++++++---------
>  include/linux/io-pgtable.h     | 16 ++++++++++++++++
>  2 files changed, 41 insertions(+), 9 deletions(-)

Non-technical question, but with patch 2/2 being drm-specific, how do
you plan to get this merged this once it's finalised? I can take this
part via the IOMMU tree?

> +static phys_addr_t arm_lpae_iova_to_phys(struct io_pgtable_ops *ops,
> +					 unsigned long iova)
> +{
> +	struct arm_lpae_io_pgtable *data = io_pgtable_ops_to_data(ops);
> +	struct io_pgtable_walk_data wd = {};
> +	int ret, lvl;
> +
> +	ret = arm_lpae_pgtable_walk(ops, iova, &wd);
> +	if (ret)
> +		return 0;
> +
> +	lvl = wd.level + data->start_level;

nit, but the level is architectural so I think we should initialise
wd.level to data->start_level instead.

>  
> -found_translation:
>  	iova &= (ARM_LPAE_BLOCK_SIZE(lvl, data) - 1);
> -	return iopte_to_paddr(pte, data) | iova;
> +	return iopte_to_paddr(wd.ptes[wd.level - 1], data) | iova;
>  }
>  
>  static void arm_lpae_restrict_pgsizes(struct io_pgtable_cfg *cfg)
> @@ -804,6 +819,7 @@ arm_lpae_alloc_pgtable(struct io_pgtable_cfg *cfg)
>  		.map_pages	= arm_lpae_map_pages,
>  		.unmap_pages	= arm_lpae_unmap_pages,
>  		.iova_to_phys	= arm_lpae_iova_to_phys,
> +		.pgtable_walk	= arm_lpae_pgtable_walk,
>  	};
>  
>  	return data;
> diff --git a/include/linux/io-pgtable.h b/include/linux/io-pgtable.h
> index 86cf1f7ae389..4d696724c7da 100644
> --- a/include/linux/io-pgtable.h
> +++ b/include/linux/io-pgtable.h
> @@ -171,12 +171,26 @@ struct io_pgtable_cfg {
>  	};
>  };
>  
> +/**
> + * struct io_pgtable_walk_data - information from a pgtable walk
> + *
> + * @ptes:     The recorded PTE values from the walk
> + * @level:    The level of the last PTE
> + *
> + * @level also specifies the last valid index in @ptes
> + */
> +struct io_pgtable_walk_data {
> +	u64 ptes[4];
> +	int level;
> +};

I wonder if we can do better than hardcoding the '4' here? I wouldn't be
surprised if this doesn't work, but could we do something along the
lines of:

struct io_pgtable_walk_data {
	int level;
	int num_levels;
	u64 ptes[] __counted_by(num_levels);
};

and then have the Arm (LPAE)-specific code wrap that in a private
structure:

struct arm_lpae_io_pgtable_walk_data {
	struct io_pgtable_walk_data data;
	u64 ptes[ARM_LPAE_MAX_LEVELS];
};

which is used by the walker?

Will

  reply	other threads:[~2024-07-03 15:02 UTC|newest]

Thread overview: 6+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-06-26 20:40 [PATCH v5 0/2] io-pgtable-arm + drm/msm: Extend iova fault debugging Rob Clark
2024-06-26 20:40 ` [PATCH v5 1/2] iommu/io-pgtable-arm: Add way to debug pgtable walk Rob Clark
2024-07-03 15:02   ` Will Deacon [this message]
2024-07-03 16:18     ` Rob Clark
2024-07-09 18:20       ` Jason Gunthorpe
2024-06-26 20:40 ` [PATCH v5 2/2] drm/msm: Extend gpu devcore dumps with pgtbl info Rob Clark

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