Linux ARM-MSM sub-architecture
 help / color / mirror / Atom feed
From: Nathan Chancellor <nathan@kernel.org>
To: Sibi Sankar <quic_sibis@quicinc.com>
Cc: sudeep.holla@arm.com, cristian.marussi@arm.com,
	andersson@kernel.org, konrad.dybcio@linaro.org,
	jassisinghbrar@gmail.com, robh+dt@kernel.org,
	krzysztof.kozlowski+dt@linaro.org, dmitry.baryshkov@linaro.org,
	linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org,
	devicetree@vger.kernel.org, quic_rgottimu@quicinc.com,
	quic_kshivnan@quicinc.com, conor+dt@kernel.org,
	quic_nkela@quicinc.com, quic_psodagud@quicinc.com,
	abel.vesa@linaro.org
Subject: Re: [PATCH V6 2/5] mailbox: Add support for QTI CPUCP mailbox controller
Date: Sun, 14 Jul 2024 20:14:51 -0700	[thread overview]
Message-ID: <20240715031451.GA2940276@thelio-3990X> (raw)
In-Reply-To: <20240612124056.39230-3-quic_sibis@quicinc.com>

Hi Sibi,

On Wed, Jun 12, 2024 at 06:10:53PM +0530, Sibi Sankar wrote:
> Add support for CPUSS Control Processor (CPUCP) mailbox controller,
> this driver enables communication between AP and CPUCP by acting as
> a doorbell between them.
> 
> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> Signed-off-by: Sibi Sankar <quic_sibis@quicinc.com>
> ---
> 
> v5:
> * Fix build error reported by kernel test robot by adding 64BIT requirement
>   to COMPILE_TEST
...
> +config QCOM_CPUCP_MBOX
> +	tristate "Qualcomm Technologies, Inc. CPUCP mailbox driver"
> +	depends on ARCH_QCOM || (COMPILE_TEST && 64BIT)

This doesn't work, ARCH=arm allmodconfig is still broken with:

  drivers/mailbox/qcom-cpucp-mbox.c: In function 'qcom_cpucp_mbox_irq_fn':
  drivers/mailbox/qcom-cpucp-mbox.c:54:18: error: implicit declaration of function 'readq'; did you mean 'readb'? [-Wimplicit-function-declaration]
     54 |         status = readq(cpucp->rx_base + APSS_CPUCP_RX_MBOX_STAT);
        |                  ^~~~~
        |                  readb
  drivers/mailbox/qcom-cpucp-mbox.c:65:17: error: implicit declaration of function 'writeq'; did you mean 'writel'? [-Wimplicit-function-declaration]
     65 |                 writeq(BIT(i), cpucp->rx_base + APSS_CPUCP_RX_MBOX_CLEAR);
        |                 ^~~~~~
        |                 writel

because there is ARCH_QCOM for that architecture as well.

You could resolve this by just including either io-64-nonatomic-hi-lo.h
or io-64-nonatomic-lo-hi.h or shuffling the dependencies to require
64BIT unconditionally:

diff --git a/drivers/mailbox/Kconfig b/drivers/mailbox/Kconfig
index d1f6c758b5e8..8d46b76c23fd 100644
--- a/drivers/mailbox/Kconfig
+++ b/drivers/mailbox/Kconfig
@@ -278,7 +278,7 @@ config SPRD_MBOX
 
 config QCOM_CPUCP_MBOX
 	tristate "Qualcomm Technologies, Inc. CPUCP mailbox driver"
-	depends on ARCH_QCOM || (COMPILE_TEST && 64BIT)
+	depends on 64BIT && (ARCH_QCOM || COMPILE_TEST)
 	help
 	  Qualcomm Technologies, Inc. CPUSS Control Processor (CPUCP) mailbox
 	  controller driver enables communication between AP and CPUCP. Say

Cheers,
Nathan

  parent reply	other threads:[~2024-07-15  3:14 UTC|newest]

Thread overview: 20+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-06-12 12:40 [PATCH V6 0/5] qcom: x1e80100: Enable CPUFreq Sibi Sankar
2024-06-12 12:40 ` [PATCH V6 1/5] dt-bindings: mailbox: qcom: Add CPUCP mailbox controller bindings Sibi Sankar
2024-06-12 12:40 ` [PATCH V6 2/5] mailbox: Add support for QTI CPUCP mailbox controller Sibi Sankar
2024-06-26  3:32   ` Bjorn Andersson
2024-06-26  9:43   ` Konrad Dybcio
2024-07-15  3:14   ` Nathan Chancellor [this message]
2024-06-12 12:40 ` [PATCH V6 3/5] arm64: dts: qcom: x1e80100: Resize GIC Redistributor register region Sibi Sankar
2024-06-12 12:40 ` [PATCH V6 4/5] arm64: dts: qcom: x1e80100: Add cpucp mailbox and sram nodes Sibi Sankar
2024-06-12 12:40 ` [PATCH V6 5/5] arm64: dts: qcom: x1e80100: Enable cpufreq Sibi Sankar
2024-07-02 15:55   ` Johan Hovold
2024-07-02 19:59     ` Sibi Sankar
2024-07-02 20:13       ` Nikunj Kela
2024-07-03 11:23         ` Sibi Sankar
2024-07-03 14:05           ` Nikunj Kela
2024-07-04 10:22             ` Sibi Sankar
2024-07-09  9:13       ` Johan Hovold
2024-07-09  9:39         ` Konrad Dybcio
2024-07-16 10:45   ` Konrad Dybcio
2024-07-22 12:12     ` Konrad Dybcio
2024-10-16 20:38 ` (subset) [PATCH V6 0/5] qcom: x1e80100: Enable CPUFreq Bjorn Andersson

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=20240715031451.GA2940276@thelio-3990X \
    --to=nathan@kernel.org \
    --cc=abel.vesa@linaro.org \
    --cc=andersson@kernel.org \
    --cc=conor+dt@kernel.org \
    --cc=cristian.marussi@arm.com \
    --cc=devicetree@vger.kernel.org \
    --cc=dmitry.baryshkov@linaro.org \
    --cc=jassisinghbrar@gmail.com \
    --cc=konrad.dybcio@linaro.org \
    --cc=krzysztof.kozlowski+dt@linaro.org \
    --cc=linux-arm-msm@vger.kernel.org \
    --cc=linux-kernel@vger.kernel.org \
    --cc=quic_kshivnan@quicinc.com \
    --cc=quic_nkela@quicinc.com \
    --cc=quic_psodagud@quicinc.com \
    --cc=quic_rgottimu@quicinc.com \
    --cc=quic_sibis@quicinc.com \
    --cc=robh+dt@kernel.org \
    --cc=sudeep.holla@arm.com \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox