From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BC05E1E0B8D; Wed, 25 Sep 2024 12:03:25 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1727265805; cv=none; b=TT9a/cy3r5zB1AJ5YfpvpQAEBCLs/Do2yYJd+kb8OrA1SgQh87ITvOXl05VM1+LVW1VTOQ8Jzt617YKt4o/Z6NZBenhVrBb6Q7MGFhlyN3WSoo62UZJiCuwDWDlVfunG6rOhJ0T6+T4ys4xP4CPEjIJlKzbeT/dzxpvGQt0u7j8= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1727265805; c=relaxed/simple; bh=DdOAZIMYSHY1pVfhyV0TUDcZfM90uA5dTndwNjWxsas=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=p4nVLbObhmozth5Hd8dBmiu67HoglKeP6qIKdGEk/KyyT35wJJu1OhxKFIGJLypZ7GI2rZcp99S41pV6KnEbWoZWjKSxgoXTdR0siYnWpp/3zdgTtGw+u/46GM34eHEwRvx2kj8XfZ7A0lMFcTWX6f5hAIZJd/A6eYrfwMZmT2c= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=NO+nHQIH; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="NO+nHQIH" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 5730EC4CEC7; Wed, 25 Sep 2024 12:03:23 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1727265805; bh=DdOAZIMYSHY1pVfhyV0TUDcZfM90uA5dTndwNjWxsas=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=NO+nHQIH4fbMmclbY0Kl4OxOk16Yh7F3CkVyi8mpJPd4DAlgHdwXR+xUT5vwN+85/ m6/+bYSZUtPC0JFxEEA6aeYDpKjfEKC4P1rxtEqMtP++t9Y2TMvZrOgg6JNsCyePPs MyCaiM6cSIVcA04eH6rwfupqj9MnFwiFgUhKiQ9Tv+acmvdDykeYJGi9Pc21WgD91q HSgCJifVnay5knKILSBnCKovqlkDuHtQVU/V4YLOmJCaHrp2ZzYvdjQu9VZZyfZKfE n3Q8wn5Y0lKoKlYZvPrcHSsh5lVQnmA0SnrX67mMXkDp02nc+icjTJNiRN7MCid1ai ZuuLGmggK9gCg== From: Sasha Levin To: linux-kernel@vger.kernel.org, stable@vger.kernel.org Cc: Marc Gonzalez , Caleb Connolly , Bjorn Andersson , Will Deacon , Sasha Levin , robdclark@gmail.com, joro@8bytes.org, iommu@lists.linux.dev, linux-arm-msm@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH AUTOSEL 6.10 103/197] iommu/arm-smmu-qcom: hide last LPASS SMMU context bank from linux Date: Wed, 25 Sep 2024 07:52:02 -0400 Message-ID: <20240925115823.1303019-103-sashal@kernel.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240925115823.1303019-1-sashal@kernel.org> References: <20240925115823.1303019-1-sashal@kernel.org> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-stable: review X-Patchwork-Hint: Ignore X-stable-base: Linux 6.10.11 Content-Transfer-Encoding: 8bit From: Marc Gonzalez [ Upstream commit 3a8990b8a778219327c5f8ecf10b5d81377b925a ] On qcom msm8998, writing to the last context bank of lpass_q6_smmu (base address 0x05100000) produces a system freeze & reboot. The hardware/hypervisor reports 13 context banks for the LPASS SMMU on msm8998, but only the first 12 are accessible... Override the number of context banks [ 2.546101] arm-smmu 5100000.iommu: probing hardware configuration... [ 2.552439] arm-smmu 5100000.iommu: SMMUv2 with: [ 2.558945] arm-smmu 5100000.iommu: stage 1 translation [ 2.563627] arm-smmu 5100000.iommu: address translation ops [ 2.568923] arm-smmu 5100000.iommu: non-coherent table walk [ 2.574566] arm-smmu 5100000.iommu: (IDR0.CTTW overridden by FW configuration) [ 2.580220] arm-smmu 5100000.iommu: stream matching with 12 register groups [ 2.587263] arm-smmu 5100000.iommu: 13 context banks (0 stage-2 only) [ 2.614447] arm-smmu 5100000.iommu: Supported page sizes: 0x63315000 [ 2.621358] arm-smmu 5100000.iommu: Stage-1: 36-bit VA -> 36-bit IPA [ 2.627772] arm-smmu 5100000.iommu: preserved 0 boot mappings Specifically, the crashes occur here: qsmmu->bypass_cbndx = smmu->num_context_banks - 1; arm_smmu_cb_write(smmu, qsmmu->bypass_cbndx, ARM_SMMU_CB_SCTLR, 0); and here: arm_smmu_write_context_bank(smmu, i); arm_smmu_cb_write(smmu, i, ARM_SMMU_CB_FSR, ARM_SMMU_CB_FSR_FAULT); It is likely that FW reserves the last context bank for its own use, thus a simple work-around is: DON'T USE IT in Linux. If we decrease the number of context banks, last one will be "hidden". Signed-off-by: Marc Gonzalez Reviewed-by: Caleb Connolly Reviewed-by: Bjorn Andersson Link: https://lore.kernel.org/r/20240820-smmu-v3-1-2f71483b00ec@freebox.fr Signed-off-by: Will Deacon Signed-off-by: Sasha Levin --- drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c index 13f3e2efb2ccb..8bc71449aabc3 100644 --- a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c +++ b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c @@ -282,6 +282,13 @@ static int qcom_smmu_cfg_probe(struct arm_smmu_device *smmu) u32 smr; int i; + /* + * MSM8998 LPASS SMMU reports 13 context banks, but accessing + * the last context bank crashes the system. + */ + if (of_device_is_compatible(smmu->dev->of_node, "qcom,msm8998-smmu-v2") && smmu->num_context_banks == 13) + smmu->num_context_banks = 12; + /* * Some platforms support more than the Arm SMMU architected maximum of * 128 stream matching groups. For unknown reasons, the additional -- 2.43.0