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Thu, 31 Oct 2024 20:29:02 +0000 (GMT) Received: from nasanex01b.na.qualcomm.com (nasanex01b.na.qualcomm.com [10.46.141.250]) by NASANPPMTA04.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 49VKT1Ui030753 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 31 Oct 2024 20:29:01 GMT Received: from hu-eberman-lv.qualcomm.com (10.49.16.6) by nasanex01b.na.qualcomm.com (10.46.141.250) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Thu, 31 Oct 2024 13:28:58 -0700 Date: Thu, 31 Oct 2024 13:28:58 -0700 From: Elliot Berman To: Dmitry Baryshkov CC: Konrad Dybcio , Tingguo Cheng , , , , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , , , Subject: Re: [PATCH v3 2/2] arm64: dts: qcom: qcs615-ride: Enable PMIC peripherals Message-ID: <20241031115300700-0700.eberman@hu-eberman-lv.qualcomm.com> References: <20241028-adds-spmi-pmic-peripherals-for-qcs615-v3-0-f0778572ee41@quicinc.com> <20241028-adds-spmi-pmic-peripherals-for-qcs615-v3-2-f0778572ee41@quicinc.com> <38cceae8-5203-4057-bd8b-f20fe3656474@quicinc.com> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Disposition: inline In-Reply-To: X-ClientProxiedBy: nalasex01a.na.qualcomm.com (10.47.209.196) To nasanex01b.na.qualcomm.com (10.46.141.250) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: Ug-cRTnA1zVwyId4jz-94oENzCbvOI7s X-Proofpoint-ORIG-GUID: Ug-cRTnA1zVwyId4jz-94oENzCbvOI7s X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.60.29 definitions=2024-09-06_09,2024-09-06_01,2024-09-02_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxscore=0 suspectscore=0 adultscore=0 spamscore=0 phishscore=0 mlxlogscore=999 malwarescore=0 bulkscore=0 clxscore=1015 lowpriorityscore=0 impostorscore=0 priorityscore=1501 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2409260000 definitions=main-2410310155 On Mon, Oct 28, 2024 at 03:14:49PM +0200, Dmitry Baryshkov wrote: > On Mon, Oct 28, 2024 at 02:09:45PM +0100, Konrad Dybcio wrote: > > On 28.10.2024 10:41 AM, Dmitry Baryshkov wrote: > > > On Mon, 28 Oct 2024 at 10:40, Tingguo Cheng wrote: > > >> On 10/28/2024 4:23 PM, Dmitry Baryshkov wrote: > > >>> On Mon, Oct 28, 2024 at 04:03:25PM +0800, Tingguo Cheng wrote: > > >>>> Enable PMIC and PMIC peripherals for qcs615-ride board. > > >>>> > > >>>> Signed-off-by: Tingguo Cheng > > >>>> --- > > >>>> arch/arm64/boot/dts/qcom/qcs615-ride.dts | 15 +++++++++++++++ > > >>>> 1 file changed, 15 insertions(+) > > >>>> > > >>>> diff --git a/arch/arm64/boot/dts/qcom/qcs615-ride.dts b/arch/arm64/boot/dts/qcom/qcs615-ride.dts > > >>>> index ee6cab3924a6d71f29934a8debba3a832882abdd..37358f080827bbe4484c14c5f159e813810c2119 100644 > > >>>> --- a/arch/arm64/boot/dts/qcom/qcs615-ride.dts > > >>>> +++ b/arch/arm64/boot/dts/qcom/qcs615-ride.dts > > >>>> @@ -6,6 +6,7 @@ > > >>>> > > >>>> #include > > >>>> #include "qcs615.dtsi" > > >>>> +#include "pm8150.dtsi" > > >>>> / { > > >>>> model = "Qualcomm Technologies, Inc. QCS615 Ride"; > > >>>> compatible = "qcom,qcs615-ride", "qcom,qcs615"; > > >>>> @@ -210,6 +211,20 @@ &rpmhcc { > > >>>> clocks = <&xo_board_clk>; > > >>>> }; > > >>>> > > >>>> +&pon { > > >>>> + /delete-property/ mode-bootloader; > > >>>> + /delete-property/ mode-recovery; > > >>> > > >>> Why? > > >> Because boot modes will be supported on PSCI module from another patch, > > >> reboot-modes are required to remove from PMIC side. I don't know why "required to remove" is here. We *could* continue to program the SDAM from Linux. That being said, I don't know that the firmware/bootloader from the QCS615 Ride has the concept of "reboot to recovery" since it's not an Android ecosystem. I'd let Tingguo comment on it. > > > > Do we know whether the PSCI call does the same thing under the hood? > > It might be writing to the SDAM. For example, SAR2130P also uses PM8150 > and, if I'm not mistaken, SDAM for reboot mode. > Yes, PSCI does the same thing under the hood. What is going here is that we have introduced the SYSTEM_RESET2 vendor resets in some firmwares which run on boards that use PM8150. Based on context here (IOW: I might be a little wrong on the details), I guess QCS615 Ride is being added to Qualcomm Linux stack, which has newer firmware that supports using the SYSTEM_RESET2 vendor resets. IMO, we should move the mode-bootloader/mode-recovery properties out of pm8150.dtsi and into the applicable board.dts. As Bjorn mentioned, the interpretation of the cookie values is specific to the board's firmware, not the the pmic*. Tingguo, can you submit patches to do that? Regards, Elliot *: In general, the cookie values are consistent. Some values are only applicable on automotive board or mobile board though (or IOT).