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AJvYcCXdu0/ksccY0W4ZZPrwGU6wxVIlBvxFOwQoQgfkgc/lShLGtJsuwZvZX3BFCGOS+/tMwXGYMwWHKNuoIZF8@vger.kernel.org X-Gm-Message-State: AOJu0YyMvRGiP67pcKQ/YnMq+XO9W+p7KCfRgjm0Tg7brOMIgqm3ITrz 8jz/kIn9lVkeNVR0e7e7y+y8xJ8BS757xBJwYgtup6lQVI2Tpf3pcHJ94VzhJw== X-Google-Smtp-Source: AGHT+IG7g6V+GncMskJmi31sl11CTfqGguPy66PiWd2w8mZ74T+uGZMa+rDBHSDEHgff9qIU3c4ZGw== X-Received: by 2002:a05:6a00:2309:b0:71e:1722:d019 with SMTP id d2e1a72fcca58-72476e7b88emr2343975b3a.22.1731653218397; Thu, 14 Nov 2024 22:46:58 -0800 (PST) Received: from thinkpad ([117.193.208.47]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-724770eef26sm661670b3a.33.2024.11.14.22.46.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 14 Nov 2024 22:46:58 -0800 (PST) Date: Fri, 15 Nov 2024 12:16:48 +0530 From: Manivannan Sadhasivam To: Konrad Dybcio Cc: Ziyue Zhang , vkoul@kernel.org, kishon@kernel.org, robh+dt@kernel.org, bhelgaas@google.com, kw@linux.com, lpieralisi@kernel.org, quic_qianyu@quicinc.com, conor+dt@kernel.org, neil.armstrong@linaro.org, andersson@kernel.org, konradybcio@kernel.org, quic_shashim@quicinc.com, quic_kaushalk@quicinc.com, quic_tdas@quicinc.com, quic_tingweiz@quicinc.com, quic_aiquny@quicinc.com, kernel@quicinc.com, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org Subject: Re: [PATCH 4/5] arm64: dts: qcom: qcs8300: enable pcie0 for QCS8300 Message-ID: <20241115064648.7ugkijhsobc4gcda@thinkpad> References: <20241114095409.2682558-1-quic_ziyuzhan@quicinc.com> <20241114095409.2682558-5-quic_ziyuzhan@quicinc.com> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: On Thu, Nov 14, 2024 at 02:02:48PM +0100, Konrad Dybcio wrote: [...] > > + > > + pcieport0: pcie@0 { > > + device_type = "pci"; > > + reg = <0x0 0x0 0x0 0x0 0x0>; > > + #address-cells = <3>; > > + #size-cells = <2>; > > + ranges; > > + bus-range = <0x01 0xff>; > > + }; > > Are you going to use this? If not, please drop > Absolutely not! This describes the IP that is present in the SoC and that IP is being used. You can however keep it disabled in the soc.dtsi and enable in board dts when PCIe controller is enabled. Moreover, I plan to move the slot supplies to this node soon, so it will be used mostly. - Mani -- மணிவண்ணன் சதாசிவம்