From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 044CB2066FB; Wed, 4 Dec 2024 17:00:28 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1733331630; cv=none; b=f6mf0OzSnSs0RXl+5Ibh7MAze2VV+5NXtNki4oXIEQAdADAgY0H5UyHOsHbRShoIbKn4ZSCGE/7Uel7N87DnSW1f1xIMDlT1+0cFT5tvzWMMXqegLz/hHAGzMxIR1aTXavWCAAg85rlrvmTKMyHuKnCPY+I/5M4RuCtCopYQscM= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1733331630; c=relaxed/simple; bh=xwgudsxGIo94rntV7Ii8BArBcCp9b9lcNfpvcnRWsHw=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=PIIzsWJzIasPofNWOT+/CWW/gZ7hgZMkRciZMHYKggl1Z0PqusgL/mOMO1J66PHcLsNfCnmQhKjqPyb7Qv6/AVP4SCwAtuOGuvtfY/08EAz0hqr+o5HmS8oqcQ7+0tL08gXAznczaqlzQLyjJ3lLF8YyoBnjMpD1/VaZxKrHShI= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=RIaKRkWC; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="RIaKRkWC" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 4F7F9C4CECD; Wed, 4 Dec 2024 17:00:27 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1733331628; bh=xwgudsxGIo94rntV7Ii8BArBcCp9b9lcNfpvcnRWsHw=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=RIaKRkWCLjRWY9z8WkllYTHZibomDeU08eBWiywhPVUs+OWi3v/il5FgnpUUQxDid hslJp83bzOFII0orcnd1fIpFXib8wV3ZlRIhF+uzph/hoxE0p3zR4hOO7Bc70TDQvd IZTKbnpvmNYCVpFK7DN625TYB15Wi7PVNfDTncFuvInk7RNyXtMG14Vv/U2ImiYvMN hsl5MqIJdrK170O6TI6QixrPlc5bY0YG/tkP6gkeVqvPkMNAVcczD3nco1U4arN6i/ GuSdrT9YeBuGdIKBHhe2cB2QCC9LpcQtwj72wFzs8GzATFD+Skq9kkLqAjb6tYxwsR 7cLOkGNTaXL7w== From: Sasha Levin To: linux-kernel@vger.kernel.org, stable@vger.kernel.org Cc: Dmitry Baryshkov , Konrad Dybcio , Bjorn Andersson , Sasha Levin , mturquette@baylibre.com, sboyd@kernel.org, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org Subject: [PATCH AUTOSEL 6.11 21/33] clk: qcom: tcsrcc-sm8550: add SAR2130P support Date: Wed, 4 Dec 2024 10:47:34 -0500 Message-ID: <20241204154817.2212455-21-sashal@kernel.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20241204154817.2212455-1-sashal@kernel.org> References: <20241204154817.2212455-1-sashal@kernel.org> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-stable: review X-Patchwork-Hint: Ignore X-stable-base: Linux 6.11.10 Content-Transfer-Encoding: 8bit From: Dmitry Baryshkov [ Upstream commit d2e0a043530b9d6f37a8de8f05e0725667aba0a6 ] The SAR2130P platform has the same TCSR Clock Controller as the SM8550, except for the lack of the UFS clocks. Extend the SM8550 TCSRCC driver to support SAR2130P. Reviewed-by: Konrad Dybcio Signed-off-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20241027-sar2130p-clocks-v5-9-ecad2a1432ba@linaro.org Signed-off-by: Bjorn Andersson Signed-off-by: Sasha Levin --- drivers/clk/qcom/tcsrcc-sm8550.c | 18 ++++++++++++++++-- 1 file changed, 16 insertions(+), 2 deletions(-) diff --git a/drivers/clk/qcom/tcsrcc-sm8550.c b/drivers/clk/qcom/tcsrcc-sm8550.c index e5e8f2e82b949..41d73f92a000a 100644 --- a/drivers/clk/qcom/tcsrcc-sm8550.c +++ b/drivers/clk/qcom/tcsrcc-sm8550.c @@ -129,6 +129,13 @@ static struct clk_branch tcsr_usb3_clkref_en = { }, }; +static struct clk_regmap *tcsr_cc_sar2130p_clocks[] = { + [TCSR_PCIE_0_CLKREF_EN] = &tcsr_pcie_0_clkref_en.clkr, + [TCSR_PCIE_1_CLKREF_EN] = &tcsr_pcie_1_clkref_en.clkr, + [TCSR_USB2_CLKREF_EN] = &tcsr_usb2_clkref_en.clkr, + [TCSR_USB3_CLKREF_EN] = &tcsr_usb3_clkref_en.clkr, +}; + static struct clk_regmap *tcsr_cc_sm8550_clocks[] = { [TCSR_PCIE_0_CLKREF_EN] = &tcsr_pcie_0_clkref_en.clkr, [TCSR_PCIE_1_CLKREF_EN] = &tcsr_pcie_1_clkref_en.clkr, @@ -146,6 +153,12 @@ static const struct regmap_config tcsr_cc_sm8550_regmap_config = { .fast_io = true, }; +static const struct qcom_cc_desc tcsr_cc_sar2130p_desc = { + .config = &tcsr_cc_sm8550_regmap_config, + .clks = tcsr_cc_sar2130p_clocks, + .num_clks = ARRAY_SIZE(tcsr_cc_sar2130p_clocks), +}; + static const struct qcom_cc_desc tcsr_cc_sm8550_desc = { .config = &tcsr_cc_sm8550_regmap_config, .clks = tcsr_cc_sm8550_clocks, @@ -153,7 +166,8 @@ static const struct qcom_cc_desc tcsr_cc_sm8550_desc = { }; static const struct of_device_id tcsr_cc_sm8550_match_table[] = { - { .compatible = "qcom,sm8550-tcsr" }, + { .compatible = "qcom,sar2130p-tcsr", .data = &tcsr_cc_sar2130p_desc }, + { .compatible = "qcom,sm8550-tcsr", .data = &tcsr_cc_sm8550_desc }, { } }; MODULE_DEVICE_TABLE(of, tcsr_cc_sm8550_match_table); @@ -162,7 +176,7 @@ static int tcsr_cc_sm8550_probe(struct platform_device *pdev) { struct regmap *regmap; - regmap = qcom_cc_map(pdev, &tcsr_cc_sm8550_desc); + regmap = qcom_cc_map(pdev, of_device_get_match_data(&pdev->dev)); if (IS_ERR(regmap)) return PTR_ERR(regmap); -- 2.43.0