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X-CSE-ConnectionGUID: 2zltuufAS0GPJ8mc2qFc+Q== X-CSE-MsgGUID: fRMAXE1dQiGH3uD8X5iyfA== X-IronPort-AV: E=McAfee;i="6700,10204,11324"; a="41883734" X-IronPort-AV: E=Sophos;i="6.13,230,1732608000"; d="scan'208";a="41883734" Received: from orviesa002.jf.intel.com ([10.64.159.142]) by orvoesa107.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 Jan 2025 19:48:42 -0800 X-CSE-ConnectionGUID: FcaMMzkpTRiK0gGgdkLT9w== X-CSE-MsgGUID: SIwu+aytSZuzIOueLOhRyQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.13,230,1732608000"; d="scan'208";a="138528984" Received: from lkp-server01.sh.intel.com (HELO d63d4d77d921) ([10.239.97.150]) by orviesa002.jf.intel.com with ESMTP; 23 Jan 2025 19:48:37 -0800 Received: from kbuild by d63d4d77d921 with local (Exim 4.96) (envelope-from ) id 1tbAgM-000c63-2F; Fri, 24 Jan 2025 03:48:34 +0000 Date: Fri, 24 Jan 2025 11:48:16 +0800 From: kernel test robot To: Taniya Das , Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Catalin Marinas , Will Deacon Cc: oe-kbuild-all@lists.linux.dev, Ajit Pandey , Imran Shaik , Jagadeesh Kona , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Taniya Das , Dmitry Baryshkov Subject: Re: [PATCH v4 07/10] clk: qcom: gpucc-qcs615: Add QCS615 graphics clock controller driver Message-ID: <202501241339.AZK5Ob8e-lkp@intel.com> References: <20250119-qcs615-mm-v4-clockcontroller-v4-7-5d1bdb5a140c@quicinc.com> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20250119-qcs615-mm-v4-clockcontroller-v4-7-5d1bdb5a140c@quicinc.com> Hi Taniya, kernel test robot noticed the following build warnings: [auto build test WARNING on 0907e7fb35756464aa34c35d6abb02998418164b] url: https://github.com/intel-lab-lkp/linux/commits/Taniya-Das/clk-qcom-clk-alpha-pll-Add-support-for-dynamic-update-for-slewing-PLLs/20250119-182754 base: 0907e7fb35756464aa34c35d6abb02998418164b patch link: https://lore.kernel.org/r/20250119-qcs615-mm-v4-clockcontroller-v4-7-5d1bdb5a140c%40quicinc.com patch subject: [PATCH v4 07/10] clk: qcom: gpucc-qcs615: Add QCS615 graphics clock controller driver config: nios2-randconfig-r111-20250124 (https://download.01.org/0day-ci/archive/20250124/202501241339.AZK5Ob8e-lkp@intel.com/config) compiler: nios2-linux-gcc (GCC) 14.2.0 reproduce: (https://download.01.org/0day-ci/archive/20250124/202501241339.AZK5Ob8e-lkp@intel.com/reproduce) If you fix the issue in a separate patch/commit (i.e. not just a new version of the same patch/commit), kindly add following tags | Reported-by: kernel test robot | Closes: https://lore.kernel.org/oe-kbuild-all/202501241339.AZK5Ob8e-lkp@intel.com/ sparse warnings: (new ones prefixed by >>) >> drivers/clk/qcom/gpucc-qcs615.c:394:15: sparse: sparse: symbol 'gpu_cc_sm6150_hws' was not declared. Should it be static? vim +/gpu_cc_sm6150_hws +394 drivers/clk/qcom/gpucc-qcs615.c 393 > 394 struct clk_hw *gpu_cc_sm6150_hws[] = { 395 [CRC_DIV_PLL0] = &crc_div_pll0.hw, 396 [CRC_DIV_PLL1] = &crc_div_pll1.hw, 397 }; 398 -- 0-DAY CI Kernel Test Service https://github.com/intel/lkp-tests/wiki