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([144.202.86.13]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-b15fa80fa97sm887608a12.51.2025.04.24.03.38.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 24 Apr 2025 03:38:23 -0700 (PDT) From: Pengyu Luo To: jun.nie@linaro.org Cc: airlied@gmail.com, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, marijn.suijten@somainline.org, mitltlatltl@gmail.com, quic_abhinavk@quicinc.com, quic_jesszhan@quicinc.com, robdclark@gmail.com, sean@poorly.run, simona@ffwll.ch Subject: Re: [PATCH v8 00/15] drm/msm/dpu: Support quad pipe with dual-DSI Date: Thu, 24 Apr 2025 18:36:07 +0800 Message-ID: <20250424103608.184295-1-mitltlatltl@gmail.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit On Wed, Apr 23, 2025 at 10:50 AM Jun Nie wrote: > Pengyu Luo 于2025年4月19日周六 02:34写道： > > > > On Mon, 03 Mar 2025 23:14:29 +0800 Jun Nie wrote: > > > 2 or more SSPPs and dual-DSI interface are need for super wide panel. > > > And 4 DSC are preferred for power optimal in this case due to width > > > limitation of SSPP and MDP clock rate constrain. This patch set > > > extends number of pipes to 4 and revise related mixer blending logic > > > to support quad pipe. All these changes depends on the virtual plane > > > feature to split a super wide drm plane horizontally into 2 or more sub > > > clip. Thus DMA of multiple SSPPs can share the effort of fetching the > > > whole drm plane. > > > > > > The first pipe pair co-work with the first mixer pair to cover the left > > > half of screen and 2nd pair of pipes and mixers are for the right half > > > of screen. If a plane is only for the right half of screen, only one > > > or two of pipes in the 2nd pipe pair are valid, and no SSPP or mixer is > > > assinged for invalid pipe. > > > > > > For those panel that does not require quad-pipe, only 1 or 2 pipes in > > > the 1st pipe pair will be used. There is no concept of right half of > > > screen. > > > > > > For legacy non virtual plane mode, the first 1 or 2 pipes are used for > > > the single SSPP and its multi-rect mode. > > > > > > To test bonded DSI on SM8650, the 5 patches for active-CTL improvement > > > are needed: > > > https://gitlab.freedesktop.org/lumag/msm/-/commits/dpu-4k?ref_type=heads > > > > > > > [...] > > > > > base-commit: b44251a8c179381b9f3ed3aa49be04fe1d516903 > > > > Hi, Jun. The display of my sm8650 device requires 4:4:2(lm, dsc, intf) > > topology, I want to test this series, these patches can't be applied to > > the latest linux-next tree, and I can't find the commit id in linux-next > > or msm-next. Where can I fetch the tree? > > > > Best wishes, > > Pengyu > > This is staging patch set. Code clean and formatting is still needed. > > https://gitlab.com/jun.nie/linux/-/tree/sm8650/v6.15-quadpipe-staging?ref_type=heads > Sory, it seems that this repo is private or internal for linaro, it is unavailable in my end. Is it possible to set the repo publicly accessible? BTW, I had tried it with linux-6.14-rc2 as you mentioned in changelog, my display(PPC100HB1-1 binding with TDDI NT36532E) has the flag `BL_UPDATE_DELAY_UNTIL_FIRST_FRAME`, if there is no frame, backlight would refused to turn on. It turns out no frame is sent to display. I checked encoder in debugfs(/sys/kernel/debug/dri/0/encoder-0/status), found all frames underrun. Do you have any idea? Thanks in advance. Best wishes, Pengyu