From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from frasgout.his.huawei.com (frasgout.his.huawei.com [185.176.79.56]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 02C9820CCF4; Thu, 29 May 2025 11:29:54 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.176.79.56 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1748518196; cv=none; b=VeG4YbgZyobEG5Sc1bH42w7kQujUWTMqmmUM6Dv4pyPIRvr+NHmMhlWRE31aug3GjfujoUjUAcIgxwLj1QmsJSn/9qCF3gCQhuqKyEuSb/YRnyBdKMPPX89Qtt5Mz3LFOKBXehj1sutV3xp9gwhjay0ZJKa7PscFSCYhl7Qudu4= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1748518196; c=relaxed/simple; bh=/XTFgQucAxsh2T22QTJl1XSs/Bkg3FT0qfuo/JDH9DY=; h=Date:From:To:CC:Subject:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=NBVBVx59MlOp3zLrbG4LOqSJi7xtDGS3y4sHi7X6iD1njunsUav2NjcCKywFCk8cjBzP1RvhJhjvwBRsILlxay9GjlP1d0yhaQ3ClBifuirBJ7exR6K+cK4usYDbsUA2xjavgX+NDgj8IYv2fW4PfQRgWkoKTnbcn14j7JFikCs= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=huawei.com; spf=pass smtp.mailfrom=huawei.com; arc=none smtp.client-ip=185.176.79.56 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=huawei.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=huawei.com Received: from mail.maildlp.com (unknown [172.18.186.216]) by frasgout.his.huawei.com (SkyGuard) with ESMTP id 4b7PJN5YnVz6L4sw; Thu, 29 May 2025 19:28:36 +0800 (CST) Received: from frapeml500008.china.huawei.com (unknown [7.182.85.71]) by mail.maildlp.com (Postfix) with ESMTPS id 2939F1400CA; Thu, 29 May 2025 19:29:52 +0800 (CST) Received: from localhost (10.203.177.66) by frapeml500008.china.huawei.com (7.182.85.71) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.1.2507.39; Thu, 29 May 2025 13:29:51 +0200 Date: Thu, 29 May 2025 12:29:50 +0100 From: Jonathan Cameron To: Songwei Chai CC: Suzuki K Poulose , Mike Leach , James Clark , "Alexander Shishkin" , Andy Gross , Bjorn Andersson , Rob Herring , Krzysztof Kozlowski , "Conor Dooley" , , , , , Subject: Re: [PATCH v5 3/7] coresight-tgu: Add signal priority support Message-ID: <20250529122950.00001fe6@huawei.com> In-Reply-To: <20250529081949.26493-4-quic_songchai@quicinc.com> References: <20250529081949.26493-1-quic_songchai@quicinc.com> <20250529081949.26493-4-quic_songchai@quicinc.com> X-Mailer: Claws Mail 4.3.0 (GTK 3.24.42; x86_64-w64-mingw32) Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="US-ASCII" Content-Transfer-Encoding: 7bit X-ClientProxiedBy: lhrpeml500001.china.huawei.com (7.191.163.213) To frapeml500008.china.huawei.com (7.182.85.71) On Thu, 29 May 2025 16:19:44 +0800 Songwei Chai wrote: > Like circuit of a Logic analyzer, in TGU, the requirement could be > configured in each step and the trigger will be created once the > requirements are met. Add priority functionality here to sort the > signals into different priorities. The signal which is wanted could > be configured in each step's priority node, the larger number means > the higher priority and the signal with higher priority will be sensed > more preferentially. > > Signed-off-by: Songwei Chai > diff --git a/drivers/hwtracing/coresight/coresight-tgu.h b/drivers/hwtracing/coresight/coresight-tgu.h > index 6c849a2f78fa..f07ead505365 100644 > --- a/drivers/hwtracing/coresight/coresight-tgu.h > +++ b/drivers/hwtracing/coresight/coresight-tgu.h > @@ -13,6 +13,112 @@ > +enum operation_index { > + TGU_PRIORITY0, > + TGU_PRIORITY1, > + TGU_PRIORITY2, > + TGU_PRIORITY3 No blank line. Also convention on anything other than a terminating entry is to leave the trailing , > + > +}; > + > /** > * struct tgu_drvdata - Data structure for a TGU (Trigger Generator Unit) > * @base: Memory-mapped base address of the TGU device > @@ -20,6 +126,9 @@ > * @csdev: Pointer to the associated coresight device > * @spinlock: Spinlock for handling concurrent access > * @enable: Flag indicating whether the TGU device is enabled > + * @value_table: Store given value based on relevant parameters. > + * @max_reg: Maximum number of registers > + * @max_step: Maximum step size > * > * This structure defines the data associated with a TGU device, > * including its base address, device pointers, clock, spinlock for > @@ -32,6 +141,9 @@ struct tgu_drvdata { > struct coresight_device *csdev; > spinlock_t spinlock; > bool enable; > + struct value_table *value_table; > + int max_reg; > + int max_step; Ah. Here some of the bits missing in previous patch that make the description make more sense. Fair enough. > }; > > #endif > >