* [PATCH v2 1/3] drm/msm/adreno: Add speedbin support for X1-85
2025-07-01 16:20 [PATCH v2 0/3] Support for Adreno X1-85 Speedbin along with new OPP levels Akhil P Oommen
@ 2025-07-01 16:20 ` Akhil P Oommen
2025-07-01 16:20 ` [PATCH v2 2/3] dt-bindings: power: qcom,rpmpd: add Turbo L5 corner Akhil P Oommen
` (2 subsequent siblings)
3 siblings, 0 replies; 5+ messages in thread
From: Akhil P Oommen @ 2025-07-01 16:20 UTC (permalink / raw)
To: Rob Clark, Sean Paul, Konrad Dybcio, Dmitry Baryshkov,
Abhinav Kumar, Jessica Zhang, Marijn Suijten, David Airlie,
Simona Vetter, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Bjorn Andersson
Cc: linux-arm-msm, dri-devel, freedreno, linux-kernel, devicetree,
Akhil P Oommen
Add the speedbin table to the X1-85's entry in the catalogue to
enable SKU detection.
Signed-off-by: Akhil P Oommen <akhilpo@oss.qualcomm.com>
---
drivers/gpu/drm/msm/adreno/a6xx_catalog.c | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c
index 7748f92919b883bbcea839a61158ab52e6e4e79d..2fdaaf4372d381c351df92b8dcb21da0fcd02776 100644
--- a/drivers/gpu/drm/msm/adreno/a6xx_catalog.c
+++ b/drivers/gpu/drm/msm/adreno/a6xx_catalog.c
@@ -1442,6 +1442,13 @@ static const struct adreno_info a7xx_gpus[] = {
.gmu_cgc_mode = 0x00020202,
},
.preempt_record_size = 4192 * SZ_1K,
+ .speedbins = ADRENO_SPEEDBINS(
+ { 0, 0 },
+ { 59, 1 },
+ { 7, 2 },
+ { 232, 3 },
+ { 146, 4 },
+ ),
}, {
.chip_ids = ADRENO_CHIP_IDS(0x43051401), /* "C520v2" */
.family = ADRENO_7XX_GEN3,
--
2.48.1
^ permalink raw reply related [flat|nested] 5+ messages in thread* [PATCH v2 2/3] dt-bindings: power: qcom,rpmpd: add Turbo L5 corner
2025-07-01 16:20 [PATCH v2 0/3] Support for Adreno X1-85 Speedbin along with new OPP levels Akhil P Oommen
2025-07-01 16:20 ` [PATCH v2 1/3] drm/msm/adreno: Add speedbin support for X1-85 Akhil P Oommen
@ 2025-07-01 16:20 ` Akhil P Oommen
2025-07-01 16:20 ` [PATCH v2 3/3] arm64: dts: qcom: x1e80100: Update GPU OPP table Akhil P Oommen
2025-07-07 5:24 ` [PATCH v2 0/3] Support for Adreno X1-85 Speedbin along with new OPP levels Jens Glathe
3 siblings, 0 replies; 5+ messages in thread
From: Akhil P Oommen @ 2025-07-01 16:20 UTC (permalink / raw)
To: Rob Clark, Sean Paul, Konrad Dybcio, Dmitry Baryshkov,
Abhinav Kumar, Jessica Zhang, Marijn Suijten, David Airlie,
Simona Vetter, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Bjorn Andersson
Cc: linux-arm-msm, dri-devel, freedreno, linux-kernel, devicetree,
Akhil P Oommen, Krzysztof Kozlowski
Update the RPMH level definitions to include TURBO_L5 corner.
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Akhil P Oommen <akhilpo@oss.qualcomm.com>
---
include/dt-bindings/power/qcom-rpmpd.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/include/dt-bindings/power/qcom-rpmpd.h b/include/dt-bindings/power/qcom-rpmpd.h
index d9b7bac309537cbfd2488e7d4fe21d195c919ef5..f15bcee7c9283e74dc8e6f9b6b6f73c0ced009e4 100644
--- a/include/dt-bindings/power/qcom-rpmpd.h
+++ b/include/dt-bindings/power/qcom-rpmpd.h
@@ -240,6 +240,7 @@
#define RPMH_REGULATOR_LEVEL_TURBO_L2 432
#define RPMH_REGULATOR_LEVEL_TURBO_L3 448
#define RPMH_REGULATOR_LEVEL_TURBO_L4 452
+#define RPMH_REGULATOR_LEVEL_TURBO_L5 456
#define RPMH_REGULATOR_LEVEL_SUPER_TURBO 464
#define RPMH_REGULATOR_LEVEL_SUPER_TURBO_NO_CPR 480
--
2.48.1
^ permalink raw reply related [flat|nested] 5+ messages in thread
* [PATCH v2 3/3] arm64: dts: qcom: x1e80100: Update GPU OPP table
2025-07-01 16:20 [PATCH v2 0/3] Support for Adreno X1-85 Speedbin along with new OPP levels Akhil P Oommen
2025-07-01 16:20 ` [PATCH v2 1/3] drm/msm/adreno: Add speedbin support for X1-85 Akhil P Oommen
2025-07-01 16:20 ` [PATCH v2 2/3] dt-bindings: power: qcom,rpmpd: add Turbo L5 corner Akhil P Oommen
@ 2025-07-01 16:20 ` Akhil P Oommen
2025-07-07 5:24 ` [PATCH v2 0/3] Support for Adreno X1-85 Speedbin along with new OPP levels Jens Glathe
3 siblings, 0 replies; 5+ messages in thread
From: Akhil P Oommen @ 2025-07-01 16:20 UTC (permalink / raw)
To: Rob Clark, Sean Paul, Konrad Dybcio, Dmitry Baryshkov,
Abhinav Kumar, Jessica Zhang, Marijn Suijten, David Airlie,
Simona Vetter, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Bjorn Andersson
Cc: linux-arm-msm, dri-devel, freedreno, linux-kernel, devicetree,
Akhil P Oommen
Update the GPU OPP table with new opp levels along with the
speedbin configurations.
Signed-off-by: Akhil P Oommen <akhilpo@oss.qualcomm.com>
---
arch/arm64/boot/dts/qcom/x1e80100.dtsi | 57 ++++++++++++++++++++++++++++++++--
arch/arm64/boot/dts/qcom/x1p42100.dtsi | 1 +
2 files changed, 56 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/x1e80100.dtsi b/arch/arm64/boot/dts/qcom/x1e80100.dtsi
index 558d7d387d7710770244fcc901f461384dd9b0d4..ae3a84e95bbbb282edcd8e42a860618ca9873b27 100644
--- a/arch/arm64/boot/dts/qcom/x1e80100.dtsi
+++ b/arch/arm64/boot/dts/qcom/x1e80100.dtsi
@@ -3773,6 +3773,9 @@ gpu: gpu@3d00000 {
qcom,gmu = <&gmu>;
#cooling-cells = <2>;
+ nvmem-cells = <&gpu_speed_bin>;
+ nvmem-cell-names = "speed_bin";
+
interconnects = <&gem_noc MASTER_GFX3D 0 &mc_virt SLAVE_EBI1 0>;
interconnect-names = "gfx-mem";
@@ -3785,11 +3788,28 @@ gpu_zap_shader: zap-shader {
gpu_opp_table: opp-table {
compatible = "operating-points-v2-adreno", "operating-points-v2";
+ opp-1500000000 {
+ opp-hz = /bits/ 64 <1500000000>;
+ opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L5>;
+ opp-peak-kBps = <16500000>;
+ qcom,opp-acd-level = <0xa82a5ffd>;
+ opp-supported-hw = <0x03>;
+ };
+
+ opp-1375000000 {
+ opp-hz = /bits/ 64 <1375000000>;
+ opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L4>;
+ opp-peak-kBps = <16500000>;
+ qcom,opp-acd-level = <0xa82a5ffd>;
+ opp-supported-hw = <0x03>;
+ };
+
opp-1250000000 {
opp-hz = /bits/ 64 <1250000000>;
opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L3>;
opp-peak-kBps = <16500000>;
qcom,opp-acd-level = <0xa82a5ffd>;
+ opp-supported-hw = <0x07>;
};
opp-1175000000 {
@@ -3797,13 +3817,24 @@ opp-1175000000 {
opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L2>;
opp-peak-kBps = <14398438>;
qcom,opp-acd-level = <0xa82a5ffd>;
+ opp-supported-hw = <0x07>;
};
- opp-1100000000 {
+ opp-1100000000-0 {
opp-hz = /bits/ 64 <1100000000>;
opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
opp-peak-kBps = <14398438>;
qcom,opp-acd-level = <0xa82a5ffd>;
+ opp-supported-hw = <0x07>;
+ };
+
+ /* Only applicable for SKUs which has 1100Mhz as Fmax */
+ opp-1100000000-1 {
+ opp-hz = /bits/ 64 <1100000000>;
+ opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
+ opp-peak-kBps = <16500000>;
+ qcom,opp-acd-level = <0xa82a5ffd>;
+ opp-supported-hw = <0x08>;
};
opp-1000000000 {
@@ -3811,6 +3842,7 @@ opp-1000000000 {
opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
opp-peak-kBps = <14398438>;
qcom,opp-acd-level = <0xa82b5ffd>;
+ opp-supported-hw = <0x0f>;
};
opp-925000000 {
@@ -3818,6 +3850,7 @@ opp-925000000 {
opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
opp-peak-kBps = <14398438>;
qcom,opp-acd-level = <0xa82b5ffd>;
+ opp-supported-hw = <0x0f>;
};
opp-800000000 {
@@ -3825,6 +3858,7 @@ opp-800000000 {
opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
opp-peak-kBps = <12449219>;
qcom,opp-acd-level = <0xa82c5ffd>;
+ opp-supported-hw = <0x0f>;
};
opp-744000000 {
@@ -3832,13 +3866,24 @@ opp-744000000 {
opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
opp-peak-kBps = <10687500>;
qcom,opp-acd-level = <0x882e5ffd>;
+ opp-supported-hw = <0x0f>;
};
- opp-687000000 {
+ opp-687000000-0 {
opp-hz = /bits/ 64 <687000000>;
opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
opp-peak-kBps = <8171875>;
qcom,opp-acd-level = <0x882e5ffd>;
+ opp-supported-hw = <0x0f>;
+ };
+
+ /* Only applicable for SKUs which has 687Mhz as Fmax */
+ opp-687000000-1 {
+ opp-hz = /bits/ 64 <687000000>;
+ opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
+ opp-peak-kBps = <16500000>;
+ qcom,opp-acd-level = <0x882e5ffd>;
+ opp-supported-hw = <0x10>;
};
opp-550000000 {
@@ -3846,6 +3891,7 @@ opp-550000000 {
opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
opp-peak-kBps = <6074219>;
qcom,opp-acd-level = <0xc0285ffd>;
+ opp-supported-hw = <0x1f>;
};
opp-390000000 {
@@ -3853,6 +3899,7 @@ opp-390000000 {
opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
opp-peak-kBps = <3000000>;
qcom,opp-acd-level = <0xc0285ffd>;
+ opp-supported-hw = <0x1f>;
};
opp-300000000 {
@@ -3860,6 +3907,7 @@ opp-300000000 {
opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>;
opp-peak-kBps = <2136719>;
qcom,opp-acd-level = <0xc02b5ffd>;
+ opp-supported-hw = <0x1f>;
};
};
};
@@ -8250,6 +8298,11 @@ qfprom: efuse@221c8000 {
reg = <0 0x221c8000 0 0x1000>;
#address-cells = <1>;
#size-cells = <1>;
+
+ gpu_speed_bin: gpu-speed-bin@119 {
+ reg = <0x119 0x2>;
+ bits = <7 8>;
+ };
};
pmu@24091000 {
diff --git a/arch/arm64/boot/dts/qcom/x1p42100.dtsi b/arch/arm64/boot/dts/qcom/x1p42100.dtsi
index 090659b8bb8942cdcc46f8d4a3e7dbcc043a0f78..c64727e3c00db1e4f8f34da2701061255caa620d 100644
--- a/arch/arm64/boot/dts/qcom/x1p42100.dtsi
+++ b/arch/arm64/boot/dts/qcom/x1p42100.dtsi
@@ -18,6 +18,7 @@
/delete-node/ &cpu_pd10;
/delete-node/ &cpu_pd11;
/delete-node/ &gpu_opp_table;
+/delete-node/ &gpu_speed_bin;
/delete-node/ &pcie3_phy;
&gcc {
--
2.48.1
^ permalink raw reply related [flat|nested] 5+ messages in thread* Re: [PATCH v2 0/3] Support for Adreno X1-85 Speedbin along with new OPP levels
2025-07-01 16:20 [PATCH v2 0/3] Support for Adreno X1-85 Speedbin along with new OPP levels Akhil P Oommen
` (2 preceding siblings ...)
2025-07-01 16:20 ` [PATCH v2 3/3] arm64: dts: qcom: x1e80100: Update GPU OPP table Akhil P Oommen
@ 2025-07-07 5:24 ` Jens Glathe
3 siblings, 0 replies; 5+ messages in thread
From: Jens Glathe @ 2025-07-07 5:24 UTC (permalink / raw)
To: Akhil P Oommen, Rob Clark, Sean Paul, Konrad Dybcio,
Dmitry Baryshkov, Abhinav Kumar, Jessica Zhang, Marijn Suijten,
David Airlie, Simona Vetter, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Bjorn Andersson
Cc: linux-arm-msm, dri-devel, freedreno, linux-kernel, devicetree,
Krzysztof Kozlowski
On 01.07.25 18:20, Akhil P Oommen wrote:
> This series adds gpu speedbin support for Adreno X1-85 GPU along with
> additional OPP levels. Because the higher OPPs require GPU ACD feature,
> this series has dependency on the GPU ACD support series [1] which is
> now available in v6.16-rc1.
>
Hi Akhil, thank you for the patch. I just tested this on the HP Omnibook
X14, which - with the matching dtb loaded - shows the same max frequency
as I can reach during benchmark tests on Windows (1250MHz).
jglathe@x14-jg:~$ cat /sys/class/devfreq/*gpu*/available_frequencies
300000000 390000000 550000000 687000000 744000000 800000000 925000000
1000000000 1100000000 1175000000 1250000000
Tested-by: Jens Glathe <jens.glathe@oldschoolsolutions.biz>
with best regards
Jens
^ permalink raw reply [flat|nested] 5+ messages in thread