From: Ziyue Zhang <ziyue.zhang@oss.qualcomm.com>
To: andersson@kernel.org, konradybcio@kernel.org, robh@kernel.org,
krzk+dt@kernel.org, conor+dt@kernel.org, jingoohan1@gmail.com,
mani@kernel.org, lpieralisi@kernel.org, kwilczynski@kernel.org,
bhelgaas@google.com, johan+linaro@kernel.org, vkoul@kernel.org,
kishon@kernel.org, neil.armstrong@linaro.org,
abel.vesa@linaro.org, kw@linux.com
Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org,
linux-phy@lists.infradead.org, qiang.yu@oss.qualcomm.com,
quic_krichai@quicinc.com, quic_vbadigan@quicinc.com,
Ziyue Zhang <ziyue.zhang@oss.qualcomm.com>,
Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Subject: [PATCH v4 4/4] arm64: dts: qcom: sa8775p: add link_down reset for pcie
Date: Fri, 18 Jul 2025 15:12:07 +0800 [thread overview]
Message-ID: <20250718071207.160988-5-ziyue.zhang@oss.qualcomm.com> (raw)
In-Reply-To: <20250718071207.160988-1-ziyue.zhang@oss.qualcomm.com>
SA8775p supports 'link_down' reset on hardware, so add it for both pcie0
and pcie1, which can provide a better user experience.
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Ziyue Zhang <ziyue.zhang@oss.qualcomm.com>
---
arch/arm64/boot/dts/qcom/sa8775p.dtsi | 14 ++++++++++----
1 file changed, 10 insertions(+), 4 deletions(-)
diff --git a/arch/arm64/boot/dts/qcom/sa8775p.dtsi b/arch/arm64/boot/dts/qcom/sa8775p.dtsi
index 731bd80fc806..d0a6303cb133 100644
--- a/arch/arm64/boot/dts/qcom/sa8775p.dtsi
+++ b/arch/arm64/boot/dts/qcom/sa8775p.dtsi
@@ -7635,8 +7635,11 @@ pcie0: pcie@1c00000 {
iommu-map = <0x0 &pcie_smmu 0x0000 0x1>,
<0x100 &pcie_smmu 0x0001 0x1>;
- resets = <&gcc GCC_PCIE_0_BCR>;
- reset-names = "pci";
+ resets = <&gcc GCC_PCIE_0_BCR>,
+ <&gcc GCC_PCIE_0_LINK_DOWN_BCR>;
+ reset-names = "pci",
+ "link_down";
+
power-domains = <&gcc PCIE_0_GDSC>;
phys = <&pcie0_phy>;
@@ -7803,8 +7806,11 @@ pcie1: pcie@1c10000 {
iommu-map = <0x0 &pcie_smmu 0x0080 0x1>,
<0x100 &pcie_smmu 0x0081 0x1>;
- resets = <&gcc GCC_PCIE_1_BCR>;
- reset-names = "pci";
+ resets = <&gcc GCC_PCIE_1_BCR>,
+ <&gcc GCC_PCIE_1_LINK_DOWN_BCR>;
+ reset-names = "pci",
+ "link_down";
+
power-domains = <&gcc PCIE_1_GDSC>;
phys = <&pcie1_phy>;
--
2.34.1
prev parent reply other threads:[~2025-07-18 7:12 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-07-18 7:12 [PATCH v4 0/4] pci: qcom: drop unrelated clock and add link_down reset for sa8775p Ziyue Zhang
2025-07-18 7:12 ` [PATCH v4 1/4] dt-bindings: phy: qcom,sc8280xp-qmp-pcie-phy: Update pcie phy bindings Ziyue Zhang
2025-07-18 7:12 ` [PATCH v4 2/4] dt-bindings: PCI: qcom,pcie-sa8775p: document link_down reset Ziyue Zhang
2025-07-18 7:12 ` [PATCH v4 3/4] arm64: dts: qcom: sa8775p: remove aux clock from pcie phy Ziyue Zhang
2025-07-18 7:12 ` Ziyue Zhang [this message]
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