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From: Bjorn Helgaas <helgaas@kernel.org>
To: manivannan.sadhasivam@oss.qualcomm.com
Cc: "Bjorn Helgaas" <bhelgaas@google.com>,
	"Manivannan Sadhasivam" <mani@kernel.org>,
	"Lorenzo Pieralisi" <lpieralisi@kernel.org>,
	"Krzysztof Wilczyński" <kwilczynski@kernel.org>,
	"Rob Herring" <robh@kernel.org>,
	linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org,
	linux-arm-msm@vger.kernel.org,
	"David E. Box" <david.e.box@linux.intel.com>,
	"Kai-Heng Feng" <kai.heng.feng@canonical.com>,
	"Rafael J. Wysocki" <rafael@kernel.org>,
	"Heiner Kallweit" <hkallweit1@gmail.com>,
	"Chia-Lin Kao" <acelan.kao@canonical.com>
Subject: Re: [PATCH v2 0/2] PCI/ASPM: Enable ASPM and Clock PM by default on devicetree platforms
Date: Tue, 23 Sep 2025 18:14:40 -0500	[thread overview]
Message-ID: <20250923231440.GA2088746@bhelgaas> (raw)
In-Reply-To: <20250922-pci-dt-aspm-v2-0-2a65cf84e326@oss.qualcomm.com>

On Mon, Sep 22, 2025 at 09:46:43PM +0530, Manivannan Sadhasivam via B4 Relay wrote:
> Hi,
> 
> This series is one of the 'let's bite the bullet' kind, where we have decided to
> enable all ASPM and Clock PM states by default on devicetree platforms [1]. The
> reason why devicetree platforms were chosen because, it will be of minimal
> impact compared to the ACPI platforms. So seemed ideal to test the waters.
> 
> Problem Statement
> =================
> 
> Historically, PCI subsystem relied on the BIOS to enable ASPM and Clock PM
> states for PCI devices before the kernel boot if the default states are
> selected using:
> 
> * Kconfig: CONFIG_PCIEASPM_DEFAULT=y, or
> * cmdline: "pcie_aspm=off", or
> * FADT: ACPI_FADT_NO_ASPM
> 
> This was done to avoid enabling ASPM for the buggy devices that are known to
> create issues with ASPM (even though they advertise the ASPM capability). But
> BIOS is not at all a thing on most of the non-x86 platforms. For instance, the
> majority of the Embedded and Compute ARM based platforms using devicetree have
> something called bootloader, which is not anyway near the standard BIOS used in
> x86 based platforms. And these bootloaders wouldn't touch PCIe at all, unless
> they boot using PCIe storage, even then there would be no guarantee that the
> ASPM states will get enabled. Another example is the Intel's VMD domain that is
> not at all configured by the BIOS. But, this series is not enabling ASPM/Clock
> PM for VMD domain. I hope it will be done similarly in the future patches.
> 
> Solution
> ========
> 
> So to avoid relying on BIOS, it was agreed [2] that the PCI subsystem has to
> enable ASPM and Clock PM states based on the device capability. If any devices
> misbehave, then they should be quirked accordingly.
> 
> First patch of this series introduces two helper functions to enable all ASPM
> and Clock PM states if of_have_populated_dt() is true. Second patch drops the
> custom ASPM enablement code from the pcie-qcom driver as it is no longer needed.
> 
> Testing
> =======
> 
> This series is tested on Lenovo Thinkpad T14s based on Snapdragon X1 SoC. All
> supported ASPM states are getting enabled for both the NVMe and WLAN devices by
> default.
> 
> [1] https://lore.kernel.org/linux-pci/a47sg5ahflhvzyzqnfxvpk3dw4clkhqlhznjxzwqpf4nyjx5dk@bcghz5o6zolk
> [2] https://lore.kernel.org/linux-pci/20250828204345.GA958461@bhelgaas
> 
> Changes in v2:
> 
> - Used of_have_populated_dt() instead of CONFIG_OF to identify devicetree
>   platforms
> - Renamed the override helpers and changed the override print
> - Moved setting the default state back to the original place and only kept the
>   override in helpers
> 
> Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@oss.qualcomm.com>
> ---
> Manivannan Sadhasivam (2):
>       PCI/ASPM: Override the ASPM and Clock PM states set by BIOS for devicetree platforms
>       PCI: qcom: Remove the custom ASPM enablement code
> 
>  drivers/pci/controller/dwc/pcie-qcom.c | 32 --------------------------
>  drivers/pci/pcie/aspm.c                | 42 ++++++++++++++++++++++++++++++++--
>  2 files changed, 40 insertions(+), 34 deletions(-)

I tentatively put this on pci/aspm and included it in pci/next.

I think it's too late in the cycle to include this for v6.18, so I'll
probably defer it until v6.19, but maybe we can start getting a little
more testing.

  parent reply	other threads:[~2025-09-23 23:14 UTC|newest]

Thread overview: 68+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-09-22 16:16 [PATCH v2 0/2] PCI/ASPM: Enable ASPM and Clock PM by default on devicetree platforms Manivannan Sadhasivam via B4 Relay
2025-09-22 16:16 ` [PATCH v2 1/2] PCI/ASPM: Override the ASPM and Clock PM states set by BIOS for " Manivannan Sadhasivam via B4 Relay
2025-10-14 16:30   ` FUKAUMI Naoki
2025-10-14 18:49     ` Bjorn Helgaas
2025-10-14 23:33       ` Dragan Simic
2025-10-15  6:22         ` Manivannan Sadhasivam
2025-10-15 11:23           ` Diederik de Haas
2025-10-23 18:57           ` Dragan Simic
2025-10-15  6:26       ` Manivannan Sadhasivam
2025-10-15  7:13         ` FUKAUMI Naoki
2025-10-15  7:50           ` Manivannan Sadhasivam
2025-10-15  9:11             ` Shawn Lin
2025-10-15  9:43               ` Manivannan Sadhasivam
2025-10-15  9:46               ` Niklas Cassel
2025-10-15 10:33                 ` Manivannan Sadhasivam
2025-10-15 12:17                   ` Niklas Cassel
2025-10-15 13:00                     ` Shawn Lin
2025-10-15 15:23                       ` Niklas Cassel
2025-10-15 23:30                       ` Bjorn Helgaas
2025-10-16  6:46                         ` Hongxing Zhu
2025-10-17  3:36                         ` Manivannan Sadhasivam
2025-10-17  9:47                           ` Shawn Lin
2025-10-17 10:04                             ` Manivannan Sadhasivam
2025-10-17 12:19                               ` Shawn Lin
2025-10-17 12:54                                 ` Manivannan Sadhasivam
2025-10-17 13:45                                   ` Bjorn Helgaas
2025-10-31  6:21                                     ` Manivannan Sadhasivam
2025-10-15 12:26       ` Diederik de Haas
2025-10-15 22:50         ` Bjorn Helgaas
2025-10-16 17:38           ` Diederik de Haas
2025-10-30 22:14       ` Bjorn Helgaas
2025-10-30 22:16         ` Bjorn Helgaas
2026-01-22 12:12   ` Jon Hunter
2026-01-22 13:17     ` Manivannan Sadhasivam
2026-01-22 13:43       ` Jon Hunter
2026-01-22 14:39         ` Manivannan Sadhasivam
2026-01-22 15:29     ` Bjorn Helgaas
2026-01-22 17:01       ` Manivannan Sadhasivam
2026-01-22 19:14         ` Jon Hunter
2026-01-23 10:55           ` Jon Hunter
2026-01-23 13:56             ` Manivannan Sadhasivam
2026-01-23 14:39               ` Jon Hunter
2026-02-16 14:03               ` Jon Hunter
2026-02-16 14:18                 ` Manivannan Sadhasivam
2026-02-16 14:35                   ` Jon Hunter
2026-02-19 17:42                     ` Jon Hunter
2026-02-26 10:34                       ` Jon Hunter
2026-02-26 11:08                         ` Manivannan Sadhasivam
2026-02-26 16:55                           ` Jon Hunter
2026-03-03 16:27                             ` Manivannan Sadhasivam
2026-02-26 11:16                       ` Manivannan Sadhasivam
2026-02-26 16:52                         ` Jon Hunter
2026-03-03 16:17                           ` Manivannan Sadhasivam
2026-03-06 16:03                             ` Jon Hunter
2026-03-09  8:00                               ` Manivannan Sadhasivam
2026-02-16 17:19         ` Claudiu Beznea
2026-02-18 13:56           ` Manivannan Sadhasivam
2026-05-07 10:25       ` Jon Hunter
2025-09-22 16:16 ` [PATCH v2 2/2] PCI: qcom: Remove the custom ASPM enablement code Manivannan Sadhasivam via B4 Relay
2025-09-23 23:14 ` Bjorn Helgaas [this message]
2025-11-08 16:18 ` [PATCH v2 0/2] PCI/ASPM: Enable ASPM and Clock PM by default on devicetree platforms Dmitry Baryshkov
2025-11-11  6:51   ` Val Packett
2025-11-11  7:19     ` Manivannan Sadhasivam
2025-11-11  7:40       ` Val Packett
2025-11-11 10:06         ` Manivannan Sadhasivam
2025-11-11 17:29           ` Val Packett
2025-11-13  4:30             ` Val Packett
2025-11-11 23:33     ` Bjorn Helgaas

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