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[103.229.18.19]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-27ed671732asm13793515ad.49.2025.09.24.23.33.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 24 Sep 2025 23:33:51 -0700 (PDT) From: Pankaj Patil Date: Thu, 25 Sep 2025 12:02:18 +0530 Subject: [PATCH 10/24] arm64: dts: qcom: glymur: Add SPMI PMIC arbiter device Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-Id: <20250925-v3_glymur_introduction-v1-10-24b601bbecc0@oss.qualcomm.com> References: <20250925-v3_glymur_introduction-v1-0-24b601bbecc0@oss.qualcomm.com> In-Reply-To: <20250925-v3_glymur_introduction-v1-0-24b601bbecc0@oss.qualcomm.com> To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Pankaj Patil , Kamal Wadhwa X-Mailer: b4 0.14.2 X-Proofpoint-ORIG-GUID: U4Y9B8dibmgao-CZVQ7hCinvGaIzyqfZ X-Proofpoint-GUID: U4Y9B8dibmgao-CZVQ7hCinvGaIzyqfZ X-Authority-Analysis: v=2.4 cv=No/Rc9dJ c=1 sm=1 tr=0 ts=68d4e251 cx=c_pps a=JL+w9abYAAE89/QcEU+0QA==:117 a=Ou0eQOY4+eZoSc0qltEV5Q==:17 a=IkcTkHD0fZMA:10 a=yJojWOMRYYMA:10 a=EUspDBNiAAAA:8 a=fj32sBe4WaP-u41FRDUA:9 a=QEXdDO2ut3YA:10 a=324X-CrmTo6CU4MGRt3R:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwOTIwMDAzNyBTYWx0ZWRfXzvlYI1SBjRYl wOZZXffivzEDw8zHv/kdYaqoGOhlw2DjjK+WVeq6NFi28xvI20MXD2ZwnRDchN1/mmxHXKRtPrq 827O4JQasDmL8SwmJQozB4aYK4BFwzTdAg8khrOZgH4IsxxncWX22w7EkL4m96GTYIGIPsjfIVJ PhXXDwr5WKO8AMcc0CbAF+sknhgg3JPW8ZD0Qp3L7Y0DtP6+OZPSneMusCpNfrqE0plVdpXcBDu 3ZbQ68N0vEyBWe8N6BxyOCADev8dDlo34chA1sAJ2E1WerqHAid2rpEAtIFHkGU+VVzS30y6Agu NIalixp0EpPzFlhsU0uMAonvoyDCwQgbVQNbUs+i26ODqjw/4mFGfpmf5fLH9X55Si5QV32GCl4 5GZWpyLN X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1117,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-09-24_07,2025-09-24_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 spamscore=0 suspectscore=0 adultscore=0 malwarescore=0 phishscore=0 bulkscore=0 priorityscore=1501 impostorscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2507300000 definitions=main-2509200037 From: Kamal Wadhwa Add spmi-pmic-arb device for the SPMI PMIC arbiter found on Glymur. It has three subnodes corresponding to the SPMI0, SPMI1 & SPMI2 bus controllers. Signed-off-by: Kamal Wadhwa Signed-off-by: Pankaj Patil --- arch/arm64/boot/dts/qcom/glymur.dtsi | 62 ++++++++++++++++++++++++++++++++++++ 1 file changed, 62 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/glymur.dtsi b/arch/arm64/boot/dts/qcom/glymur.dtsi index 2632ef381687c2392f8fad0294901e33887ac4d3..e6e001485747785fd29c606773cba7793bbd2a5c 100644 --- a/arch/arm64/boot/dts/qcom/glymur.dtsi +++ b/arch/arm64/boot/dts/qcom/glymur.dtsi @@ -2600,6 +2600,68 @@ sram@c30f000 { reg = <0x0 0x0c30f000 0x0 0x400>; }; + pmic_arbiter: arbiter@c400000 { + compatible = "qcom,glymur-spmi-pmic-arb"; + reg = <0x0 0x0c400000 0x0 0x00003000>, + <0x0 0x0c900000 0x0 0x00400000>, + <0x0 0x0c4c0000 0x0 0x00400000>, + <0x0 0x0c403000 0x0 0x00008000>; + reg-names = "core", + "chnls", + "obsrvr", + "chnl_map"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + qcom,channel = <0>; + qcom,ee = <0>; + + spmi_bus0: spmi@c426000 { + reg = <0x0 0x0c426000 0x0 0x00004000>, + <0x0 0x0c8c0000 0x0 0x00010000>, + <0x0 0x0c42a000 0x0 0x00008000>; + reg-names = "cnfg", + "intr", + "chnl_owner"; + interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "periph_irq"; + interrupt-controller; + #interrupt-cells = <4>; + #address-cells = <2>; + #size-cells = <0>; + }; + + spmi_bus1: spmi@c437000 { + reg = <0x0 0x0c437000 0x0 0x00004000>, + <0x0 0x0c8d0000 0x0 0x00010000>, + <0x0 0x0c43b000 0x0 0x00008000>; + reg-names = "cnfg", + "intr", + "chnl_owner"; + interrupts-extended = <&pdc 3 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "periph_irq"; + interrupt-controller; + #interrupt-cells = <4>; + #address-cells = <2>; + #size-cells = <0>; + }; + + spmi_bus2: spmi@c48000 { + reg = <0x0 0x0c448000 0x0 0x00004000>, + <0x0 0x0c8e0000 0x0 0x00010000>, + <0x0 0x0c44c000 0x0 0x00008000>; + reg-names = "cnfg", + "intr", + "chnl_owner"; + interrupts-extended = <&pdc 72 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "periph_irq"; + interrupt-controller; + #interrupt-cells = <4>; + #address-cells = <2>; + #size-cells = <0>; + }; + }; + tlmm: pinctrl@f100000 { compatible = "qcom,glymur-tlmm"; reg = <0x0 0x0f100000 0x0 0xf00000>; -- 2.34.1