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[103.229.18.19]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-27ed671732asm13793515ad.49.2025.09.24.23.34.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 24 Sep 2025 23:34:23 -0700 (PDT) From: Pankaj Patil Date: Thu, 25 Sep 2025 12:02:28 +0530 Subject: [PATCH 20/24] arm64: dts: qcom: glymur-crd: Add power supply and sideband signal for pcie5 Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-Id: <20250925-v3_glymur_introduction-v1-20-24b601bbecc0@oss.qualcomm.com> References: <20250925-v3_glymur_introduction-v1-0-24b601bbecc0@oss.qualcomm.com> In-Reply-To: <20250925-v3_glymur_introduction-v1-0-24b601bbecc0@oss.qualcomm.com> To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Pankaj Patil , Qiang Yu X-Mailer: b4 0.14.2 X-Proofpoint-GUID: n5a6RQdYi1fcwQ-AghEZS-XH0C3gC_Tj X-Proofpoint-ORIG-GUID: n5a6RQdYi1fcwQ-AghEZS-XH0C3gC_Tj X-Authority-Analysis: v=2.4 cv=Yaq95xRf c=1 sm=1 tr=0 ts=68d4e273 cx=c_pps a=cmESyDAEBpBGqyK7t0alAg==:117 a=Ou0eQOY4+eZoSc0qltEV5Q==:17 a=IkcTkHD0fZMA:10 a=yJojWOMRYYMA:10 a=EUspDBNiAAAA:8 a=p3KB_V4m9cBtC7zP5zwA:9 a=QEXdDO2ut3YA:10 a=1OuFwYUASf3TG4hYMiVC:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwOTIzMDExMyBTYWx0ZWRfX8NyM/Vgt7Y9C THH2dBnK/iXEK9sSS0/OSeYbNko47ypXGUqDg3StmIxEf70Fs0NVDlu6oMBsqWI7GEgx7NAV6g+ UowLiVi+3y3XR64pGNrN3nv/hwiIYVYW7NcVWf6QwYghr32piSpT0JruecSl8ubzgLDQ4s6lJgy 8eaE3bGg82errgEBaWynVR7H6vVWHlazuCAvja8313RheThm5ildo5o6gKHrAFsflvlRizSnIbP CGq5FWCc1msX4ye1F9ZONX5G7MZBUy7yjNty9QbuqaL+fQDoLa0NBseNgenD7/dNzO70UVzYTJq T6XUP4unqZ3CI3YODJ7ZlasBnnte2V3IYCusMigmPbKOgSiz1bMqOrsgQx20PLa506dss+O1Qky DbkektpZ X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1117,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-09-24_07,2025-09-24_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 clxscore=1015 suspectscore=0 priorityscore=1501 phishscore=0 adultscore=0 malwarescore=0 impostorscore=0 bulkscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2507300000 definitions=main-2509230113 From: Qiang Yu Add perst, wake and clkreq sideband signals and required regulators in PCIe5 controller and PHY device tree node. Signed-off-by: Qiang Yu Signed-off-by: Pankaj Patil --- arch/arm64/boot/dts/qcom/glymur-crd.dts | 68 +++++++++++++++++++++++++++++++++ 1 file changed, 68 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/glymur-crd.dts b/arch/arm64/boot/dts/qcom/glymur-crd.dts index 3f94bdf8b3ccfdff182005d67b8b3f84f956a430..03aacdb1dd7e2354fe31e63183519e53fa022829 100644 --- a/arch/arm64/boot/dts/qcom/glymur-crd.dts +++ b/arch/arm64/boot/dts/qcom/glymur-crd.dts @@ -107,6 +107,20 @@ port@1 { }; }; }; + + vreg_nvme: regulator-nvme { + compatible = "regulator-fixed"; + + regulator-name = "VREG_NVME_3P3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + gpio = <&pmh0101_gpios 14 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 = <&nvme_reg_en>; + pinctrl-names = "default"; + }; }; &tlmm { @@ -461,3 +475,57 @@ vreg_l4h_e0_1p2: ldo4 { &pmk8850_rtc { no-alarm; }; + +&pmh0101_gpios { + nvme_reg_en: nvme-reg-en-state { + pins = "gpio14"; + function = "normal"; + bias-disable; + }; +}; + +&tlmm { + pcie5_default: pcie5-default-state { + clkreq-n-pins { + pins = "gpio153"; + function = "pcie5_clk_req_n"; + drive-strength = <2>; + bias-pull-up; + }; + + perst-n-pins { + pins = "gpio152"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + wake-n-pins { + pins = "gpio154"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + }; +}; + +&pcie5 { + vddpe-3v3-supply = <&vreg_nvme>; + + pinctrl-0 = <&pcie5_default>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&pcie5_phy { + vdda-phy-supply = <&vreg_l2f_e0_0p82>; + vdda-pll-supply = <&vreg_l4h_e0_1p2>; + + status = "okay"; +}; + +&pcie5port0 { + perst-gpios = <&tlmm 152 GPIO_ACTIVE_LOW>; + wake-gpios = <&tlmm 154 GPIO_ACTIVE_LOW>; +}; -- 2.34.1