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[103.229.18.19]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-27ed671732asm13793515ad.49.2025.09.24.23.34.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 24 Sep 2025 23:34:30 -0700 (PDT) From: Pankaj Patil Date: Thu, 25 Sep 2025 12:02:30 +0530 Subject: [PATCH 22/24] arm64: dts: qcom: glymur: Add display clock controller device Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-Id: <20250925-v3_glymur_introduction-v1-22-24b601bbecc0@oss.qualcomm.com> References: <20250925-v3_glymur_introduction-v1-0-24b601bbecc0@oss.qualcomm.com> In-Reply-To: <20250925-v3_glymur_introduction-v1-0-24b601bbecc0@oss.qualcomm.com> To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Pankaj Patil , Taniya Das X-Mailer: b4 0.14.2 X-Authority-Analysis: v=2.4 cv=YPqfyQGx c=1 sm=1 tr=0 ts=68d4e278 cx=c_pps a=MTSHoo12Qbhz2p7MsH1ifg==:117 a=Ou0eQOY4+eZoSc0qltEV5Q==:17 a=IkcTkHD0fZMA:10 a=yJojWOMRYYMA:10 a=EUspDBNiAAAA:8 a=xJZpmU4_KKqDGsKAShUA:9 a=QEXdDO2ut3YA:10 a=GvdueXVYPmCkWapjIL-Q:22 X-Proofpoint-ORIG-GUID: MlCWAKHzCzMWS95l9V6ADjqT20JKnljT X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwOTIwMDAwMCBTYWx0ZWRfX74/bmlIGB77e anroQ3ScNaD3CTk5ZnfWHscZ8d3fJ/6PIXmNOmd2hQif/aHaX8ZbwsAWVpL5gBAfGG/sxFn8J6z ZUmgSRhte//VjkE7+eSULlBMSphq/JI9B8KgwjYRyfNOLCOzhQudGJSZA6RpWPscCxuu0qc2lCs cli7khvnz17lNZ8bDqr1bDgBXCH6bG1EcOSnx6rgy/7WxFt/tyYMZdXQFLmRIbO3w+6n80B/Z0f FwIH2gCApRve/QnohOLjKyh/sRJiUqKZeXC7/OdTlbr8XlMoS2vahoA09iXIm5XifTxQcrf6d48 IZejJ1XRWGqFjOjgIWtjef8uOu0u8krcKk9U1R19ZwO80PNFKhY01IwQbYaQ6afMOCWD8YvPnXr /xxZJqBF X-Proofpoint-GUID: MlCWAKHzCzMWS95l9V6ADjqT20JKnljT X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1117,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-09-24_07,2025-09-24_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 bulkscore=0 priorityscore=1501 phishscore=0 adultscore=0 clxscore=1015 impostorscore=0 spamscore=0 malwarescore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2507300000 definitions=main-2509200000 From: Taniya Das Support the display clock controller for GLYMUR SoC. Signed-off-by: Taniya Das Signed-off-by: Pankaj Patil --- arch/arm64/boot/dts/qcom/glymur.dtsi | 30 ++++++++++++++++++++++++++++++ 1 file changed, 30 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/glymur.dtsi b/arch/arm64/boot/dts/qcom/glymur.dtsi index 986dc385200029071136068ab79ff8dd66d5284a..8a563d55bdd4902222039946dd75eaf4d3a4895b 100644 --- a/arch/arm64/boot/dts/qcom/glymur.dtsi +++ b/arch/arm64/boot/dts/qcom/glymur.dtsi @@ -3,6 +3,7 @@ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. */ +#include #include #include #include @@ -13,6 +14,7 @@ #include #include #include +#include #include #include #include @@ -2775,6 +2777,34 @@ lpass_ag_noc: interconnect@7e40000 { #interconnect-cells = <2>; }; + dispcc: clock-controller@af00000 { + compatible = "qcom,glymur-dispcc"; + reg = <0 0x0af00000 0 0x20000>; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&sleep_clk>, + <0>, /* dp0 */ + <0>, + <0>, /* dp1 */ + <0>, + <0>, /* dp2 */ + <0>, + <0>, /* dp3 */ + <0>, + <0>, /* dsi0 */ + <0>, + <0>, /* dsi1 */ + <0>, + <0>, + <0>, + <0>, + <0>; + power-domains = <&rpmhpd RPMHPD_MMCX>; + required-opps = <&rpmhpd_opp_turbo>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; + pdc: interrupt-controller@b220000 { compatible = "qcom,glymur-pdc", "qcom,pdc"; reg = <0x0 0x0b220000 0x0 0x10000>; -- 2.34.1