From: Pankaj Patil <pankaj.patil@oss.qualcomm.com>
To: Bjorn Andersson <andersson@kernel.org>,
Konrad Dybcio <konradybcio@kernel.org>,
Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>
Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org,
Pankaj Patil <pankaj.patil@oss.qualcomm.com>,
Kamal Wadhwa <kamal.wadhwa@oss.qualcomm.com>
Subject: [PATCH v2 09/24] arm64: dts: qcom: glymur-crd: Add RPMH regulator rails
Date: Thu, 25 Sep 2025 11:58:15 +0530 [thread overview]
Message-ID: <20250925-v3_glymur_introduction-v2-9-8e1533a58d2d@oss.qualcomm.com> (raw)
In-Reply-To: <20250925-v3_glymur_introduction-v2-0-8e1533a58d2d@oss.qualcomm.com>
From: Kamal Wadhwa <kamal.wadhwa@oss.qualcomm.com>
Add RPMH regulator rails for Glymur CRD.
Signed-off-by: Kamal Wadhwa <kamal.wadhwa@oss.qualcomm.com>
Signed-off-by: Pankaj Patil <pankaj.patil@oss.qualcomm.com>
---
arch/arm64/boot/dts/qcom/glymur-crd.dts | 332 ++++++++++++++++++++++++++++++++
1 file changed, 332 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/glymur-crd.dts b/arch/arm64/boot/dts/qcom/glymur-crd.dts
index 4561c0b87b017cba0a1db8814123a070b37fd434..e89b81dcb4f47b78307fa3ab6831657cf6491c89 100644
--- a/arch/arm64/boot/dts/qcom/glymur-crd.dts
+++ b/arch/arm64/boot/dts/qcom/glymur-crd.dts
@@ -6,6 +6,7 @@
/dts-v1/;
#include "glymur.dtsi"
+#include <dt-bindings/regulator/qcom,rpmh-regulator.h>
/ {
model = "Qualcomm Technologies, Inc. Glymur CRD";
@@ -66,3 +67,334 @@ chosen {
&tlmm {
gpio-reserved-ranges = <4 4>, <10 2>, <44 4>; /*Security SPI (TPM)*/
};
+
+&apps_rsc {
+
+ vph_pwr: vph-pwr-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vph_pwr";
+ regulator-min-microvolt = <3700000>;
+ regulator-max-microvolt = <3700000>;
+ };
+
+ regulators-0 {
+ compatible = "qcom,pmh0101-rpmh-regulators";
+ qcom,pmic-id = "B_E0";
+
+ vdd-bob1-supply = <&vph_pwr>;
+ vdd-bob2-supply = <&vph_pwr>;
+ vdd-l1-l10-l15-supply = <&vreg_s9f_e0_1p9>;
+ vdd-l2-l7-l8-l9-l16-supply = <&vreg_bob1_e0>;
+ vdd-l11-l12-l18-supply = <&vreg_s7f_e0_1p32>;
+ vdd-l17-supply = <&vreg_bob2_e0>;
+
+ vreg_bob1_e0: bob1 {
+ regulator-name = "vreg_bob1_e0";
+ regulator-min-microvolt = <2200000>;
+ regulator-max-microvolt = <4224000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_AUTO>;
+ };
+
+ vreg_bob2_e0: bob2 {
+ regulator-name = "vreg_bob2_e0";
+ regulator-min-microvolt = <2540000>;
+ regulator-max-microvolt = <3600000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_AUTO>;
+ };
+
+ vreg_l1b_e0_1p8: ldo1 {
+ regulator-name = "vreg_l1b_e0_1p8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l2b_e0_2p9: ldo2 {
+ regulator-name = "vreg_l2b_e0_2p9";
+ regulator-min-microvolt = <2900000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l7b_e0_2p79: ldo7 {
+ regulator-name = "vreg_l7b_e0_2p79";
+ regulator-min-microvolt = <2790000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l8b_e0_1p50: ldo8 {
+ regulator-name = "vreg_l8b_e0_1p50";
+ regulator-min-microvolt = <1504000>;
+ regulator-max-microvolt = <3544000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l9b_e0_2p7: ldo9 {
+ regulator-name = "vreg_l9b_e0_2p7";
+ regulator-min-microvolt = <2700000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l10b_e0_1p8: ldo10 {
+ regulator-name = "vreg_l10b_e0_1p8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l11b_e0_1p2: ldo11 {
+ regulator-name = "vreg_l11b_e0_1p2";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l12b_e0_1p14: ldo12 {
+ regulator-name = "vreg_l12b_e0_1p14";
+ regulator-min-microvolt = <1140000>;
+ regulator-max-microvolt = <1260000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l15b_e0_1p8: ldo15 {
+ regulator-name = "vreg_l15b_e0_1p8";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l17b_e0_2p4: ldo17 {
+ regulator-name = "vreg_l17b_e0_2p4";
+ regulator-min-microvolt = <2400000>;
+ regulator-max-microvolt = <2700000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l18b_e0_1p2: ldo18 {
+ regulator-name = "vreg_l18b_e0_1p2";
+ regulator-min-microvolt = <1200000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+ };
+
+ regulators-1 {
+ compatible = "qcom,pmcx0102-rpmh-regulators";
+ qcom,pmic-id = "C_E0";
+ vdd-s1-supply = <&vph_pwr>;
+ vdd-s8-supply = <&vph_pwr>;
+
+ vreg_s1c_e0_0p3: smps1 {
+ regulator-name = "vreg_s1c_e0_0p3";
+ regulator-min-microvolt = <300000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_s8c_e0_0p3: smps8 {
+ regulator-name = "vreg_s8c_e0_0p3";
+ regulator-min-microvolt = <300000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+ };
+
+ regulators-2 {
+ compatible = "qcom,pmcx0102-rpmh-regulators";
+ qcom,pmic-id = "C_E1";
+
+ vdd-l2-supply = <&vreg_s7f_e0_1p32>;
+ vdd-l1-l3-l4-supply = <&vreg_s8f_e0_0p95>;
+
+ vreg_l1c_e1_0p82: ldo1 {
+ regulator-name = "vreg_l1c_e1_0p82";
+ regulator-min-microvolt = <825000>;
+ regulator-max-microvolt = <958000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l2c_e1_1p14: ldo2 {
+ regulator-name = "vreg_l2c_e1_1p14";
+ regulator-min-microvolt = <1140000>;
+ regulator-max-microvolt = <1300000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l3c_e1_0p89: ldo3 {
+ regulator-name = "vreg_l3c_e1_0p89";
+ regulator-min-microvolt = <890000>;
+ regulator-max-microvolt = <980000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l4c_e1_0p72: ldo4 {
+ regulator-name = "vreg_l4c_e1_0p72";
+ regulator-min-microvolt = <720000>;
+ regulator-max-microvolt = <980000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+ };
+
+ regulators-3 {
+ compatible = "qcom,pmh0110-rpmh-regulators";
+ qcom,pmic-id = "F_E0";
+ vdd-s7-supply = <&vph_pwr>;
+ vdd-s8-supply = <&vph_pwr>;
+ vdd-s9-supply = <&vph_pwr>;
+ vdd-s10-supply = <&vph_pwr>;
+ vdd-l2-supply = <&vreg_s8f_e0_0p95>;
+ vdd-l3-supply = <&vreg_s8f_e0_0p95>;
+ vdd-l4-supply = <&vreg_s8f_e0_0p95>;
+
+ vreg_s7f_e0_1p32: smps7 {
+ regulator-name = "vreg_s7f_e0_1p32";
+ regulator-min-microvolt = <1320000>;
+ regulator-max-microvolt = <1352000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_s8f_e0_0p95: smps8 {
+ regulator-name = "vreg_s8f_e0_0p95";
+ regulator-min-microvolt = <952000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_s9f_e0_1p9: smps9 {
+ regulator-name = "vreg_s9f_e0_1p9";
+ regulator-min-microvolt = <1900000>;
+ regulator-max-microvolt = <2000000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_s10f_e0_0p3: smps10 {
+ regulator-name = "vreg_s10f_e0_0p3";
+ regulator-min-microvolt = <300000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l2f_e0_0p82: ldo2 {
+ regulator-name = "vreg_l2f_e0_0p82";
+ regulator-min-microvolt = <825000>;
+ regulator-max-microvolt = <980000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l3f_e0_0p72: ldo3 {
+ regulator-name = "vreg_l3f_e0_0p72";
+ regulator-min-microvolt = <720000>;
+ regulator-max-microvolt = <980000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l4f_e0_0p3: ldo4 {
+ regulator-name = "vreg_l4f_e0_0p3";
+ regulator-min-microvolt = <300000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+ };
+
+ regulators-4 {
+ compatible = "qcom,pmh0110-rpmh-regulators";
+ qcom,pmic-id = "F_E1";
+ vdd-s1-supply = <&vph_pwr>;
+ vdd-s3-supply = <&vph_pwr>;
+ vdd-s5-supply = <&vph_pwr>;
+ vdd-s6-supply = <&vph_pwr>;
+ vdd-s7-supply = <&vph_pwr>;
+ vdd-l1-supply = <&vreg_s8f_e0_0p95>;
+ vdd-l2-supply = <&vreg_s8f_e0_0p95>;
+ vdd-l4-supply = <&vreg_s8f_e0_0p95>;
+
+ vreg_s1f_e1_0p3: smps1 {
+ regulator-name = "vreg_s1f_e1_0p3";
+ regulator-min-microvolt = <300000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_s5f_e1_0p3: smps5 {
+ regulator-name = "vreg_s5f_e1_0p3";
+ regulator-min-microvolt = <300000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_s6f_e1_0p3: smps6 {
+ regulator-name = "vreg_s6f_e1_0p3";
+ regulator-min-microvolt = <300000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_s7f_e1_0p3: smps7 {
+ regulator-name = "vreg_s7f_e1_0p3";
+ regulator-min-microvolt = <300000>;
+ regulator-max-microvolt = <1200000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l1f_e1_0p82: ldo1 {
+ regulator-name = "vreg_l1f_e1_0p82";
+ regulator-min-microvolt = <825000>;
+ regulator-max-microvolt = <950000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l2f_e1_0p83: ldo2 {
+ regulator-name = "vreg_l2f_e1_0p83";
+ regulator-min-microvolt = <830000>;
+ regulator-max-microvolt = <920000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l4f_e1_1p08: ldo4 {
+ regulator-name = "vreg_l4f_e1_1p08";
+ regulator-min-microvolt = <1080000>;
+ regulator-max-microvolt = <1320000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+ };
+
+ regulators-5 {
+ compatible = "qcom,pmh0110-rpmh-regulators";
+ qcom,pmic-id = "H_E0";
+
+ vdd-l1-supply = <&vreg_s8f_e0_0p95>;
+ vdd-l2-supply = <&vreg_s8f_e0_0p95>;
+ vdd-l3-supply = <&vreg_s9f_e0_1p9>;
+ vdd-l4-supply = <&vreg_s7f_e0_1p32>;
+
+ vreg_l1h_e0_0p89: ldo1 {
+ regulator-name = "vreg_l1h_e0_0p89";
+ regulator-min-microvolt = <825000>;
+ regulator-max-microvolt = <950000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l2h_e0_0p72: ldo2 {
+ regulator-name = "vreg_l2h_e0_0p72";
+ regulator-min-microvolt = <830000>;
+ regulator-max-microvolt = <920000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l3h_e0_0p32: ldo3 {
+ regulator-name = "vreg_l3h_e0_0p32";
+ regulator-min-microvolt = <320000>;
+ regulator-max-microvolt = <2000000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+
+ vreg_l4h_e0_1p2: ldo4 {
+ regulator-name = "vreg_l4h_e0_1p2";
+ regulator-min-microvolt = <1080000>;
+ regulator-max-microvolt = <1320000>;
+ regulator-initial-mode = <RPMH_REGULATOR_MODE_HPM>;
+ };
+ };
+};
--
2.34.1
next prev parent reply other threads:[~2025-09-25 6:29 UTC|newest]
Thread overview: 43+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-09-25 6:28 [PATCH v2 00/24] arm64: dts: qcom: Introduce Glymur SoC dtsi and Glymur CRD dts Pankaj Patil
2025-09-25 6:28 ` [PATCH v2 01/24] dt-bindings: arm: qcom: Document Glymur SoC and board Pankaj Patil
2025-09-25 6:28 ` [PATCH v2 02/24] arm64: defconfig: Enable Glymur configs for boot to shell Pankaj Patil
2025-09-25 21:09 ` Dmitry Baryshkov
2025-09-25 6:28 ` [PATCH v2 03/24] arm64: dts: qcom: Introduce Glymur base dtsi and CRD dts Pankaj Patil
2025-09-25 6:28 ` [PATCH v2 04/24] arm64: dts: qcom: glymur: Add QUPv3 configuration for serial engines Pankaj Patil
2025-09-25 21:16 ` Dmitry Baryshkov
2025-10-15 10:47 ` Jyothi Kumar Seerapu
2025-09-25 6:28 ` [PATCH v2 05/24] arm64: dts: qcom: glymur: Add cpu idle states Pankaj Patil
2025-09-25 6:28 ` [PATCH v2 06/24] arm64: dts: qcom: glymur: Enable pdp0 mailbox Pankaj Patil
2025-09-25 6:28 ` [PATCH v2 07/24] arm64: dts: qcom: glymur: Enable cpu dvfs for CPU scaling Pankaj Patil
2025-09-25 6:28 ` [PATCH v2 08/24] arm64: dts: qcom: glymur: Enable ipcc and aoss nodes Pankaj Patil
2025-09-25 6:28 ` Pankaj Patil [this message]
2025-09-25 6:28 ` [PATCH v2 10/24] arm64: dts: qcom: glymur: Add SPMI PMIC arbiter device Pankaj Patil
2025-09-25 6:28 ` [PATCH v2 11/24] arm64: dts: qcom: Add PMCX0102 pmic dtsi Pankaj Patil
2025-09-25 6:28 ` [PATCH v2 12/24] arm64: dts: qcom: Add SMB2370 " Pankaj Patil
2025-09-25 6:28 ` [PATCH v2 13/24] arm64: dts: qcom: Update pmh0104 dtsi for Glymur CRD Pankaj Patil
2025-09-25 7:55 ` Krzysztof Kozlowski
2025-09-26 7:07 ` Pankaj Patil
2025-09-26 8:55 ` Konrad Dybcio
2025-09-25 6:28 ` [PATCH v2 14/24] arm64: dts: qcom: Update the pmh0110.dtsi for Glymur Pankaj Patil
2025-09-25 6:28 ` [PATCH v2 15/24] arm64: dts: qcom: glymur: Add PMICs dtsi for CRD Pankaj Patil
2025-09-25 8:15 ` Abel Vesa
2025-09-30 14:22 ` Kamal Wadhwa
2025-09-25 6:28 ` [PATCH v2 16/24] arm64: boot: dts: glymur-crd: Add Volume down/up keys support Pankaj Patil
2025-09-25 13:45 ` Krzysztof Kozlowski
2025-09-25 6:28 ` [PATCH v2 17/24] arm64: dts: qcom: glymur-crd: Avoid RTC probe failure Pankaj Patil
2025-09-25 6:28 ` [PATCH v2 18/24] arm64: dts: qcom: glymur: Add PMIC glink node Pankaj Patil
2025-09-25 6:28 ` [PATCH v2 19/24] arm64: dts: qcom: glymur: Add support for PCIe5 Pankaj Patil
2025-09-25 6:28 ` [PATCH v2 20/24] arm64: dts: qcom: glymur-crd: Add power supply and sideband signal for pcie5 Pankaj Patil
2025-09-25 6:28 ` [PATCH v2 21/24] arm64: dts: qcom: glymur: Enable tsens and thermal zone nodes Pankaj Patil
2025-09-25 6:28 ` [PATCH v2 22/24] arm64: dts: qcom: glymur: Add display clock controller device Pankaj Patil
2025-09-25 6:28 ` [PATCH v2 23/24] arm64: dts: qcom: glymur: Add USB support Pankaj Patil
2025-09-25 8:06 ` Abel Vesa
2025-09-25 10:54 ` Abel Vesa
2025-09-25 10:59 ` Konrad Dybcio
2025-09-25 11:29 ` Abel Vesa
2025-09-26 1:09 ` Wesley Cheng
2025-10-01 8:42 ` Konrad Dybcio
2025-09-25 20:42 ` Dmitry Baryshkov
2025-09-25 6:28 ` [PATCH v2 24/24] arm64: dts: qcom: glymur: Add remoteprocs Pankaj Patil
2025-09-25 6:35 ` [PATCH v2 00/24] arm64: dts: qcom: Introduce Glymur SoC dtsi and Glymur CRD dts Pankaj Patil
2025-09-25 21:06 ` Dmitry Baryshkov
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20250925-v3_glymur_introduction-v2-9-8e1533a58d2d@oss.qualcomm.com \
--to=pankaj.patil@oss.qualcomm.com \
--cc=andersson@kernel.org \
--cc=conor+dt@kernel.org \
--cc=devicetree@vger.kernel.org \
--cc=kamal.wadhwa@oss.qualcomm.com \
--cc=konradybcio@kernel.org \
--cc=krzk+dt@kernel.org \
--cc=linux-arm-msm@vger.kernel.org \
--cc=linux-kernel@vger.kernel.org \
--cc=robh@kernel.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).