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Wed, 22 Oct 2025 01:41:05 -0700 (PDT) X-Google-Smtp-Source: AGHT+IGb91OwEUPXSLbVPj+Cd6pyUWYUNUbhUhWolXQs0W0Kwo71NvZHu8POb8y8sNsk2y7/uHctWQ== X-Received: by 2002:a05:6a00:1817:b0:78a:f7cb:1e81 with SMTP id d2e1a72fcca58-7a2647c8eccmr3235811b3a.13.1761122464870; Wed, 22 Oct 2025 01:41:04 -0700 (PDT) Received: from hu-kriskura-hyd.qualcomm.com ([202.46.22.19]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-7a25e9be9f3sm3740317b3a.71.2025.10.22.01.41.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 22 Oct 2025 01:41:04 -0700 (PDT) From: Krishna Kurapati To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson , Konrad Dybcio Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Wesley Cheng , Konrad Dybcio , Krishna Kurapati Subject: [PATCH v8 1/3] arm64: dts: qcom: sm8750: Add USB support to SM8750 SoCs Date: Wed, 22 Oct 2025 14:10:50 +0530 Message-Id: <20251022084052.218043-2-krishna.kurapati@oss.qualcomm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20251022084052.218043-1-krishna.kurapati@oss.qualcomm.com> References: <20251022084052.218043-1-krishna.kurapati@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMDE4MDAyMCBTYWx0ZWRfX2rmjCmgL3Z1v w2ospASQ6jBvWtHb1eVLbPsv6xV19GCkVt7bHrfROYHVZPslz2TjfNOEZNgmf9Jqww8jEdC45Hm boeAyqaSIy2DJ+6cO9/PVGMyxX1AB2FCJ7uQvxQ0Fo7sdq4W/NQ2PQWxTmO9AI9vHxOQED2FQZQ w3TgyybUNZTz3XibPoIl7geifm0H2omcWZPM3jprBP+A0bttQ8teGzDcq8P4nF1ASVS3nUMjBMg ukddVHYbc6YmTOgULHI6U7qxIZF6UpCESxMyJ+mTwbkt4vdUpYf7uVpZZ+zd6b8P1IPCRCsa1HQ MNzXTiJD2ejE1tJwLanXpYWIa1w6HO3bW7JkB6GUcEkBgZobeQhRVdRzhhYUd3EkNAMjtGRAvuP b1KBYcWBHgOLli8+8ihAbQfiG1rZlw== X-Authority-Analysis: v=2.4 cv=KqFAGGWN c=1 sm=1 tr=0 ts=68f898a3 cx=c_pps a=mDZGXZTwRPZaeRUbqKGCBw==:117 a=fChuTYTh2wq5r3m49p7fHw==:17 a=x6icFKpwvdMA:10 a=VkNPw1HP01LnGYTKEx00:22 a=EUspDBNiAAAA:8 a=n1SQX4eW7R_9Zp26JX0A:9 a=zc0IvFSfCIW2DFIPzwfm:22 X-Proofpoint-GUID: LsqTI56kgSEUYICGaMnl46iqJI6iaL3d X-Proofpoint-ORIG-GUID: LsqTI56kgSEUYICGaMnl46iqJI6iaL3d X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-10-22_03,2025-10-13_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 clxscore=1015 phishscore=0 malwarescore=0 impostorscore=0 lowpriorityscore=0 adultscore=0 priorityscore=1501 spamscore=0 suspectscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2510020000 definitions=main-2510180020 From: Wesley Cheng Add the base USB devicetree definitions for SM8750 platforms. The overall chipset contains a single DWC3 USB3 controller (rev. 200a), SS QMP PHY (rev. v8) and M31 eUSB2 PHY. The major difference for SM8750 is the transition to using the M31 eUSB2 PHY compared to previous SoCs. Enable USB support on SM8750 MTP and QRD variants. SM8750 has a QMP combo PHY for the SSUSB path, and a M31 eUSB2 PHY for the HSUSB path. Signed-off-by: Wesley Cheng Suggested-by: Konrad Dybcio [Konrad: Suggestion to flatten DT] Signed-off-by: Krishna Kurapati --- arch/arm64/boot/dts/qcom/sm8750.dtsi | 158 +++++++++++++++++++++++++++ 1 file changed, 158 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8750.dtsi b/arch/arm64/boot/dts/qcom/sm8750.dtsi index a82d9867c7cb..d933c378bd8d 100644 --- a/arch/arm64/boot/dts/qcom/sm8750.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8750.dtsi @@ -12,6 +12,7 @@ #include #include #include +#include #include #include #include @@ -2581,6 +2582,163 @@ data-pins { }; }; + usb_1_hsphy: phy@88e3000 { + compatible = "qcom,sm8750-m31-eusb2-phy"; + reg = <0x0 0x88e3000 0x0 0x29c>; + + clocks = <&tcsrcc TCSR_USB2_CLKREF_EN>; + clock-names = "ref"; + + resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; + + #phy-cells = <0>; + + status = "disabled"; + }; + + usb_dp_qmpphy: phy@88e8000 { + compatible = "qcom,sm8750-qmp-usb3-dp-phy"; + reg = <0x0 0x088e8000 0x0 0x4000>; + + clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, + <&tcsrcc TCSR_USB3_CLKREF_EN>, + <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>, + <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; + clock-names = "aux", + "ref", + "com_aux", + "usb3_pipe"; + + resets = <&gcc GCC_USB3_PHY_PRIM_BCR>, + <&gcc GCC_USB3_DP_PHY_PRIM_BCR>; + reset-names = "phy", + "common"; + + power-domains = <&gcc GCC_USB3_PHY_GDSC>; + + #clock-cells = <1>; + #phy-cells = <1>; + + orientation-switch; + + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + usb_dp_qmpphy_out: endpoint { + }; + }; + + port@1 { + reg = <1>; + + usb_dp_qmpphy_usb_ss_in: endpoint { + remote-endpoint = <&usb_1_dwc3_ss>; + }; + }; + + port@2 { + reg = <2>; + + usb_dp_qmpphy_dp_in: endpoint { + }; + }; + }; + }; + + usb_1: usb@a600000 { + compatible = "qcom,sm8750-dwc3", "qcom,snps-dwc3"; + reg = <0x0 0x0a600000 0x0 0xfc100>; + + clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, + <&gcc GCC_USB30_PRIM_MASTER_CLK>, + <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, + <&gcc GCC_USB30_PRIM_SLEEP_CLK>, + <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>; + clock-names = "cfg_noc", + "core", + "iface", + "sleep", + "mock_utmi"; + + assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, + <&gcc GCC_USB30_PRIM_MASTER_CLK>; + assigned-clock-rates = <19200000>, + <200000000>; + + interrupts-extended = <&intc GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 14 IRQ_TYPE_EDGE_BOTH>, + <&pdc 15 IRQ_TYPE_EDGE_BOTH>, + <&pdc 17 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "dwc_usb3", + "pwr_event", + "hs_phy_irq", + "dp_hs_phy_irq", + "dm_hs_phy_irq", + "ss_phy_irq"; + + power-domains = <&gcc GCC_USB30_PRIM_GDSC>; + required-opps = <&rpmhpd_opp_nom>; + + resets = <&gcc GCC_USB30_PRIM_BCR>; + + interconnects = <&aggre1_noc MASTER_USB3_0 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_USB3_0 QCOM_ICC_TAG_ACTIVE_ONLY>; + interconnect-names = "usb-ddr", "apps-usb"; + + iommus = <&apps_smmu 0x40 0x0>; + + phys = <&usb_1_hsphy>, + <&usb_dp_qmpphy QMP_USB43DP_USB3_PHY>; + phy-names = "usb2-phy", + "usb3-phy"; + + snps,hird-threshold = /bits/ 8 <0x0>; + snps,usb2-gadget-lpm-disable; + snps,dis_u2_susphy_quirk; + snps,dis_enblslpm_quirk; + snps,dis-u1-entry-quirk; + snps,dis-u2-entry-quirk; + snps,is-utmi-l1-suspend; + snps,usb3_lpm_capable; + snps,usb2-lpm-disable; + snps,has-lpm-erratum; + tx-fifo-resize; + + dma-coherent; + + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + usb_1_dwc3_hs: endpoint { + }; + }; + + port@1 { + reg = <1>; + + usb_1_dwc3_ss: endpoint { + remote-endpoint = <&usb_dp_qmpphy_usb_ss_in>; + }; + }; + }; + }; + pdc: interrupt-controller@b220000 { compatible = "qcom,sm8750-pdc", "qcom,pdc"; reg = <0x0 0x0b220000 0x0 0x10000>, <0x0 0x164400f0 0x0 0x64>; -- 2.34.1