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([67.243.142.39]) by smtp.gmail.com with ESMTPSA id 6a1803df08f44-87fc4997e56sm81140356d6.49.2025.10.28.11.17.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 28 Oct 2025 11:17:14 -0700 (PDT) From: Connor Abbott To: Rob Clark , Akhil P Oommen , Sean Paul , Konrad Dybcio , Dmitry Baryshkov , Abhinav Kumar , Jessica Zhang , Marijn Suijten Cc: Connor Abbott , freedreno@lists.freedesktop.org, linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org Subject: [PATCH RESEND] drm/msm: Don't sync BR and BV before every submit Date: Tue, 28 Oct 2025 14:16:21 -0400 Message-ID: <20251028-msm-less-bv-sync-v1-1-6527fd02c52f@gmail.com> X-Mailer: git-send-email 2.49.0 Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1761675189; l=3477; i=cwabbott0@gmail.com; s=20240426; h=from:subject:message-id; bh=5B/tyXXNbztReQJ/afPZcg+Os2/bScCFHYAx7g9KsyM=; b=gDev45SDt2WD6lFN2WxncUZVzICSsgh7zVUNFwfbSqkfv+Xq8GQd9/WxiThtzubpvUfQiOvRb 6PH9hK80ZbcChFHSfiB/iugYyqo3NL+uw/1qLezaKxzCuxkiLQkwC1j X-Developer-Key: i=cwabbott0@gmail.com; a=ed25519; pk=dkpOeRSXLzVgqhy0Idr3nsBr4ranyERLMnoAgR4cHmY= Content-Transfer-Encoding: quoted-printable We should allow BV to run ahead of BR when there are multiple submits=0D from the same context. Per the Vulkan memory model this should be safe=0D because there are no implied execution dependencies between submits. In=0D particular this should allow BV to run at least a frame ahead of BR when=0D applications render direct to display (i.e. unredirected rendering).=0D =0D We also shuffle around some of the synchronization in=0D a6xx_set_pagetable() to better match what the downstream driver does.=0D Previously this was only different because of the extra synchronization=0D before a6xx_set_pagetable().=0D =0D Signed-off-by: Connor Abbott =0D ---=0D drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 34 ++++++++++++++++++++-----------= ---=0D 1 file changed, 20 insertions(+), 14 deletions(-)=0D =0D diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/ad= reno/a6xx_gpu.c=0D index b8f8ae940b55f5578abdbdec6bf1e90a53e721a5..794b79a6a4a1940c84709c32e89= 5b62b97f1ac5a 100644=0D --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c=0D +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c=0D @@ -216,15 +216,9 @@ static void a6xx_set_pagetable(struct a6xx_gpu *a6xx_g= pu,=0D return;=0D =0D if (adreno_gpu->info->family >=3D ADRENO_7XX_GEN1) {=0D - /* Wait for previous submit to complete before continuing: */=0D - OUT_PKT7(ring, CP_WAIT_TIMESTAMP, 4);=0D - OUT_RING(ring, 0);=0D - OUT_RING(ring, lower_32_bits(rbmemptr(ring, fence)));=0D - OUT_RING(ring, upper_32_bits(rbmemptr(ring, fence)));=0D - OUT_RING(ring, submit->seqno - 1);=0D -=0D + /* Sync both threads. */=0D OUT_PKT7(ring, CP_THREAD_CONTROL, 1);=0D - OUT_RING(ring, CP_SET_THREAD_BOTH);=0D + OUT_RING(ring, CP_THREAD_CONTROL_0_SYNC_THREADS | CP_SET_THREAD_BOTH);=0D =0D /* Reset state used to synchronize BR and BV */=0D OUT_PKT7(ring, CP_RESET_CONTEXT_STATE, 1);=0D @@ -234,8 +228,21 @@ static void a6xx_set_pagetable(struct a6xx_gpu *a6xx_g= pu,=0D CP_RESET_CONTEXT_STATE_0_CLEAR_BV_BR_COUNTER |=0D CP_RESET_CONTEXT_STATE_0_RESET_GLOBAL_LOCAL_TS);=0D =0D + /*=0D + * Toggle concurrent binning for pagetable switch and set the=0D + * thread to BR since only it can execute the pagetable switch=0D + * packets.=0D + */=0D OUT_PKT7(ring, CP_THREAD_CONTROL, 1);=0D - OUT_RING(ring, CP_SET_THREAD_BR);=0D + OUT_RING(ring, CP_THREAD_CONTROL_0_SYNC_THREADS | CP_SET_THREAD_BR);=0D +=0D + /* Wait for previous submit to complete before continuing: */=0D + OUT_PKT7(ring, CP_WAIT_TIMESTAMP, 4);=0D + OUT_RING(ring, 0);=0D + OUT_RING(ring, lower_32_bits(rbmemptr(ring, fence)));=0D + OUT_RING(ring, upper_32_bits(rbmemptr(ring, fence)));=0D + OUT_RING(ring, submit->seqno - 1);=0D +=0D }=0D =0D if (!sysprof) {=0D @@ -444,14 +451,13 @@ static void a7xx_submit(struct msm_gpu *gpu, struct m= sm_gem_submit *submit)=0D =0D adreno_check_and_reenable_stall(adreno_gpu);=0D =0D + a6xx_set_pagetable(a6xx_gpu, ring, submit);=0D +=0D /*=0D - * Toggle concurrent binning for pagetable switch and set the thread to=0D - * BR since only it can execute the pagetable switch packets.=0D + * Set pseudo register and get counters on BR.=0D */=0D OUT_PKT7(ring, CP_THREAD_CONTROL, 1);=0D - OUT_RING(ring, CP_THREAD_CONTROL_0_SYNC_THREADS | CP_SET_THREAD_BR);=0D -=0D - a6xx_set_pagetable(a6xx_gpu, ring, submit);=0D + OUT_RING(ring, CP_SET_THREAD_BR);=0D =0D /*=0D * If preemption is enabled, then set the pseudo register for the save=0D =0D ---=0D base-commit: b5bad77e1e3c7249e4c0c88f98477e1ee7669b63=0D change-id: 20251027-msm-less-bv-sync-ab03721d0a3b=0D =0D Best regards,=0D -- =0D Connor Abbott =0D =0D