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Thu, 06 Nov 2025 03:34:40 -0800 (PST) From: Bartosz Golaszewski Date: Thu, 06 Nov 2025 12:34:06 +0100 Subject: [PATCH v8 10/11] crypto: qce - Add support for BAM locking Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-Id: <20251106-qcom-qce-cmd-descr-v8-10-ecddca23ca26@linaro.org> References: <20251106-qcom-qce-cmd-descr-v8-0-ecddca23ca26@linaro.org> In-Reply-To: <20251106-qcom-qce-cmd-descr-v8-0-ecddca23ca26@linaro.org> To: Vinod Koul , Jonathan Corbet , Thara Gopinath , Herbert Xu , "David S. Miller" , Udit Tiwari , Daniel Perez-Zoghbi , Md Sadre Alam Cc: dmaengine@vger.kernel.org, linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-crypto@vger.kernel.org, Bartosz Golaszewski X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=3514; i=bartosz.golaszewski@linaro.org; h=from:subject:message-id; bh=0GwW+SMcBXkCtr2mAoPq27FNGWc61s6sW/IzW4L4/uU=; b=owEBbQKS/ZANAwAKARGnLqAUcddyAcsmYgBpDIe9jxDA/CEFJAoo8UbcYKvaZaTUhBnB1quRD FjDe4FqVeqJAjMEAAEKAB0WIQQWnetsC8PEYBPSx58Rpy6gFHHXcgUCaQyHvQAKCRARpy6gFHHX cgaWEACUGoEPNZS7SMnPFhtoZhThZ9zEq5xOPsFo8MfrPG2r/vmc7Hw+By35x9lVneRd9IiXm7I U1DiVTeo5hM8FaoFVEaBp2lK+SetYXhuKxCrakz7/9RQ75UBR2pA6luqPdp14Y4vWm+Gw8P7oZ8 sBvMPOSVifRN/GHqeCFSUIs77WnETvrzTaqNRJlfvIeC35eTfZqi2if1mgFHYcLiOmtPnKef92p GMugw4gfWP1AvgRT1aKo/nEWMnGmyAM0mNP/VgnC68qPkYuvlTjCX1KnjVSaS1a/ypaMIzf0GkT zRyApiBYc8Cwz/1M50PWvJ1FUamhUU88idKAE9kih0/Ufg7us9nfxfp3CNlOA4JqL2U1BUUaktZ zPMSaXLx4kRlusW/+5Mi/e6WmKseKH1YFzIo8wU72u2vADBisM9IxumkYQ7nhfxZPG+l4SpnzIW Rkmdzek/Zqt0CWrg6wiX8xuyEgEA13KlMi27fPLujHOnOFIpLlUzTOQmDavM/Te0ByR0NGz8gol Z+gPmFpUpVdNoF5GxkntlEVVpPC+gDkmB7hvzTqF5kj8Tn6Ab/HScZmZjHnmkxnAuxfip7FFZpK wxJILCw2LvKBefsrrUZmQvoEsICBl9Qqxg7lwGgJeE/Q6tK1OPi+q36faTuh0zxP5/cH9Mq4Xbr s/ZqmXoMy9Of+fQ== X-Developer-Key: i=bartosz.golaszewski@linaro.org; a=openpgp; fpr=169DEB6C0BC3C46013D2C79F11A72EA01471D772 From: Bartosz Golaszewski Implement the infrastructure for using the new DMA controller lock/unlock feature of the BAM driver. No functional change for now. Signed-off-by: Bartosz Golaszewski --- drivers/crypto/qce/common.c | 18 ++++++++++++++++++ drivers/crypto/qce/dma.c | 19 +++++++++++++++++-- drivers/crypto/qce/dma.h | 4 ++++ 3 files changed, 39 insertions(+), 2 deletions(-) diff --git a/drivers/crypto/qce/common.c b/drivers/crypto/qce/common.c index 04253a8d33409a2a51db527435d09ae85a7880af..74756c222fed6d0298eb6c957ed15b8b7083b72f 100644 --- a/drivers/crypto/qce/common.c +++ b/drivers/crypto/qce/common.c @@ -593,3 +593,21 @@ void qce_get_version(struct qce_device *qce, u32 *major, u32 *minor, u32 *step) *minor = (val & CORE_MINOR_REV_MASK) >> CORE_MINOR_REV_SHIFT; *step = (val & CORE_STEP_REV_MASK) >> CORE_STEP_REV_SHIFT; } + +int qce_bam_lock(struct qce_device *qce) +{ + qce_clear_bam_transaction(qce); + /* Dummy write to acquire the lock on the BAM pipe. */ + qce_write(qce, REG_AUTH_SEG_CFG, 0); + + return qce_submit_cmd_desc_lock(qce); +} + +int qce_bam_unlock(struct qce_device *qce) +{ + qce_clear_bam_transaction(qce); + /* Dummy write to release the lock on the BAM pipe. */ + qce_write(qce, REG_AUTH_SEG_CFG, 0); + + return qce_submit_cmd_desc_unlock(qce); +} diff --git a/drivers/crypto/qce/dma.c b/drivers/crypto/qce/dma.c index 9bb9a8246cb054dd16b9ab6cf5cfabef51b1ef83..bfdc1397a289b66af1ef482f0dda7aa057a9103d 100644 --- a/drivers/crypto/qce/dma.c +++ b/drivers/crypto/qce/dma.c @@ -41,13 +41,13 @@ void qce_clear_bam_transaction(struct qce_device *qce) bam_txn->pre_bam_ce_idx = 0; } -int qce_submit_cmd_desc(struct qce_device *qce) +static int qce_do_submit_cmd_desc(struct qce_device *qce, unsigned long flags) { struct qce_desc_info *qce_desc = qce->dma.bam_txn->desc; struct qce_bam_transaction *bam_txn = qce->dma.bam_txn; struct dma_async_tx_descriptor *dma_desc; struct dma_chan *chan = qce->dma.rxchan; - unsigned long attrs = DMA_PREP_CMD; + unsigned long attrs = DMA_PREP_CMD | flags; dma_cookie_t cookie; unsigned int mapped; int ret; @@ -76,6 +76,21 @@ int qce_submit_cmd_desc(struct qce_device *qce) return 0; } +int qce_submit_cmd_desc(struct qce_device *qce) +{ + return qce_do_submit_cmd_desc(qce, 0); +} + +int qce_submit_cmd_desc_lock(struct qce_device *qce) +{ + return qce_do_submit_cmd_desc(qce, DMA_PREP_LOCK); +} + +int qce_submit_cmd_desc_unlock(struct qce_device *qce) +{ + return qce_do_submit_cmd_desc(qce, DMA_PREP_UNLOCK); +} + static void qce_prep_dma_cmd_desc(struct qce_device *qce, struct qce_dma_data *dma, unsigned int addr, void *buf) { diff --git a/drivers/crypto/qce/dma.h b/drivers/crypto/qce/dma.h index f05dfa9e6b25bd60e32f45079a8bc7e6a4cf81f9..4b3ee17db72e29b9f417994477ad8a0ec2294db1 100644 --- a/drivers/crypto/qce/dma.h +++ b/drivers/crypto/qce/dma.h @@ -47,6 +47,10 @@ qce_sgtable_add(struct sg_table *sgt, struct scatterlist *sg_add, unsigned int max_len); void qce_write_dma(struct qce_device *qce, unsigned int offset, u32 val); int qce_submit_cmd_desc(struct qce_device *qce); +int qce_submit_cmd_desc_lock(struct qce_device *qce); +int qce_submit_cmd_desc_unlock(struct qce_device *qce); void qce_clear_bam_transaction(struct qce_device *qce); +int qce_bam_lock(struct qce_device *qce); +int qce_bam_unlock(struct qce_device *qce); #endif /* _DMA_H_ */ -- 2.51.0