From: David Heidelberg via B4 Relay <devnull+david.ixit.cz@kernel.org>
To: Robert Foss <rfoss@kernel.org>, Todor Tomov <todor.too@gmail.com>,
Bryan O'Donoghue <bryan.odonoghue@linaro.org>,
Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org>,
Mauro Carvalho Chehab <mchehab@kernel.org>,
Luca Weiss <luca.weiss@fairphone.com>,
Petr Hodina <phodina@protonmail.com>,
Casey Connolly <casey.connolly@linaro.org>,
"Dr. Git" <drgitx@gmail.com>
Cc: Joel Selvaraj <foss@joelselvaraj.com>,
linux-media@vger.kernel.org, linux-arm-msm@vger.kernel.org,
linux-kernel@vger.kernel.org, phone-devel@vger.kernel.org,
David Heidelberg <david@ixit.cz>
Subject: [PATCH RFC 5/8] media: qcom: camss: Initialize lanes after lane configuration is available
Date: Sun, 09 Nov 2025 10:39:48 +0100 [thread overview]
Message-ID: <20251109-qcom-cphy-v1-5-165f7e79b0e1@ixit.cz> (raw)
In-Reply-To: <20251109-qcom-cphy-v1-0-165f7e79b0e1@ixit.cz>
From: Petr Hodina <phodina@protonmail.com>
The lanes must not be initialized before the driver has access to
the lane configuration, as it depends on whether D-PHY or C-PHY mode
is in use. Move the lane initialization to a later stage where the
configuration structures are available.
Signed-off-by: Petr Hodina <phodina@protonmail.com>
Signed-off-by: David Heidelberg <david@ixit.cz>
---
.../platform/qcom/camss/camss-csiphy-3ph-1-0.c | 70 ++++++++++++----------
1 file changed, 37 insertions(+), 33 deletions(-)
diff --git a/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c b/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c
index 348b8cd18327e..c2adbde6b4e0d 100644
--- a/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c
+++ b/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c
@@ -1101,6 +1101,42 @@ static void csiphy_lanes_enable(struct csiphy_device *csiphy,
u8 val;
int i;
+ switch (csiphy->camss->res->version) {
+ case CAMSS_845:
+ regs->lane_regs = &lane_regs_sdm845[0];
+ regs->lane_array_size = ARRAY_SIZE(lane_regs_sdm845);
+ break;
+ case CAMSS_2290:
+ regs->lane_regs = &lane_regs_qcm2290[0];
+ regs->lane_array_size = ARRAY_SIZE(lane_regs_qcm2290);
+ break;
+ case CAMSS_7280:
+ case CAMSS_8250:
+ regs->lane_regs = &lane_regs_sm8250[0];
+ regs->lane_array_size = ARRAY_SIZE(lane_regs_sm8250);
+ break;
+ case CAMSS_8280XP:
+ regs->lane_regs = &lane_regs_sc8280xp[0];
+ regs->lane_array_size = ARRAY_SIZE(lane_regs_sc8280xp);
+ break;
+ case CAMSS_X1E80100:
+ case CAMSS_8550:
+ regs->offset = 0x1000;
+ break;
+ case CAMSS_8650:
+ regs->lane_regs = &lane_regs_sm8650[0];
+ regs->lane_array_size = ARRAY_SIZE(lane_regs_sm8650);
+ regs->offset = 0x1000;
+ break;
+ case CAMSS_8300:
+ case CAMSS_8775P:
+ regs->lane_regs = &lane_regs_sa8775p[0];
+ regs->lane_array_size = ARRAY_SIZE(lane_regs_sa8775p);
+ break;
+ default:
+ break;
+ }
+
settle_cnt = csiphy_settle_cnt_calc(link_freq, csiphy->timer_clk_rate);
if (c->cphy) {
@@ -1160,47 +1196,15 @@ static int csiphy_init(struct csiphy_device *csiphy)
return -ENOMEM;
csiphy->regs = regs;
- regs->offset = 0x800;
switch (csiphy->camss->res->version) {
- case CAMSS_845:
- regs->lane_regs = &lane_regs_sdm845[0];
- regs->lane_array_size = ARRAY_SIZE(lane_regs_sdm845);
- break;
- case CAMSS_2290:
- regs->lane_regs = &lane_regs_qcm2290[0];
- regs->lane_array_size = ARRAY_SIZE(lane_regs_qcm2290);
- break;
- case CAMSS_7280:
- case CAMSS_8250:
- regs->lane_regs = &lane_regs_sm8250[0];
- regs->lane_array_size = ARRAY_SIZE(lane_regs_sm8250);
- break;
- case CAMSS_8280XP:
- regs->lane_regs = &lane_regs_sc8280xp[0];
- regs->lane_array_size = ARRAY_SIZE(lane_regs_sc8280xp);
- break;
case CAMSS_X1E80100:
- regs->lane_regs = &lane_regs_x1e80100[0];
- regs->lane_array_size = ARRAY_SIZE(lane_regs_x1e80100);
- regs->offset = 0x1000;
- break;
case CAMSS_8550:
- regs->lane_regs = &lane_regs_sm8550[0];
- regs->lane_array_size = ARRAY_SIZE(lane_regs_sm8550);
- regs->offset = 0x1000;
- break;
case CAMSS_8650:
- regs->lane_regs = &lane_regs_sm8650[0];
- regs->lane_array_size = ARRAY_SIZE(lane_regs_sm8650);
regs->offset = 0x1000;
break;
- case CAMSS_8300:
- case CAMSS_8775P:
- regs->lane_regs = &lane_regs_sa8775p[0];
- regs->lane_array_size = ARRAY_SIZE(lane_regs_sa8775p);
- break;
default:
+ regs->offset = 0x800;
break;
}
--
2.51.0
next prev parent reply other threads:[~2025-11-09 9:40 UTC|newest]
Thread overview: 24+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-11-09 9:39 [PATCH RFC 0/8] media: camss: Add support for C-PHY configuration on Qualcomm platforms David Heidelberg via B4 Relay
2025-11-09 9:39 ` [PATCH RFC 1/8] media: qcom: camss: csiphy-3ph: Add Gen2 v1.1 MIPI CSI-2 CPHY init David Heidelberg via B4 Relay
2025-11-10 20:23 ` Vladimir Zapolskiy
2025-11-09 9:39 ` [PATCH RFC 2/8] media: qcom: camss: csiphy: Introduce C-PHY David Heidelberg via B4 Relay
2025-11-09 12:35 ` Casey Connolly
2025-11-10 11:35 ` Bryan O'Donoghue
2025-11-12 16:15 ` David Heidelberg
2025-11-13 9:27 ` Bryan O'Donoghue
2025-11-09 9:39 ` [PATCH RFC 3/8] media: qcom: camss: csiphy-3ph: Use odd bits for configuring C-PHY lanes David Heidelberg via B4 Relay
2025-11-09 9:49 ` David Heidelberg
2025-11-09 9:39 ` [PATCH RFC 4/8] media: qcom: camss: Prepare CSID for C-PHY support David Heidelberg via B4 Relay
2025-11-10 11:37 ` Bryan O'Donoghue
2025-12-01 20:30 ` David Heidelberg
2025-11-09 9:39 ` David Heidelberg via B4 Relay [this message]
2025-11-10 11:38 ` [PATCH RFC 5/8] media: qcom: camss: Initialize lanes after lane configuration is available Bryan O'Donoghue
2025-11-09 9:39 ` [PATCH RFC 6/8] media: qcom: camss: csiphy-3ph: Use sdm845 C-PHY configuration sequence David Heidelberg via B4 Relay
2025-11-10 11:40 ` Bryan O'Donoghue
2025-11-10 11:41 ` Luca Weiss
2025-11-09 9:39 ` [PATCH RFC 7/8] media: qcom: camss: Account for C-PHY when calculating link frequency David Heidelberg via B4 Relay
2025-11-09 12:42 ` Casey Connolly
2025-11-09 9:39 ` [PATCH RFC 8/8] media: qcom: camss: Remove D-PHY-only endpoint restriction David Heidelberg via B4 Relay
2025-11-09 12:43 ` Casey Connolly
2025-11-09 17:22 ` Luca Weiss
2025-11-09 12:49 ` [PATCH RFC 0/8] media: camss: Add support for C-PHY configuration on Qualcomm platforms Casey Connolly
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