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[129.46.96.20]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-7b0c9c09f22sm10565900b3a.20.2025.11.09.22.59.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 09 Nov 2025 22:59:46 -0800 (PST) From: Qiang Yu Date: Sun, 09 Nov 2025 22:59:42 -0800 Subject: [PATCH 3/5] PCI: dwc: Remove MSI/MSIX capability if iMSI-RX is used as MSI controller Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-Id: <20251109-remove_cap-v1-3-2208f46f4dc2@oss.qualcomm.com> References: <20251109-remove_cap-v1-0-2208f46f4dc2@oss.qualcomm.com> In-Reply-To: <20251109-remove_cap-v1-0-2208f46f4dc2@oss.qualcomm.com> To: Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , Manivannan Sadhasivam , Rob Herring , Bjorn Helgaas , Jingoo Han Cc: linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, Qiang Yu X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1762757982; l=2379; i=qiang.yu@oss.qualcomm.com; s=20250513; h=from:subject:message-id; bh=hqQvTcsdaEoA9+Xh3Z8OKwCXQnyyBaKEZqGjPB6mXCc=; b=a9TNQphv0olEWd4VZeZicZIvivZzIDMYwEDpaxxIOnLRVfiJaisq6pzmb71V78utdnylUOr5k l1B9B2hAcppCFWYavnsq836rkyolkarAOQc99T9xPK87VlrsLQifiEs X-Developer-Key: i=qiang.yu@oss.qualcomm.com; a=ed25519; pk=Rr94t+fykoieF1ngg/bXxEfr5KoQxeXPtYxM8fBQTAI= X-Proofpoint-ORIG-GUID: _GbJn6R7TdFshaSxDDeNpeeGoUk3tZ_u X-Authority-Analysis: v=2.4 cv=BfDVE7t2 c=1 sm=1 tr=0 ts=69118d63 cx=c_pps a=Qgeoaf8Lrialg5Z894R3/Q==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=IkcTkHD0fZMA:10 a=6UeiqGixMTsA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=EUspDBNiAAAA:8 a=q7mzEFEhQNumAzJHHS8A:9 a=QEXdDO2ut3YA:10 a=x9snwWr2DeNwDh03kgHS:22 X-Proofpoint-GUID: _GbJn6R7TdFshaSxDDeNpeeGoUk3tZ_u X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUxMTEwMDA1OSBTYWx0ZWRfX7pQXdS52ujbj CqJUz5Kv6nbeI4HbhrP7/mC/MYgV49m0aXZDJ1RhTxCztCNVzkSNxDSZV5smCBYj9Kw/hXdKkbd oQXX+4Ihbq3b+rvP+cBILLdLrmn6s2LEyMPWwZDcjtde4MkGCeyZVASy4bYoLIo/6k4JIFhprY7 UVXcmSX1Ew5nv8w6Wg64oSYMUaO1lhSSWyqLsaZug8jETL0tUVRS2K+GNTVPnpyN5SP1O2JkmZr +huCQepx3kbrE+g1E5rdroY8al7lZ1vN1iM0gXAfpR9lpit1OxidqNYQPost9ozc6bwrZCfnYnM 6LNmTMh0MTqOzAjgFOgiPo4FaAMuk9mKpdZExIuvrrZgUtTkN5u9o2TvvBbW8+pJKSPBW0MY6jF TPcfKUWZYm+QRBMhj70WEIxPhnzNNQ== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.100.49 definitions=2025-11-10_02,2025-11-06_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 priorityscore=1501 malwarescore=0 impostorscore=0 spamscore=0 phishscore=0 lowpriorityscore=0 clxscore=1015 adultscore=0 suspectscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2510240001 definitions=main-2511100059 Some platforms may not support ITS (Interrupt Translation Service) and MBI (Message Based Interrupt), or there are not enough available empty SPI lines for MBI, in which case the msi-map and msi-parent property will not be provided in device tree node. For those cases, the DWC PCIe driver defaults to using the iMSI-RX module as MSI controller. However, due to DWC IP design, iMSI-RX cannot generate MSI interrupts for Root Ports even when MSI is properly configured and supported as iMSI-RX will only monitor and intercept incoming MSI TLPs from PCIe link, but the memory write generated by Root Port are internal system bus transactions instead of PCIe TLPs, so they are ignored. This leads to interrupts such as PME, AER from the Root Port not received on the host and the users have to resort to workarounds such as passing "pcie_pme=nomsi" cmdline parameter. To ensure reliable interrupt handling, remove MSI and MSI-X capabilities from Root Ports when using iMSI-RX as MSI controller, which is indicated by has_msi_ctrl == true. This forces a fallback to INTx interrupts, eliminating the need for manual kernel command line workarounds. With this behavior: - Platforms with ITS/MBI support use ITS/MBI MSI for interrupts from all components. - Platforms without ITS/MBI support fall back to INTx for Root Ports and use iMSI-RX for other PCI devices. Signed-off-by: Qiang Yu --- drivers/pci/controller/dwc/pcie-designware-host.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c index 20c9333bcb1c4812e2fd96047a49944574df1e6f..3724aa7f9b356bfba33a6515e2c62a3170aef1e9 100644 --- a/drivers/pci/controller/dwc/pcie-designware-host.c +++ b/drivers/pci/controller/dwc/pcie-designware-host.c @@ -1083,6 +1083,16 @@ int dw_pcie_setup_rc(struct dw_pcie_rp *pp) dw_pcie_dbi_ro_wr_dis(pci); + /* + * If iMSI-RX module is used as the MSI controller, remove MSI and + * MSI-X capabilities from PCIe Root Ports to ensure fallback to INTx + * interrupt handling. + */ + if (pp->has_msi_ctrl) { + dw_pcie_remove_capability(pci, PCI_CAP_ID_MSI); + dw_pcie_remove_capability(pci, PCI_CAP_ID_MSIX); + } + return 0; } EXPORT_SYMBOL_GPL(dw_pcie_setup_rc); -- 2.34.1