From: David Heidelberg via B4 Relay <devnull+david.ixit.cz@kernel.org>
To: Robert Foss <rfoss@kernel.org>, Todor Tomov <todor.too@gmail.com>,
Bryan O'Donoghue <bryan.odonoghue@linaro.org>,
Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org>,
Mauro Carvalho Chehab <mchehab@kernel.org>,
Luca Weiss <luca.weiss@fairphone.com>,
Petr Hodina <phodina@protonmail.com>,
Casey Connolly <casey.connolly@linaro.org>,
"Dr. Git" <drgitx@gmail.com>
Cc: Joel Selvaraj <foss@joelselvaraj.com>,
Kieran Bingham <kbingham@kernel.org>,
Sakari Ailus <sakari.ailus@linux.intel.com>,
linux-media@vger.kernel.org, linux-arm-msm@vger.kernel.org,
linux-kernel@vger.kernel.org, phone-devel@vger.kernel.org,
David Heidelberg <david@ixit.cz>
Subject: [PATCH WIP v2 5/8] media: qcom: camss: csiphy-3ph: Add Gen2 v1.1 MIPI CSI-2 CPHY init
Date: Thu, 04 Dec 2025 17:32:39 +0100 [thread overview]
Message-ID: <20251204-qcom-cphy-v2-5-6b35ef8b071e@ixit.cz> (raw)
In-Reply-To: <20251204-qcom-cphy-v2-0-6b35ef8b071e@ixit.cz>
From: Casey Connolly <casey.connolly@linaro.org>
Add a PHY configuration sequence for the sdm845 which uses a Qualcomm
Gen 2 version 1.1 CSI-2 PHY.
The PHY can be configured as two phase or three phase in C-PHY or D-PHY
mode. This configuration supports three-phase C-PHY mode.
Signed-off-by: Casey Connolly <casey.connolly@linaro.org>
Reviewed-by: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org>
Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Co-developed-by: David Heidelberg <david@ixit.cz>
Signed-off-by: David Heidelberg <david@ixit.cz>
---
.../platform/qcom/camss/camss-csiphy-3ph-1-0.c | 74 +++++++++++++++++++++-
1 file changed, 72 insertions(+), 2 deletions(-)
diff --git a/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c b/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c
index 3d30cdce33f96..7121aa97a19c4 100644
--- a/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c
+++ b/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c
@@ -145,6 +145,7 @@ csiphy_lane_regs lane_regs_sa8775p[] = {
};
/* GEN2 1.0 2PH */
+/* 5 entries: clock + 4 lanes */
static const struct
csiphy_lane_regs lane_regs_sdm845[] = {
{0x0004, 0x0C, 0x00, CSIPHY_DEFAULT_PARAMS},
@@ -219,6 +220,69 @@ csiphy_lane_regs lane_regs_sdm845[] = {
{0x0664, 0x7F, 0x00, CSIPHY_DEFAULT_PARAMS},
};
+/* GEN2 1.0 3PH */
+/* 3 entries: 3 lanes (C-PHY) */
+static const struct
+csiphy_lane_regs lane_regs_sdm845_3ph[] = {
+ {0x015C, 0x43, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0168, 0xA0, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x016C, 0x25, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0104, 0x06, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x010C, 0x12, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE},
+ {0x0108, 0x00, 0x00, CSIPHY_SETTLE_CNT_HIGHER_BYTE},
+ {0x0114, 0x20, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0150, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0118, 0x3e, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x011C, 0x41, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0120, 0x41, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0124, 0x7F, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0128, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x012C, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0144, 0x12, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0160, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x01CC, 0x41, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0164, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x01DC, 0x51, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x035C, 0x43, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0368, 0xA0, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x036C, 0x25, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0304, 0x06, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x030C, 0x12, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE},
+ {0x0308, 0x00, 0x00, CSIPHY_SETTLE_CNT_HIGHER_BYTE},
+ {0x0314, 0x20, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0350, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0318, 0x3e, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x031C, 0x41, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0320, 0x41, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0324, 0x7F, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0328, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x032C, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0344, 0x12, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0360, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x03CC, 0x41, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0364, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x03DC, 0x51, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x055C, 0x43, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0568, 0xA0, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x056C, 0x25, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0504, 0x06, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x050C, 0x12, 0x00, CSIPHY_SETTLE_CNT_LOWER_BYTE},
+ {0x0508, 0x00, 0x00, CSIPHY_SETTLE_CNT_HIGHER_BYTE},
+ {0x0514, 0x20, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0550, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0518, 0x3e, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x051C, 0x41, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0520, 0x41, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0524, 0x7F, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0528, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x052C, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0544, 0x12, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0560, 0x02, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x05CC, 0x41, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x0564, 0x00, 0x00, CSIPHY_DEFAULT_PARAMS},
+ {0x05DC, 0x51, 0x00, CSIPHY_DEFAULT_PARAMS},
+};
+
/* GEN2 1.1 2PH */
static const struct
csiphy_lane_regs lane_regs_sc8280xp[] = {
@@ -1043,8 +1107,14 @@ static void csiphy_lanes_enable(struct csiphy_device *csiphy,
switch (csiphy->camss->res->version) {
case CAMSS_845:
- regs->lane_regs = &lane_regs_sdm845[0];
- regs->lane_array_size = ARRAY_SIZE(lane_regs_sdm845);
+ if (c->phy_cfg == V4L2_MBUS_CSI2_CPHY) {
+ regs->lane_regs = &lane_regs_sdm845_3ph[0];
+ regs->lane_array_size = ARRAY_SIZE(lane_regs_sdm845_3ph);
+
+ } else { /* V4L2_MBUS_CSI2_DPHY */
+ regs->lane_regs = &lane_regs_sdm845[0];
+ regs->lane_array_size = ARRAY_SIZE(lane_regs_sdm845);
+ }
break;
case CAMSS_2290:
regs->lane_regs = &lane_regs_qcm2290[0];
--
2.51.0
next prev parent reply other threads:[~2025-12-04 16:32 UTC|newest]
Thread overview: 22+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-12-04 16:32 [PATCH WIP v2 0/8] media: camss: Add support for C-PHY configuration on Qualcomm platforms David Heidelberg via B4 Relay
2025-12-04 16:32 ` [PATCH WIP v2 1/8] media: qcom: camss: csiphy: Introduce PHY configuration David Heidelberg via B4 Relay
2025-12-04 16:32 ` [PATCH WIP v2 2/8] media: qcom: camss: csiphy-3ph: Use odd bits for configuring C-PHY lanes David Heidelberg via B4 Relay
2025-12-05 10:33 ` Bryan O'Donoghue
2025-12-05 11:59 ` David Heidelberg
2025-12-04 16:32 ` [PATCH WIP v2 3/8] media: qcom: camss: Prepare CSID for C-PHY support David Heidelberg via B4 Relay
2025-12-05 9:43 ` Konrad Dybcio
2025-12-11 15:20 ` David Heidelberg
2025-12-04 16:32 ` [PATCH WIP v2 4/8] media: qcom: camss: Initialize lanes after lane configuration is available David Heidelberg via B4 Relay
2025-12-04 16:32 ` David Heidelberg via B4 Relay [this message]
2025-12-05 9:54 ` [PATCH WIP v2 5/8] media: qcom: camss: csiphy-3ph: Add Gen2 v1.1 MIPI CSI-2 CPHY init Konrad Dybcio
2025-12-05 11:56 ` David Heidelberg
2025-12-05 12:00 ` Konrad Dybcio
2025-12-05 12:11 ` David Heidelberg
2025-12-04 16:32 ` [PATCH WIP v2 6/8] media: qcom: camss: csiphy-3ph: Add Gen2 v1.2.1 MIPI CSI-2 C-PHY init David Heidelberg via B4 Relay
2025-12-05 9:59 ` Konrad Dybcio
2025-12-04 16:32 ` [PATCH WIP v2 7/8] media: qcom: camss: csiphy-3ph: C-PHY needs own lane configuration David Heidelberg via B4 Relay
2025-12-05 10:01 ` Konrad Dybcio
2025-12-05 10:38 ` Bryan O'Donoghue
2025-12-05 10:39 ` Bryan O'Donoghue
2025-12-04 16:32 ` [PATCH WIP v2 8/8] media: qcom: camss: Account for C-PHY when calculating link frequency David Heidelberg via B4 Relay
2025-12-06 6:55 ` kernel test robot
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