From: David Heidelberg via B4 Relay <devnull+david.ixit.cz@kernel.org>
To: Robert Foss <rfoss@kernel.org>, Todor Tomov <todor.too@gmail.com>,
Bryan O'Donoghue <bryan.odonoghue@linaro.org>,
Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org>,
Mauro Carvalho Chehab <mchehab@kernel.org>,
Luca Weiss <luca.weiss@fairphone.com>,
Petr Hodina <phodina@protonmail.com>,
Casey Connolly <casey.connolly@linaro.org>,
"Dr. Git" <drgitx@gmail.com>
Cc: Joel Selvaraj <foss@joelselvaraj.com>,
Kieran Bingham <kbingham@kernel.org>,
Sakari Ailus <sakari.ailus@linux.intel.com>,
linux-media@vger.kernel.org, linux-arm-msm@vger.kernel.org,
linux-kernel@vger.kernel.org, phone-devel@vger.kernel.org,
David Heidelberg <david@ixit.cz>
Subject: [PATCH WIP v2 7/8] media: qcom: camss: csiphy-3ph: C-PHY needs own lane configuration
Date: Thu, 04 Dec 2025 17:32:41 +0100 [thread overview]
Message-ID: <20251204-qcom-cphy-v2-7-6b35ef8b071e@ixit.cz> (raw)
In-Reply-To: <20251204-qcom-cphy-v2-0-6b35ef8b071e@ixit.cz>
From: David Heidelberg <david@ixit.cz>
Make sure we have proper lane registers definition in-place for each
generation, otherwise C-PHY won't work.
Signed-off-by: David Heidelberg <david@ixit.cz>
---
.../platform/qcom/camss/camss-csiphy-3ph-1-0.c | 48 ++++++++++++++++------
1 file changed, 36 insertions(+), 12 deletions(-)
diff --git a/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c b/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c
index 6d6dd54c5ac9c..c957f7dbfb243 100644
--- a/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c
+++ b/drivers/media/platform/qcom/camss/camss-csiphy-3ph-1-0.c
@@ -1222,8 +1222,12 @@ static void csiphy_lanes_enable(struct csiphy_device *csiphy,
}
break;
case CAMSS_2290:
- regs->lane_regs = &lane_regs_qcm2290[0];
- regs->lane_array_size = ARRAY_SIZE(lane_regs_qcm2290);
+ if (c->phy_cfg == V4L2_MBUS_CSI2_CPHY) {
+ dev_err(dev, "Missing lane_regs definition for %d\n", c->phy_cfg);
+ } else { /* V4L2_MBUS_CSI2_DPHY */
+ regs->lane_regs = &lane_regs_qcm2290[0];
+ regs->lane_array_size = ARRAY_SIZE(lane_regs_qcm2290);
+ }
break;
case CAMSS_7280:
case CAMSS_8250:
@@ -1236,25 +1240,45 @@ static void csiphy_lanes_enable(struct csiphy_device *csiphy,
}
break;
case CAMSS_8280XP:
- regs->lane_regs = &lane_regs_sc8280xp[0];
- regs->lane_array_size = ARRAY_SIZE(lane_regs_sc8280xp);
+ if (c->phy_cfg == V4L2_MBUS_CSI2_CPHY) {
+ dev_err(dev, "Missing lane_regs definition for %d\n", c->phy_cfg);
+ } else { /* V4L2_MBUS_CSI2_DPHY */
+ regs->lane_regs = &lane_regs_sc8280xp[0];
+ regs->lane_array_size = ARRAY_SIZE(lane_regs_sc8280xp);
+ }
break;
case CAMSS_X1E80100:
- regs->lane_regs = &lane_regs_x1e80100[0];
- regs->lane_array_size = ARRAY_SIZE(lane_regs_x1e80100);
+ if (c->phy_cfg == V4L2_MBUS_CSI2_CPHY) {
+ dev_err(dev, "Missing lane_regs definition for %d\n", c->phy_cfg);
+ } else { /* V4L2_MBUS_CSI2_DPHY */
+ regs->lane_regs = &lane_regs_x1e80100[0];
+ regs->lane_array_size = ARRAY_SIZE(lane_regs_x1e80100);
+ }
break;
case CAMSS_8550:
- regs->lane_regs = &lane_regs_sm8550[0];
- regs->lane_array_size = ARRAY_SIZE(lane_regs_sm8550);
+ if (c->phy_cfg == V4L2_MBUS_CSI2_CPHY) {
+ dev_err(dev, "Missing lane_regs definition for %d\n", c->phy_cfg);
+ } else { /* V4L2_MBUS_CSI2_DPHY */
+ regs->lane_regs = &lane_regs_sm8550[0];
+ regs->lane_array_size = ARRAY_SIZE(lane_regs_sm8550);
+ }
break;
case CAMSS_8650:
- regs->lane_regs = &lane_regs_sm8650[0];
- regs->lane_array_size = ARRAY_SIZE(lane_regs_sm8650);
+ if (c->phy_cfg == V4L2_MBUS_CSI2_CPHY) {
+ dev_err(dev, "Missing lane_regs definition for %d\n", c->phy_cfg);
+ } else { /* V4L2_MBUS_CSI2_DPHY */
+ regs->lane_regs = &lane_regs_sm8650[0];
+ regs->lane_array_size = ARRAY_SIZE(lane_regs_sm8650);
+ }
break;
case CAMSS_8300:
case CAMSS_8775P:
- regs->lane_regs = &lane_regs_sa8775p[0];
- regs->lane_array_size = ARRAY_SIZE(lane_regs_sa8775p);
+ if (c->phy_cfg == V4L2_MBUS_CSI2_CPHY) {
+ dev_err(dev, "Missing lane_regs definition for %d\n", c->phy_cfg);
+ } else { /* V4L2_MBUS_CSI2_DPHY */
+ regs->lane_regs = &lane_regs_sa8775p[0];
+ regs->lane_array_size = ARRAY_SIZE(lane_regs_sa8775p);
+ }
break;
default:
break;
--
2.51.0
next prev parent reply other threads:[~2025-12-04 16:32 UTC|newest]
Thread overview: 22+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-12-04 16:32 [PATCH WIP v2 0/8] media: camss: Add support for C-PHY configuration on Qualcomm platforms David Heidelberg via B4 Relay
2025-12-04 16:32 ` [PATCH WIP v2 1/8] media: qcom: camss: csiphy: Introduce PHY configuration David Heidelberg via B4 Relay
2025-12-04 16:32 ` [PATCH WIP v2 2/8] media: qcom: camss: csiphy-3ph: Use odd bits for configuring C-PHY lanes David Heidelberg via B4 Relay
2025-12-05 10:33 ` Bryan O'Donoghue
2025-12-05 11:59 ` David Heidelberg
2025-12-04 16:32 ` [PATCH WIP v2 3/8] media: qcom: camss: Prepare CSID for C-PHY support David Heidelberg via B4 Relay
2025-12-05 9:43 ` Konrad Dybcio
2025-12-11 15:20 ` David Heidelberg
2025-12-04 16:32 ` [PATCH WIP v2 4/8] media: qcom: camss: Initialize lanes after lane configuration is available David Heidelberg via B4 Relay
2025-12-04 16:32 ` [PATCH WIP v2 5/8] media: qcom: camss: csiphy-3ph: Add Gen2 v1.1 MIPI CSI-2 CPHY init David Heidelberg via B4 Relay
2025-12-05 9:54 ` Konrad Dybcio
2025-12-05 11:56 ` David Heidelberg
2025-12-05 12:00 ` Konrad Dybcio
2025-12-05 12:11 ` David Heidelberg
2025-12-04 16:32 ` [PATCH WIP v2 6/8] media: qcom: camss: csiphy-3ph: Add Gen2 v1.2.1 MIPI CSI-2 C-PHY init David Heidelberg via B4 Relay
2025-12-05 9:59 ` Konrad Dybcio
2025-12-04 16:32 ` David Heidelberg via B4 Relay [this message]
2025-12-05 10:01 ` [PATCH WIP v2 7/8] media: qcom: camss: csiphy-3ph: C-PHY needs own lane configuration Konrad Dybcio
2025-12-05 10:38 ` Bryan O'Donoghue
2025-12-05 10:39 ` Bryan O'Donoghue
2025-12-04 16:32 ` [PATCH WIP v2 8/8] media: qcom: camss: Account for C-PHY when calculating link frequency David Heidelberg via B4 Relay
2025-12-06 6:55 ` kernel test robot
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