From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3A0AB242D79; Mon, 8 Dec 2025 19:11:12 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1765221073; cv=none; b=YJZXuasRga2CIj7JYVkjcq3j0FB20JtD4VHSqK2+YlrWVzWgQRcNCqRYOhPe2qWhKH3wpOVJ+F9YMOHUKxmXFLfSBVjadmL3hztUmL5DXhlXIP8XWfcg3HvXABVGe7Qq1hmQxEreCYJuvl5tAvkYREOa7xfbjnFI/Uic5C98C/g= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1765221073; c=relaxed/simple; bh=qA200K7aoJ1D07Oig2GNEZ+7d43xuiwI5ZAaPd2N0HA=; h=Date:From:To:Cc:Subject:Message-ID:References:MIME-Version: Content-Type:Content-Disposition:In-Reply-To; b=LqllsJrkKRuXeB7M2LheG90xeJ3povGuq8OwNgKoy4g1wIiPDFfr7Y0N5t466R4X/XWK/En/LrHteJH4K5ngas5W0iZvBhAQOmxsmqOvPm2F8SjGz825nGtNiJLzKwE+QFkbyg6yIhO3UFFjDL1t7PH9Z+a4nRsraGvfegDh03I= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=NlB8DKtG; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="NlB8DKtG" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 80883C4CEF1; Mon, 8 Dec 2025 19:11:12 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1765221072; bh=qA200K7aoJ1D07Oig2GNEZ+7d43xuiwI5ZAaPd2N0HA=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=NlB8DKtGOG0T/XaVEoYJGV41lqPuxUliaXSAh1m3LBjHCG6y33dMW1qqoMr+d84de GGLhfiNORkGWPD5mPVzwNQBy24CbI4SkpUupBD4NJ8OjLad4JjqEDLK7WkdisD2Lwf U9DMY2unyh3P8VfF0j5KF8Ww65syU2rKPi1A5k3/CL6+uH2RbEdGuHf6oxk9qhTsfW 4ShgPVynPhzLFaZ2G3CtaublU6x48EgQHvEAl5dxo2LPmIiLtGoX/3T0WX6O5Cxohl I5Dwz9ErdGUNH4l1W1qvWRAcPISV7e0I9G+p5YlJGjWVesGr47HXcP0nKqLlxROlcb 1CHlIRQlGjIIA== Date: Mon, 8 Dec 2025 13:11:10 -0600 From: Rob Herring To: Manivannan Sadhasivam Cc: Bjorn Helgaas , Manivannan Sadhasivam , Krzysztof Kozlowski , Conor Dooley , Bartosz Golaszewski , linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org, Stephan Gerhold , Dmitry Baryshkov , linux-pm@vger.kernel.org, Frank Li Subject: Re: [PATCH v3 1/4] dt-bindings: connector: Add PCIe M.2 Mechanical Key M connector Message-ID: <20251208191110.GA2473021-robh@kernel.org> References: <20251125-pci-m2-v3-0-c528042aea47@oss.qualcomm.com> <20251125-pci-m2-v3-1-c528042aea47@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20251125-pci-m2-v3-1-c528042aea47@oss.qualcomm.com> On Tue, Nov 25, 2025 at 04:42:26PM +0530, Manivannan Sadhasivam wrote: > Add the devicetree binding for PCIe M.2 Mechanical Key M connector defined > in the PCI Express M.2 Specification, r4.0, sec 5.3. This connector > provides interfaces like PCIe and SATA to attach the Solid State Drives > (SSDs) to the host machine along with additional interfaces like USB, and > SMB for debugging and supplementary features. At any point of time, the > connector can only support either PCIe or SATA as the primary host > interface. > > The connector provides a primary power supply of 3.3v, along with an > optional 1.8v VIO supply for the Adapter I/O buffer circuitry operating at > 1.8v sideband signaling. > > The connector also supplies optional signals in the form of GPIOs for fine > grained power management. > > Reviewed-by: Frank Li > Signed-off-by: Manivannan Sadhasivam > --- > .../bindings/connector/pcie-m2-m-connector.yaml | 141 +++++++++++++++++++++ > 1 file changed, 141 insertions(+) > > diff --git a/Documentation/devicetree/bindings/connector/pcie-m2-m-connector.yaml b/Documentation/devicetree/bindings/connector/pcie-m2-m-connector.yaml > new file mode 100644 > index 000000000000..f65a05d93735 > --- /dev/null > +++ b/Documentation/devicetree/bindings/connector/pcie-m2-m-connector.yaml > @@ -0,0 +1,141 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/connector/pcie-m2-m-connector.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: PCIe M.2 Mechanical Key M Connector > + > +maintainers: > + - Manivannan Sadhasivam > + > +description: > + A PCIe M.2 M connector node represents a physical PCIe M.2 Mechanical Key M > + connector. The Mechanical Key M connectors are used to connect SSDs to the > + host system over PCIe/SATA interfaces. These connectors also offer optional > + interfaces like USB, SMB. > + > +properties: > + compatible: > + const: pcie-m2-m-connector > + > + vpcie3v3-supply: > + description: A phandle to the regulator for 3.3v supply. > + > + vpcie1v8-supply: > + description: A phandle to the regulator for VIO 1.8v supply. > + > + ports: > + $ref: /schemas/graph.yaml#/properties/ports > + description: OF graph bindings modeling the interfaces exposed on the > + connector. Since a single connector can have multiple interfaces, every > + interface has an assigned OF graph port number as described below. > + > + properties: > + port@0: > + $ref: /schemas/graph.yaml#/properties/port > + description: Host interfaces of the connector > + > + properties: > + endpoint@0: > + $ref: /schemas/graph.yaml#/properties/endpoint > + description: PCIe interface > + > + endpoint@1: > + $ref: /schemas/graph.yaml#/properties/endpoint > + description: SATA interface Where's the binding changes to allow graph nodes on SATA and PCIe bindings? I suppose Thunderbolt/USB4 on USB-C connectors will need that too. > + > + anyOf: > + - required: > + - endpoint@0 > + - required: > + - endpoint@1 > + > + port@1: > + $ref: /schemas/graph.yaml#/properties/port > + description: USB 2.0 interface > + > + port@2: > + $ref: /schemas/graph.yaml#/properties/port > + description: SMB interface SMB is SMBus? There's no graph support for I2C either. For that, we use 'i2c-parent'. > + > + required: > + - port@0 > + > + clocks: > + description: 32.768 KHz Suspend Clock (SUSCLK) input from the host system to > + the M.2 card. Refer, PCI Express M.2 Specification r4.0, sec 3.1.12.1 for > + more details. > + maxItems: 1 > + > + pedet-gpios: > + description: GPIO controlled connection to PEDET signal. This signal is used Instead of 'controlled connection' use just input or output. Arguably an input isn't GPIO controlled. > + by the host systems to determine the communication protocol that the M.2 > + card uses; SATA signaling (low) or PCIe signaling (high). Refer, PCI > + Express M.2 Specification r4.0, sec 3.3.4.2 for more details. > + maxItems: 1 > + > + led1-gpios: > + description: GPIO controlled connection to LED_1# signal. This signal is > + used by the M.2 card to indicate the card status via the system mounted > + LED. Refer, PCI Express M.2 Specification r4.0, sec 3.1.12.2 for more > + details. > + maxItems: 1 > + > + viocfg-gpios: > + description: GPIO controlled connection to IO voltage configuration > + (VIO_CFG) signal. This signal is used by the M.2 card to indicate to the > + host system that the card supports an independent IO voltage domain for > + the sideband signals. Refer, PCI Express M.2 Specification r4.0, sec > + 3.1.15.1 for more details. > + maxItems: 1 > + > + pwrdis-gpios: > + description: GPIO controlled connection to Power Disable (PWRDIS) signal. > + This signal is used by the host system to disable power on the M.2 card. > + Refer, PCI Express M.2 Specification r4.0, sec 3.3.5.2 for more details. > + maxItems: 1 > + > + pln-gpios: > + description: GPIO controlled connection to Power Loss Notification (PLN#) > + signal. This signal is use to notify the M.2 card by the host system that > + the power loss event is expected to occur. Refer, PCI Express M.2 > + Specification r4.0, sec 3.2.17.1 for more details. > + maxItems: 1 > + > + plas3-gpios: > + description: GPIO controlled connection to Power Loss Acknowledge (PLA_S3#) > + signal. This signal is used by the M.2 card to notify the host system, the > + status of the M.2 card's preparation for power loss. > + maxItems: 1 > + > +required: > + - compatible > + - vpcie3v3-supply > + > +additionalProperties: false > + > +examples: > + # PCI M.2 Key M connector for SSDs with PCIe interface > + - | > + connector { > + compatible = "pcie-m2-m-connector"; > + vpcie3v3-supply = <&vreg_nvme>; > + > + ports { > + #address-cells = <1>; > + #size-cells = <0>; > + > + port@0 { > + #address-cells = <1>; > + #size-cells = <0>; > + > + reg = <0>; > + > + endpoint@0 { > + reg = <0>; > + remote-endpoint = <&pcie6_port0_ep>; > + }; > + }; > + }; > + }; > > -- > 2.48.1 >