From: Xiangxu Yin via B4 Relay <devnull+xiangxu.yin.oss.qualcomm.com@kernel.org>
To: Vinod Koul <vkoul@kernel.org>,
Neil Armstrong <neil.armstrong@linaro.org>,
Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>
Cc: linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
fange.zhang@oss.qualcomm.com, yongxing.mou@oss.qualcomm.com,
li.liu@oss.qualcomm.com, tingwei.zhang@oss.qualcomm.com,
Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>,
Bjorn Andersson <andersson@kernel.org>,
Konrad Dybcio <konradybcio@kernel.org>,
Xiangxu Yin <xiangxu.yin@oss.qualcomm.com>
Subject: [PATCH v8 07/12] phy: qcom: qmp-usbc: Move USB-only init to usb_power_on
Date: Mon, 15 Dec 2025 20:42:03 +0800 [thread overview]
Message-ID: <20251215-add-displayport-support-for-qcs615-platform-v8-7-cbc72c88a44e@oss.qualcomm.com> (raw)
In-Reply-To: <20251215-add-displayport-support-for-qcs615-platform-v8-0-cbc72c88a44e@oss.qualcomm.com>
From: Xiangxu Yin <xiangxu.yin@oss.qualcomm.com>
The current implementation programs USB-specific registers in
qmp_usbc_com_init(), which is shared by both USB and DP modes. This
causes unnecessary configuration when the PHY is used for DP.
Move USB-only register setup from com_init to qmp_usbc_usb_power_on,
so it runs only for USB mode.
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Signed-off-by: Xiangxu Yin <xiangxu.yin@oss.qualcomm.com>
---
drivers/phy/qualcomm/phy-qcom-qmp-usbc.c | 22 ++++++++++------------
1 file changed, 10 insertions(+), 12 deletions(-)
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-usbc.c b/drivers/phy/qualcomm/phy-qcom-qmp-usbc.c
index a6431e6d5586..c8e0f9574ba6 100644
--- a/drivers/phy/qualcomm/phy-qcom-qmp-usbc.c
+++ b/drivers/phy/qualcomm/phy-qcom-qmp-usbc.c
@@ -30,6 +30,8 @@
#include "phy-qcom-qmp-pcs-misc-v3.h"
#define PHY_INIT_COMPLETE_TIMEOUT 10000
+#define SW_PORTSELECT_VAL BIT(0)
+#define SW_PORTSELECT_MUX BIT(1)
/* set of registers with offsets different per-PHY */
enum qphy_reg_layout {
@@ -531,8 +533,6 @@ static int qmp_usbc_com_init(struct phy *phy)
{
struct qmp_usbc *qmp = phy_get_drvdata(phy);
const struct qmp_phy_cfg *cfg = qmp->cfg;
- void __iomem *pcs = qmp->pcs;
- u32 val = 0;
int ret;
ret = regulator_bulk_enable(cfg->num_vregs, qmp->vregs);
@@ -557,16 +557,6 @@ static int qmp_usbc_com_init(struct phy *phy)
if (ret)
goto err_assert_reset;
- qphy_setbits(pcs, cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL], SW_PWRDN);
-
-#define SW_PORTSELECT_VAL BIT(0)
-#define SW_PORTSELECT_MUX BIT(1)
- /* Use software based port select and switch on typec orientation */
- val = SW_PORTSELECT_MUX;
- if (qmp->orientation == TYPEC_ORIENTATION_REVERSE)
- val |= SW_PORTSELECT_VAL;
- writel(val, qmp->pcs_misc);
-
return 0;
err_assert_reset:
@@ -599,6 +589,14 @@ static int qmp_usbc_usb_power_on(struct phy *phy)
unsigned int val;
int ret;
+ qphy_setbits(qmp->pcs, cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL], SW_PWRDN);
+
+ /* Use software based port select and switch on typec orientation */
+ val = SW_PORTSELECT_MUX;
+ if (qmp->orientation == TYPEC_ORIENTATION_REVERSE)
+ val |= SW_PORTSELECT_VAL;
+ writel(val, qmp->pcs_misc);
+
qmp_configure(qmp->dev, qmp->serdes, cfg->serdes_tbl,
cfg->serdes_tbl_num);
--
2.34.1
next prev parent reply other threads:[~2025-12-15 12:42 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-12-15 12:41 [PATCH v8 00/12] Add DisplayPort support for QCS615 platform Xiangxu Yin via B4 Relay
2025-12-15 12:41 ` [PATCH v8 01/12] dt-bindings: phy: Add QMP USB3+DP PHY for QCS615 Xiangxu Yin via B4 Relay
2025-12-15 12:41 ` [PATCH v8 02/12] phy: qcom: qmp-usbc: Rename USB-specific ops to prepare for DP support Xiangxu Yin via B4 Relay
2025-12-15 12:41 ` [PATCH v8 03/12] phy: qcom: qmp-usbc: Add DP-related fields for USB/DP switchable PHY Xiangxu Yin via B4 Relay
2025-12-15 12:42 ` [PATCH v8 04/12] phy: qcom: qmp-usbc: Add regulator init_load support Xiangxu Yin via B4 Relay
2025-12-15 12:42 ` [PATCH v8 05/12] phy: qcom: qmp-usbc: Move reset config into PHY cfg Xiangxu Yin via B4 Relay
2025-12-15 12:42 ` [PATCH v8 06/12] phy: qcom: qmp-usbc: add DP link and vco_div clocks for DP PHY Xiangxu Yin via B4 Relay
2025-12-15 12:42 ` Xiangxu Yin via B4 Relay [this message]
2025-12-15 12:42 ` [PATCH v8 08/12] phy: qcom: qmp-usbc: Add TCSR parsing and PHY mode setting Xiangxu Yin via B4 Relay
2025-12-15 12:42 ` [PATCH v8 09/12] phy: qcom: qmp-usbc: Add DP PHY ops for USB/DP switchable Type-C PHYs Xiangxu Yin via B4 Relay
2025-12-15 12:42 ` [PATCH v8 10/12] phy: qcom: qmp-usbc: Add USB/DP exclude handling Xiangxu Yin via B4 Relay
2025-12-15 12:42 ` [PATCH v8 11/12] phy: qcom: qmp: Add DP v2 PHY register definitions Xiangxu Yin via B4 Relay
2025-12-15 12:42 ` [PATCH v8 12/12] phy: qcom: qmp-usbc: Add QCS615 USB/DP PHY config and DP mode support Xiangxu Yin via B4 Relay
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