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Mon, 05 Jan 2026 06:47:16 -0800 (PST) X-Google-Smtp-Source: AGHT+IEC0ntpKtEblnNYcl3KPIbge9nxcKn7exCL5e75nVmgyPbQLMaOfTGf4/gEXkYBasPUBxvShA== X-Received: by 2002:a17:90b:54c3:b0:34c:2f3f:d27e with SMTP id 98e67ed59e1d1-34e92113230mr40041974a91.3.1767624435695; Mon, 05 Jan 2026 06:47:15 -0800 (PST) Received: from hu-pragalla-hyd.qualcomm.com ([202.46.23.25]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-34f476ec311sm6634868a91.4.2026.01.05.06.47.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 05 Jan 2026 06:47:15 -0800 (PST) From: Pradeep P V K To: vkoul@kernel.org, neil.armstrong@linaro.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, martin.petersen@oracle.com, andersson@kernel.org, konradybcio@kernel.org, taniya.das@oss.qualcomm.com, dmitry.baryshkov@oss.qualcomm.com, manivannan.sadhasivam@oss.qualcomm.com Cc: linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-scsi@vger.kernel.org, nitin.rawat@oss.qualcomm.com, Pradeep P V K , Konrad Dybcio , Abel Vesa Subject: [PATCH V3 3/4] arm64: dts: qcom: hamoa: Add UFS nodes for x1e80100 SoC Date: Mon, 5 Jan 2026 20:16:42 +0530 Message-Id: <20260105144643.669344-4-pradeep.pragallapati@oss.qualcomm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20260105144643.669344-1-pradeep.pragallapati@oss.qualcomm.com> References: <20260105144643.669344-1-pradeep.pragallapati@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwMTA1MDEyOSBTYWx0ZWRfX4Zdzi78vPRsJ qo2PGtUeLn6Q7m73gv+o6uzGwB4NPslYkNFVfm0Vly4kcNDTn8P23y7el+foY/uJTf+LdnqkVF3 CtQwj+HFVukV78XcSt92ux9FHwjtv1wBC+hoAxs24rlND+JqwMTChakDnMs563BaXclqSSeZboZ Phf7vl+9PYmyRLD6bzrGQbJ86v0oCY3T1DuFgmAaE0HIqUMhi25d73lsKwMectqRyoeDspPtQJB bs/0cFNbATwuyfph/eBnPqItkHKqBp8ySzwoqwr46B4C6FeiCFo5dN/8uc7Ke4b4oDEs8wnTp2u V3Q4v0Slx0wLYzibpWshrKI8KldCPooRtH6feYzntDGoxQ05x0NrVajysendVrOcbfpwNa25bPD nFX9rSYDTiXqvnlRGSgzz57K5TnrzM2VbLkFz2F/JCGEfPA7egJIt1gJr1urJLAUFGnpVc3ilwm RdvsE4PxsTd2+sVzCiQ== X-Proofpoint-ORIG-GUID: znky9Xcq1xRjJYlaiLogUkk6sXXy1ywM X-Authority-Analysis: v=2.4 cv=c4ymgB9l c=1 sm=1 tr=0 ts=695bcef5 cx=c_pps a=vVfyC5vLCtgYJKYeQD43oA==:117 a=ZePRamnt/+rB5gQjfz0u9A==:17 a=vUbySO9Y5rIA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=EUspDBNiAAAA:8 a=-wAyGzpI3j0i2zLxvnIA:9 a=rl5im9kqc5Lf4LNbBjHf:22 X-Proofpoint-GUID: znky9Xcq1xRjJYlaiLogUkk6sXXy1ywM X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1121,Hydra:6.1.9,FMLib:17.12.100.49 definitions=2026-01-05_01,2026-01-05_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 suspectscore=0 adultscore=0 clxscore=1015 bulkscore=0 impostorscore=0 priorityscore=1501 phishscore=0 spamscore=0 malwarescore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2512120000 definitions=main-2601050129 Add UFS host controller and PHY nodes for x1e80100 SoC. Reviewed-by: Konrad Dybcio Reviewed-by: Abel Vesa Reviewed-by: Taniya Das Signed-off-by: Pradeep P V K --- arch/arm64/boot/dts/qcom/hamoa.dtsi | 123 +++++++++++++++++++++++++++- 1 file changed, 120 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/hamoa.dtsi b/arch/arm64/boot/dts/qcom/hamoa.dtsi index f7d71793bc77..33899fa06aa4 100644 --- a/arch/arm64/boot/dts/qcom/hamoa.dtsi +++ b/arch/arm64/boot/dts/qcom/hamoa.dtsi @@ -835,9 +835,9 @@ gcc: clock-controller@100000 { <0>, <0>, <0>, - <0>, - <0>, - <0>; + <&ufs_mem_phy 0>, + <&ufs_mem_phy 1>, + <&ufs_mem_phy 2>; power-domains = <&rpmhpd RPMHPD_CX>; #clock-cells = <1>; @@ -3848,6 +3848,123 @@ pcie4_phy: phy@1c0e000 { status = "disabled"; }; + ufs_mem_phy: phy@1d80000 { + compatible = "qcom,x1e80100-qmp-ufs-phy", + "qcom,sm8550-qmp-ufs-phy"; + reg = <0x0 0x01d80000 0x0 0x2000>; + + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_UFS_PHY_PHY_AUX_CLK>, + <&tcsr TCSR_UFS_PHY_CLKREF_EN>; + + clock-names = "ref", + "ref_aux", + "qref"; + resets = <&ufs_mem_hc 0>; + reset-names = "ufsphy"; + + power-domains = <&gcc GCC_UFS_MEM_PHY_GDSC>; + + #clock-cells = <1>; + #phy-cells = <0>; + + status = "disabled"; + }; + + ufs_mem_hc: ufs@1d84000 { + compatible = "qcom,x1e80100-ufshc", + "qcom,sm8550-ufshc", + "qcom,ufshc", + "jedec,ufs-2.0"; + reg = <0x0 0x01d84000 0x0 0x3000>; + + interrupts = ; + + clocks = <&gcc GCC_UFS_PHY_AXI_CLK>, + <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, + <&gcc GCC_UFS_PHY_AHB_CLK>, + <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, + <&rpmhcc RPMH_LN_BB_CLK3>, + <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, + <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, + <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>; + clock-names = "core_clk", + "bus_aggr_clk", + "iface_clk", + "core_clk_unipro", + "ref_clk", + "tx_lane0_sync_clk", + "rx_lane0_sync_clk", + "rx_lane1_sync_clk"; + + operating-points-v2 = <&ufs_opp_table>; + + resets = <&gcc GCC_UFS_PHY_BCR>; + reset-names = "rst"; + + interconnects = <&aggre1_noc MASTER_UFS_MEM QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_UFS_MEM_CFG QCOM_ICC_TAG_ACTIVE_ONLY>; + interconnect-names = "ufs-ddr", + "cpu-ufs"; + + power-domains = <&gcc GCC_UFS_PHY_GDSC>; + required-opps = <&rpmhpd_opp_nom>; + + iommus = <&apps_smmu 0x1a0 0>; + dma-coherent; + + lanes-per-direction = <2>; + + phys = <&ufs_mem_phy>; + phy-names = "ufsphy"; + + #reset-cells = <1>; + + status = "disabled"; + + ufs_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-75000000 { + opp-hz = /bits/ 64 <75000000>, + /bits/ 64 <0>, + /bits/ 64 <0>, + /bits/ 64 <75000000>, + /bits/ 64 <0>, + /bits/ 64 <0>, + /bits/ 64 <0>, + /bits/ 64 <0>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-150000000 { + opp-hz = /bits/ 64 <150000000>, + /bits/ 64 <0>, + /bits/ 64 <0>, + /bits/ 64 <150000000>, + /bits/ 64 <0>, + /bits/ 64 <0>, + /bits/ 64 <0>, + /bits/ 64 <0>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-300000000 { + opp-hz = /bits/ 64 <300000000>, + /bits/ 64 <0>, + /bits/ 64 <0>, + /bits/ 64 <300000000>, + /bits/ 64 <0>, + /bits/ 64 <0>, + /bits/ 64 <0>, + /bits/ 64 <0>; + required-opps = <&rpmhpd_opp_nom>; + }; + }; + }; + cryptobam: dma-controller@1dc4000 { compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0"; reg = <0x0 0x01dc4000 0x0 0x28000>; -- 2.34.1