From: Can Guo <can.guo@oss.qualcomm.com>
To: avri.altman@wdc.com, bvanassche@acm.org, beanhuo@micron.com,
martin.petersen@oracle.com
Cc: linux-scsi@vger.kernel.org, Can Guo <can.guo@oss.qualcomm.com>,
Manivannan Sadhasivam <mani@kernel.org>,
"James E.J. Bottomley" <James.Bottomley@HansenPartnership.com>,
linux-arm-msm@vger.kernel.org (open list:ARM/QUALCOMM MAILING
LIST), linux-kernel@vger.kernel.org (open list)
Subject: [PATCH v2 10/11] scsi: ufs: ufs-qcom: Implement vops apply_tx_eqtr_settings()
Date: Wed, 4 Mar 2026 05:53:12 -0800 [thread overview]
Message-ID: <20260304135313.413688-11-can.guo@oss.qualcomm.com> (raw)
In-Reply-To: <20260304135313.413688-1-can.guo@oss.qualcomm.com>
On some platforms, when Host Software triggers TX Equalization Training,
HW does not take TX EQTR settings programmed in PA_TxEQTRSetting, instead
HW takes TX EQTR settings from PA_TxEQG1Setting. Implement vops
apply_tx_eqtr_setting() to work around it by programming TX EQTR settings
to PA_TxEQG1Setting during TX EQTR procedure.
Signed-off-by: Can Guo <can.guo@oss.qualcomm.com>
---
drivers/ufs/host/ufs-qcom.c | 33 +++++++++++++++++++++++++++++++++
drivers/ufs/host/ufs-qcom.h | 2 ++
2 files changed, 35 insertions(+)
diff --git a/drivers/ufs/host/ufs-qcom.c b/drivers/ufs/host/ufs-qcom.c
index b8fa4670ddd6..89bea823a08b 100644
--- a/drivers/ufs/host/ufs-qcom.c
+++ b/drivers/ufs/host/ufs-qcom.c
@@ -2848,6 +2848,28 @@ static int ufs_qcom_get_rx_fom(struct ufs_hba *hba,
return ret;
}
+static int ufs_qcom_apply_tx_eqtr_settings(struct ufs_hba *hba,
+ struct ufs_pa_layer_attr *pwr_mode,
+ struct tx_eqtr_iter *h_iter,
+ struct tx_eqtr_iter *d_iter)
+{
+ struct ufs_qcom_host *host = ufshcd_get_variant(hba);
+ u32 setting = 0;
+ int lane, ret;
+
+ if (host->hw_ver.major != 0x7 || host->hw_ver.minor > 0x1)
+ return 0;
+
+ for (lane = 0; lane < h_iter->num_lanes; lane++) {
+ setting |= TX_HS_PRESHOOT_BITS(lane, h_iter->preshoot);
+ setting |= TX_HS_DEEMPHASIS_BITS(lane, h_iter->deemphasis);
+ }
+
+ ret = ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TXEQG1SETTING), setting);
+
+ return ret;
+}
+
static int ufs_qcom_tx_eqtr_notify(struct ufs_hba *hba,
enum ufs_notify_change_status status,
struct ufs_pa_layer_attr *pwr_mode)
@@ -2870,6 +2892,11 @@ static int ufs_qcom_tx_eqtr_notify(struct ufs_hba *hba,
return 0;
if (status == PRE_CHANGE) {
+ ret = ufshcd_dme_get(hba, UIC_ARG_MIB(PA_TXEQG1SETTING),
+ &host->saved_tx_eq_g1_setting);
+ if (ret)
+ return ret;
+
/* PMC to target HS Gear. */
ret = ufs_qcom_change_power_mode(hba, pwr_mode,
UFSHCD_PMC_POLICY_DONT_FORCE);
@@ -2877,6 +2904,11 @@ static int ufs_qcom_tx_eqtr_notify(struct ufs_hba *hba,
dev_err(hba->dev, "%s: Failed to change power mode to target HS-G%u, Rate-%s: %d\n",
__func__, gear, UFS_HS_RATE_STRING(rate), ret);
} else {
+ ret = ufshcd_dme_set(hba, UIC_ARG_MIB(PA_TXEQG1SETTING),
+ host->saved_tx_eq_g1_setting);
+ if (ret)
+ return ret;
+
/* PMC back to HS-G1. */
ret = ufs_qcom_change_power_mode(hba, &pwr_mode_hs_g1,
UFSHCD_PMC_POLICY_DONT_FORCE);
@@ -2919,6 +2951,7 @@ static const struct ufs_hba_variant_ops ufs_hba_qcom_vops = {
.config_esi = ufs_qcom_config_esi,
.freq_to_gear_speed = ufs_qcom_freq_to_gear_speed,
.get_rx_fom = ufs_qcom_get_rx_fom,
+ .apply_tx_eqtr_settings = ufs_qcom_apply_tx_eqtr_settings,
.tx_eqtr_notify = ufs_qcom_tx_eqtr_notify,
};
diff --git a/drivers/ufs/host/ufs-qcom.h b/drivers/ufs/host/ufs-qcom.h
index 66fb42453e5c..ebe4e07c7da1 100644
--- a/drivers/ufs/host/ufs-qcom.h
+++ b/drivers/ufs/host/ufs-qcom.h
@@ -350,6 +350,8 @@ struct ufs_qcom_host {
u32 phy_gear;
bool esi_enabled;
+
+ u32 saved_tx_eq_g1_setting;
};
struct ufs_qcom_drvdata {
--
2.34.1
next prev parent reply other threads:[~2026-03-04 13:54 UTC|newest]
Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top
[not found] <20260304135313.413688-1-can.guo@oss.qualcomm.com>
2026-03-04 13:53 ` [PATCH v2 01/11] scsi: ufs: core: Introduce a new ufshcd vops negotiate_pwr_mode() Can Guo
2026-03-05 12:53 ` Krzysztof Kozlowski
2026-03-06 12:25 ` Can Guo
2026-03-05 21:03 ` Bean Huo
2026-03-06 12:41 ` Can Guo
2026-03-04 13:53 ` [PATCH v2 07/11] scsi: ufs: ufs-qcom: Fixup PAM-4 TX L0_L1_L2_L3 adaptation pattern length Can Guo
2026-03-04 15:10 ` Manivannan Sadhasivam
2026-03-06 11:14 ` Can Guo
2026-03-04 13:53 ` [PATCH v2 08/11] scsi: ufs: ufs-qcom: Implement vops tx_eqtr_notify() Can Guo
2026-03-04 15:20 ` Manivannan Sadhasivam
2026-03-06 13:41 ` Can Guo
2026-03-05 21:17 ` Bean Huo
2026-03-06 13:33 ` Can Guo
2026-03-04 13:53 ` [PATCH v2 09/11] scsi: ufs: ufs-qcom: Implement vops get_rx_fom() Can Guo
2026-03-04 15:39 ` Manivannan Sadhasivam
2026-03-06 14:04 ` Can Guo
2026-03-04 13:53 ` Can Guo [this message]
2026-03-04 15:41 ` [PATCH v2 10/11] scsi: ufs: ufs-qcom: Implement vops apply_tx_eqtr_settings() Manivannan Sadhasivam
2026-03-06 14:05 ` Can Guo
2026-03-04 13:53 ` [PATCH v2 11/11] scsi: ufs: ufs-qcom: Enable TX Equalization Can Guo
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20260304135313.413688-11-can.guo@oss.qualcomm.com \
--to=can.guo@oss.qualcomm.com \
--cc=James.Bottomley@HansenPartnership.com \
--cc=avri.altman@wdc.com \
--cc=beanhuo@micron.com \
--cc=bvanassche@acm.org \
--cc=linux-arm-msm@vger.kernel.org \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-scsi@vger.kernel.org \
--cc=mani@kernel.org \
--cc=martin.petersen@oracle.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox