From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 37CF1246774; Sat, 7 Mar 2026 13:18:49 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772889530; cv=none; b=W16T9IxYi9R3UNi/2A+6VUyVKMTGuPI3BCAVdSfArjaGv20oTIHHcetkAL01b27SpMvUEhJ00QrIuWtLFa7MtKBJEpO32hSi7RtVuK9GYTkOEXBFhAA932D+lAWmsCwgg+qBbSQxNIN5Ay992BpTDHpz5O8y9K/vgtonbjcODuk= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1772889530; c=relaxed/simple; bh=QZXxLPBHntF+vLD7uqKs9SQIti+fSk6TrNuInv4oxgU=; h=Date:From:To:Cc:Subject:Message-ID:References:MIME-Version: Content-Type:Content-Disposition:In-Reply-To; b=Ab2oOIx0zyMJ30mlFkNos+0XhcLK5mh3Q1fzq7QkhS4v8LSG3HftLD+MgviyKPA3VBe3+DslnMOrct0Z1lc/PF+53/ycWFqsc2sLCG655Vqheo/QPv8CUgIkpm7xYbrV1kH6ngr0ecHfpJpoMaKbD64hoTruK2hdgWvbGg7nFig= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=BXBa6ASp; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="BXBa6ASp" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 44E10C19422; Sat, 7 Mar 2026 13:18:49 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1772889529; bh=QZXxLPBHntF+vLD7uqKs9SQIti+fSk6TrNuInv4oxgU=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=BXBa6ASpU8uBvhfOja6Mg78haIbtuV+PJfqAMCZyEXuk03AHm/ZBuoqKL0XFhVqoS QmsOV+zRDRsTY5gFzXGxen/8YmKiXq8Vit4qXrdVY/bc97dKLvNX0bnwFA52wd30Q9 eiQmfpamrgnEY3GOYWOE0v38n4IqFmAvgGo4wnDFsDbY+zj2m+LESqt7ki+3JM/RY1 H2fpiSngyWfedb/3nzRwaOLt0z+CbowQzD8xtrVoV6xIEuMmWKUcpqR94cI8G4PreU KjxUaiYrRZ8IqrotVRQHvftg589KLH4WJ1gYTH/DUXUT4Ts4KOAtfExJdCffnxEgTT 57xa0uCJwkK/g== Date: Sat, 7 Mar 2026 14:18:47 +0100 From: Krzysztof Kozlowski To: Wangao Wang Cc: Bryan O'Donoghue , Vikash Garodia , Dikshita Agarwal , Abhinav Kumar , Mauro Carvalho Chehab , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson , Konrad Dybcio , linux-media@vger.kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH v2 4/5] media: iris: Add platform data for X1P42100 Message-ID: <20260307-curious-skilled-ibis-fffadf@quoll> References: <20260306-enable_iris_on_purwa-v2-0-75fa80a0a9e3@oss.qualcomm.com> <20260306-enable_iris_on_purwa-v2-4-75fa80a0a9e3@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline In-Reply-To: <20260306-enable_iris_on_purwa-v2-4-75fa80a0a9e3@oss.qualcomm.com> On Fri, Mar 06, 2026 at 04:44:32PM +0800, Wangao Wang wrote: > Introduce platform data for X1P42100, derived from SM8550 but using a > different clock configuration and a dedicated OPP setup. > > Signed-off-by: Wangao Wang > --- > .../platform/qcom/iris/iris_platform_common.h | 1 + > .../media/platform/qcom/iris/iris_platform_gen2.c | 97 ++++++++++++++++++++++ > .../platform/qcom/iris/iris_platform_x1p42100.h | 22 +++++ > drivers/media/platform/qcom/iris/iris_probe.c | 4 + > 4 files changed, 124 insertions(+) > > diff --git a/drivers/media/platform/qcom/iris/iris_platform_common.h b/drivers/media/platform/qcom/iris/iris_platform_common.h > index 5a489917580eb10022fdcb52f7321a915e8b239d..2e97360ddcd56a4b61fb296782b0c914b6154784 100644 > --- a/drivers/media/platform/qcom/iris/iris_platform_common.h > +++ b/drivers/media/platform/qcom/iris/iris_platform_common.h > @@ -47,6 +47,7 @@ extern const struct iris_platform_data sm8250_data; > extern const struct iris_platform_data sm8550_data; > extern const struct iris_platform_data sm8650_data; > extern const struct iris_platform_data sm8750_data; > +extern const struct iris_platform_data x1p42100_data; > > enum platform_clk_type { > IRIS_AXI_CLK, /* AXI0 in case of platforms with multiple AXI clocks */ > diff --git a/drivers/media/platform/qcom/iris/iris_platform_gen2.c b/drivers/media/platform/qcom/iris/iris_platform_gen2.c > index 5da90d47f9c6eab4a7e6b17841fdc0e599397bf7..3194bb9465aec4764d5f75a7f68c9f2f33232687 100644 > --- a/drivers/media/platform/qcom/iris/iris_platform_gen2.c > +++ b/drivers/media/platform/qcom/iris/iris_platform_gen2.c > @@ -15,6 +15,7 @@ > #include "iris_platform_qcs8300.h" > #include "iris_platform_sm8650.h" > #include "iris_platform_sm8750.h" > +#include "iris_platform_x1p42100.h" > > #define VIDEO_ARCH_LX 1 > #define BITRATE_MAX 245000000 > @@ -1317,3 +1318,99 @@ const struct iris_platform_data qcs8300_data = { > .enc_op_int_buf_tbl = sm8550_enc_op_int_buf_tbl, > .enc_op_int_buf_tbl_size = ARRAY_SIZE(sm8550_enc_op_int_buf_tbl), > }; > + > +const struct iris_platform_data x1p42100_data = { > + .get_instance = iris_hfi_gen2_get_instance, > + .init_hfi_command_ops = iris_hfi_gen2_command_ops_init, > + .init_hfi_response_ops = iris_hfi_gen2_response_ops_init, > + .get_vpu_buffer_size = iris_vpu_buf_size, > + .vpu_ops = &iris_vpu3_ops, > + .set_preset_registers = iris_set_sm8550_preset_registers, > + .icc_tbl = sm8550_icc_table, > + .icc_tbl_size = ARRAY_SIZE(sm8550_icc_table), > + .clk_rst_tbl = sm8550_clk_reset_table, > + .clk_rst_tbl_size = ARRAY_SIZE(sm8550_clk_reset_table), > + .bw_tbl_dec = sm8550_bw_table_dec, > + .bw_tbl_dec_size = ARRAY_SIZE(sm8550_bw_table_dec), > + .pmdomain_tbl = sm8550_pmdomain_table, > + .pmdomain_tbl_size = ARRAY_SIZE(sm8550_pmdomain_table), > + .opp_pd_tbl = sm8550_opp_pd_table, > + .opp_pd_tbl_size = ARRAY_SIZE(sm8550_opp_pd_table), > + .clk_tbl = x1p42100_clk_table, > + .clk_tbl_size = ARRAY_SIZE(x1p42100_clk_table), > + .opp_clk_tbl = x1p42100_opp_clk_table, > + /* Upper bound of DMA address range */ > + .dma_mask = 0xe0000000 - 1, > + .fwname = "qcom/vpu/vpu30_p4.mbn", > + .pas_id = IRIS_PAS_ID, > + .inst_iris_fmts = platform_fmts_sm8550_dec, > + .inst_iris_fmts_size = ARRAY_SIZE(platform_fmts_sm8550_dec), > + .inst_caps = &platform_inst_cap_sm8550, > + .inst_fw_caps_dec = inst_fw_cap_sm8550_dec, > + .inst_fw_caps_dec_size = ARRAY_SIZE(inst_fw_cap_sm8550_dec), > + .inst_fw_caps_enc = inst_fw_cap_sm8550_enc, > + .inst_fw_caps_enc_size = ARRAY_SIZE(inst_fw_cap_sm8550_enc), > + .tz_cp_config_data = tz_cp_config_sm8550, > + .tz_cp_config_data_size = ARRAY_SIZE(tz_cp_config_sm8550), > + .core_arch = VIDEO_ARCH_LX, > + .hw_response_timeout = HW_RESPONSE_TIMEOUT_VALUE, > + .ubwc_config = &ubwc_config_sm8550, > + .num_vpp_pipe = 4, > + .max_session_count = 16, > + .max_core_mbpf = NUM_MBS_8K * 2, > + .max_core_mbps = ((7680 * 4320) / 256) * 60, > + .dec_input_config_params_default = > + sm8550_vdec_input_config_params_default, > + .dec_input_config_params_default_size = > + ARRAY_SIZE(sm8550_vdec_input_config_params_default), > + .dec_input_config_params_hevc = > + sm8550_vdec_input_config_param_hevc, > + .dec_input_config_params_hevc_size = > + ARRAY_SIZE(sm8550_vdec_input_config_param_hevc), > + .dec_input_config_params_vp9 = > + sm8550_vdec_input_config_param_vp9, > + .dec_input_config_params_vp9_size = > + ARRAY_SIZE(sm8550_vdec_input_config_param_vp9), > + .dec_input_config_params_av1 = > + sm8550_vdec_input_config_param_av1, > + .dec_input_config_params_av1_size = > + ARRAY_SIZE(sm8550_vdec_input_config_param_av1), > + .dec_output_config_params = > + sm8550_vdec_output_config_params, > + .dec_output_config_params_size = > + ARRAY_SIZE(sm8550_vdec_output_config_params), > + > + .enc_input_config_params = > + sm8550_venc_input_config_params, > + .enc_input_config_params_size = > + ARRAY_SIZE(sm8550_venc_input_config_params), > + .enc_output_config_params = > + sm8550_venc_output_config_params, > + .enc_output_config_params_size = > + ARRAY_SIZE(sm8550_venc_output_config_params), > + > + .dec_input_prop = sm8550_vdec_subscribe_input_properties, > + .dec_input_prop_size = ARRAY_SIZE(sm8550_vdec_subscribe_input_properties), > + .dec_output_prop_avc = sm8550_vdec_subscribe_output_properties_avc, > + .dec_output_prop_avc_size = > + ARRAY_SIZE(sm8550_vdec_subscribe_output_properties_avc), > + .dec_output_prop_hevc = sm8550_vdec_subscribe_output_properties_hevc, > + .dec_output_prop_hevc_size = > + ARRAY_SIZE(sm8550_vdec_subscribe_output_properties_hevc), > + .dec_output_prop_vp9 = sm8550_vdec_subscribe_output_properties_vp9, > + .dec_output_prop_vp9_size = > + ARRAY_SIZE(sm8550_vdec_subscribe_output_properties_vp9), > + .dec_output_prop_av1 = sm8550_vdec_subscribe_output_properties_av1, > + .dec_output_prop_av1_size = > + ARRAY_SIZE(sm8550_vdec_subscribe_output_properties_av1), > + > + .dec_ip_int_buf_tbl = sm8550_dec_ip_int_buf_tbl, > + .dec_ip_int_buf_tbl_size = ARRAY_SIZE(sm8550_dec_ip_int_buf_tbl), > + .dec_op_int_buf_tbl = sm8550_dec_op_int_buf_tbl, > + .dec_op_int_buf_tbl_size = ARRAY_SIZE(sm8550_dec_op_int_buf_tbl), > + > + .enc_ip_int_buf_tbl = sm8550_enc_ip_int_buf_tbl, > + .enc_ip_int_buf_tbl_size = ARRAY_SIZE(sm8550_enc_ip_int_buf_tbl), > + .enc_op_int_buf_tbl = sm8550_enc_op_int_buf_tbl, > + .enc_op_int_buf_tbl_size = ARRAY_SIZE(sm8550_enc_op_int_buf_tbl), > +}; > \ No newline at end of file You have patch warnings. Check your patches before you send them. > diff --git a/drivers/media/platform/qcom/iris/iris_platform_x1p42100.h b/drivers/media/platform/qcom/iris/iris_platform_x1p42100.h > new file mode 100644 > index 0000000000000000000000000000000000000000..d89acfbc1233dad0692f6c13c3fc22b10e5bdd80 > --- /dev/null > +++ b/drivers/media/platform/qcom/iris/iris_platform_x1p42100.h > @@ -0,0 +1,22 @@ > +/* SPDX-License-Identifier: GPL-2.0-only */ > +/* > + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. > + */ > + > +#ifndef __IRIS_PLATFORM_X1P42100_H__ > +#define __IRIS_PLATFORM_X1P42100_H__ > + > +static const struct platform_clk_data x1p42100_clk_table[] = { > + {IRIS_AXI_CLK, "iface" }, > + {IRIS_CTRL_CLK, "core" }, > + {IRIS_HW_CLK, "vcodec0_core" }, > + {IRIS_BSE_HW_CLK, "vcodec0_bse" }, And maybe that's just IRIS_AXI_CLK clock? People keep sending downstream code and name such stuff because they found it in downstream, so I have doubts. It looks like you just duplicate what was for sm8750 in iris_vpu35_power_on_hw(). Best regards, Krzysztof