From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C20223C553B; Wed, 25 Mar 2026 11:14:01 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774437241; cv=none; b=iANzptbBzUGuBSKy1Qg0hXKk1X/esg44llxMVOIyo/mK/k8yQSZTm5xfebQeswHky4zSxKHklWo2BR0p9vjbnvR+6KBsouMwJaITdXc8nBG5wYMnMOUUapgVW7L8itoltbMHbJiTk69Q6BBcQMCdwMPtjoEQkB14jZmJxq0SX7c= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774437241; c=relaxed/simple; bh=hcYNt9DUgklKTrpHxMNPyP+h2t607LXaxgQ36exgrRc=; h=Date:From:To:Cc:Subject:Message-ID:References:MIME-Version: Content-Type:Content-Disposition:In-Reply-To; b=BHEfghn3Egz1pnYCEvgeW9ooVjGjPRFTeTNG3cVJ7L/EG4icXvWzP+ucEmzCrWcWi7u53mFRwtnnxSxN8sH4O+l6PMoeNmD8C7IrRg7X4dxfROiHk2I9+CaxqAic7JFLjfjAAHiYdtFX3S3APDdnRLf1WGTIAoremH0I0Bg0nQw= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=jntd9qoQ; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="jntd9qoQ" Received: by smtp.kernel.org (Postfix) with ESMTPSA id BD80DC4CEF7; Wed, 25 Mar 2026 11:14:00 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1774437241; bh=hcYNt9DUgklKTrpHxMNPyP+h2t607LXaxgQ36exgrRc=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=jntd9qoQcwrHUTmb9HjZFBJa42NxmyCanq4YysGzLPX96V2w2NFp830kAIwnN8MCG HO6EQZmt8b+InoLJe/lvz9S2D/9oIKNs+h6BKnniPtvp4HNSaKZmptu2s7NBRjZnrb 9ItI51U6kcpV2y5Kf7tx8qjE4iLAs6dGvzD8fscEpeFeYN1HArjW7WfPSxljlU5ehE jwvxy5SGdzZPqhvWs4fDVH0uCBthvQbgNP7dDPevN4HMfJlVRKAq6tsx1HNJHFav1p S7jGH57Sd+3v7QeWW+u76q0hJp3mJMI/zA+isu1sLziXF6nloWc9aIZ5Lc97TnANBT p8W5vc3hLp5aw== Date: Wed, 25 Mar 2026 12:13:58 +0100 From: Krzysztof Kozlowski To: Viken Dadhaniya Cc: Mark Brown , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Bjorn Andersson , Konrad Dybcio , cros-qcom-dts-watchers@chromium.org, linux-arm-msm@vger.kernel.org, linux-spi@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH v1 3/6] arm64: dts: qcom: talos: Add QSPI support Message-ID: <20260325-dancing-macho-coyote-deaa55@quoll> References: <20260324-spi-nor-v1-0-3efe59c1c119@oss.qualcomm.com> <20260324-spi-nor-v1-3-3efe59c1c119@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline In-Reply-To: <20260324-spi-nor-v1-3-3efe59c1c119@oss.qualcomm.com> On Tue, Mar 24, 2026 at 06:43:20PM +0530, Viken Dadhaniya wrote: > The Talos (QCS615) platform includes a QSPI controller used for accessing > external flash storage. Add the QSPI OPP table, TLMM pinmux entries, and > the QSPI controller node to enable support for this hardware. > > Signed-off-by: Viken Dadhaniya > --- > arch/arm64/boot/dts/qcom/talos.dtsi | 80 +++++++++++++++++++++++++++++++++++++ > 1 file changed, 80 insertions(+) > > diff --git a/arch/arm64/boot/dts/qcom/talos.dtsi b/arch/arm64/boot/dts/qcom/talos.dtsi > index 75716b4a58d6..fd727924b8ca 100644 > --- a/arch/arm64/boot/dts/qcom/talos.dtsi > +++ b/arch/arm64/boot/dts/qcom/talos.dtsi > @@ -530,6 +530,25 @@ cdsp_smp2p_in: slave-kernel { > > }; > > + qspi_opp_table: opp-table-qspi { Does device have only one QSPI? Then table goes to device node and binding needs "opp-table". Best regards, Krzysztof