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[199.106.103.254]) by smtp.gmail.com with ESMTPSA id a92af1059eb24-12de321df36sm7572644c88.7.2026.04.29.20.21.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 29 Apr 2026 20:21:42 -0700 (PDT) From: Linlin Zhang To: linux-arm-msm@vger.kernel.org, linux-crypto@vger.kernel.org, linux-kernel@vger.kernel.org, ebiggers@google.com Cc: neeraj.soni@oss.qualcomm.com, gaurav.kashyap@oss.qualcomm.com, deepti.jaggi@oss.qualcomm.com, bjorn.andersson@oss.qualcomm.com, quic_shazhuss@quicinc.com, trilok.soni@oss.qualcomm.com, konrad.dybcio@oss.qualcomm.com Subject: [PATCH v6 2/3] soc: qcom: ice: Enable PM runtime for ICE driver Date: Wed, 29 Apr 2026 20:21:34 -0700 Message-Id: <20260430032136.3058773-3-linlin.zhang@oss.qualcomm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20260430032136.3058773-1-linlin.zhang@oss.qualcomm.com> References: <20260430032136.3058773-1-linlin.zhang@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNDMwMDAzMSBTYWx0ZWRfXzMx4P5HxVElE yzErB2+vMYbY1GWDzvIBLbPddT+11zfIzcKp/7lTGgaerV5uORlU+BDjurDbDnP8YihnsjDhjpU J93w7mxDvteLN1JyTE/Bgb9WRIdkEU3+C1CfK79SS1Yp3fGKxSyiw0TrOcxHx4zFieb6S7CvqIQ U+kaKvSIN8LKvSprOleaWnRzdQyWDQBxvuTgBsD4+3ydCu9fTcXCq+6AqkcXhZaTDryPsRK4DqQ 6b/+g/XhAARd4Y1dSuU5dzGG5kgDCmiL2OLFuToC7IW+QvrtG9s6K58D3GmrVR2Yq/V4p34ratZ qjDtQ+unU/EMA2xvPUSeqFkWNaxWdYkgGAEzm1NUWO/+M6pcVQxhXLXxzZoOHjhovd9+EM+MId8 1OCFbzDFy7fE6mxl6Pq6zctnL9hCxaZ5g+zbTlcPQ1yeIb8LNuOB0NWas2NmAQGyJhm1ytdscmT +A3m4PwkyV5XpyyYkgg== X-Authority-Analysis: v=2.4 cv=Oc2oyBTY c=1 sm=1 tr=0 ts=69f2cac8 cx=c_pps a=wEP8DlPgTf/vqF+yE6f9lg==:117 a=JYp8KDb2vCoCEuGobkYCKw==:17 a=A5OVakUREuEA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=3WHJM1ZQz_JShphwDgj5:22 a=EUspDBNiAAAA:8 a=7JBRkwD79zxFga_vYKgA:9 a=bBxd6f-gb0O0v-kibOvt:22 X-Proofpoint-GUID: gsToAiU-fF2fSYQzhA-E27jmTzUUUL9O X-Proofpoint-ORIG-GUID: gsToAiU-fF2fSYQzhA-E27jmTzUUUL9O X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-04-30_01,2026-04-28_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 spamscore=0 lowpriorityscore=0 phishscore=0 suspectscore=0 impostorscore=0 bulkscore=0 malwarescore=0 priorityscore=1501 adultscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2604200000 definitions=main-2604300031 The QCOM ICE driver manages the ICE core clock through direct calls to clk_prepare_enable() and clk_disable_unprepare(), which limits integration with platforms that rely on firmware-managed resources or platform-specific power management mechanisms. Replace direct clock management with runtime PM support by moving clock enable and disable into runtime PM callbacks. Use pm_runtime_resume_and_get() and pm_runtime_put_sync() in qcom_ice_resume() and qcom_ice_suspend() to drive power state transitions, and enable runtime PM in qcom_ice_probe(). Reviewed-by: Neeraj Soni Reviewed-by: Deepti Jaggi Signed-off-by: Linlin Zhang --- drivers/soc/qcom/ice.c | 58 ++++++++++++++++++++++++++++++++++++++---- 1 file changed, 53 insertions(+), 5 deletions(-) diff --git a/drivers/soc/qcom/ice.c b/drivers/soc/qcom/ice.c index b203bc685cad..6f9d679b530c 100644 --- a/drivers/soc/qcom/ice.c +++ b/drivers/soc/qcom/ice.c @@ -16,6 +16,7 @@ #include #include #include +#include #include @@ -310,8 +311,8 @@ int qcom_ice_resume(struct qcom_ice *ice) struct device *dev = ice->dev; int err; - err = clk_prepare_enable(ice->core_clk); - if (err) { + err = pm_runtime_resume_and_get(dev); + if (err < 0) { dev_err(dev, "failed to enable core clock (%d)\n", err); return err; @@ -323,7 +324,7 @@ EXPORT_SYMBOL_GPL(qcom_ice_resume); int qcom_ice_suspend(struct qcom_ice *ice) { - clk_disable_unprepare(ice->core_clk); + pm_runtime_put_sync(ice->dev); ice->hwkm_init_complete = false; return 0; @@ -716,24 +717,69 @@ EXPORT_SYMBOL_GPL(devm_of_qcom_ice_get); static int qcom_ice_probe(struct platform_device *pdev) { + struct device *dev = &pdev->dev; struct qcom_ice *engine; void __iomem *base; + int ret; base = devm_platform_ioremap_resource(pdev, 0); if (IS_ERR(base)) { - dev_warn(&pdev->dev, "ICE registers not found\n"); + dev_warn(dev, "ICE registers not found\n"); return PTR_ERR(base); } - engine = qcom_ice_create(&pdev->dev, base); + engine = qcom_ice_create(dev, base); if (IS_ERR(engine)) return PTR_ERR(engine); platform_set_drvdata(pdev, engine); + ret = devm_pm_runtime_enable(dev); + if (ret) { + dev_warn(dev, "Enable runtime PM failed, ret: %d\n", ret); + return ret; + } + + ret = pm_runtime_resume_and_get(dev); + if (ret < 0) { + dev_warn(dev, "Runtime PM fails to resume, ret: %d\n", ret); + return ret; + } + return 0; } +static void qcom_ice_remove(struct platform_device *pdev) +{ + pm_runtime_put_sync(&pdev->dev); +} + +static int ice_runtime_resume(struct device *dev) +{ + struct qcom_ice *ice = dev_get_drvdata(dev); + int err = 0; + + err = clk_prepare_enable(ice->core_clk); + if (err) { + dev_err(dev, "failed to enable core clock (%d)\n", + err); + } + + return err; +} + +static int ice_runtime_suspend(struct device *dev) +{ + struct qcom_ice *ice = dev_get_drvdata(dev); + + clk_disable_unprepare(ice->core_clk); + return 0; +} + +static const struct dev_pm_ops ice_pm_ops = { + SET_RUNTIME_PM_OPS(ice_runtime_suspend, ice_runtime_resume, NULL) +}; + static const struct of_device_id qcom_ice_of_match_table[] = { { .compatible = "qcom,inline-crypto-engine" }, { }, @@ -742,8 +788,10 @@ MODULE_DEVICE_TABLE(of, qcom_ice_of_match_table); static struct platform_driver qcom_ice_driver = { .probe = qcom_ice_probe, + .remove = qcom_ice_remove, .driver = { .name = "qcom-ice", + .pm = &ice_pm_ops, .of_match_table = qcom_ice_of_match_table, }, }; -- 2.34.1