From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-qv1-f41.google.com (mail-qv1-f41.google.com [209.85.219.41]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 000703DC4BD for ; Fri, 1 May 2026 15:54:51 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.219.41 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1777650893; cv=none; b=bHTQtKvGPsV8ZF3DBVs6uPXsErwbGND1hiKSbmYHvYu8XaC8fwBCfa8jP0n7CmgpORwtXJoS25hRZNB4o9sxDOEobh0007Z/E7iIzIdO3Tp6ascxR2qp6s3+aq98XzfPPHEt77B/3Q5lAdQHjVvIDb/IK9Wgd6FKHivB9D0es0o= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1777650893; c=relaxed/simple; bh=sdVoEALgUHLLwTph3KA4x290Mapqipjj87aWWehudsk=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=VsoZ+ktdSv/uKi7mU1VGt3Hcq1djHnAw8WO44b3RYo/dLAgHoWXJ6GIPhDO8cEczVPglBK5/PQlYYfh1XIrOz1oOL9ws0FkIj/FdiIHqkCkPfAX6TjOMfdJERVxx+M7yIfbIHutibPKmaCUD96xswW8F1VGVF2k33MH/GHedxgM= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=riscstar.com; spf=pass smtp.mailfrom=riscstar.com; dkim=pass (2048-bit key) header.d=riscstar-com.20251104.gappssmtp.com header.i=@riscstar-com.20251104.gappssmtp.com header.b=JOF3DMg8; arc=none smtp.client-ip=209.85.219.41 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=riscstar.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=riscstar.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=riscstar-com.20251104.gappssmtp.com header.i=@riscstar-com.20251104.gappssmtp.com header.b="JOF3DMg8" Received: by mail-qv1-f41.google.com with SMTP id 6a1803df08f44-8a210c813f8so13842876d6.0 for ; Fri, 01 May 2026 08:54:51 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=riscstar-com.20251104.gappssmtp.com; s=20251104; t=1777650891; x=1778255691; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=8RGGmioeApSW4Mpcfugq/UHupyYC8IBT0gCB0CxHGJA=; b=JOF3DMg8AnITnSLlbsITV4GJ1SJJXvN9eI9iCkMITDyCW+wnTUiLDdq8H2hw2FvvXG 7S1HiDJU/lzu2K2f/ojbj2+nWLRfN/tT5I7m5lHza+oUD8hngS2Y/iJQTcvCbTlFSgwR OL+OPBVwgma0zHpy10xiFDnrDiFCltTE8VE7VGLNXuYwTtF+QcQA8qUcZCZwfj2JK9pi lKJ30zHs18eNlEfs3+MnlxBFZ3jg8dvjcxa1K0z82pDmC+1A1+UHLzQ1V9HgHnzwoUtD 6yWYAjJ9P5oaRhQPwo1gZde9rjg4jPacD/sdMLQjSjJo32qudwdvDx+YBjQ7sgGbsMPV sUzg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1777650891; x=1778255691; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from :to:cc:subject:date:message-id:reply-to; bh=8RGGmioeApSW4Mpcfugq/UHupyYC8IBT0gCB0CxHGJA=; b=dHm0QFrG5HAVU/xj6KnoBZCMOT72ySpvVKOGpurajH5SdcIgHwO6oR1rDzQvM8l4jH EjO0CMRdt60J6GNen6Q/yZGsAsMMH/6Vyin7gyNQSSglcBtVRYxB8iFtReeYqQpEO0fP UJgMZoF1NYjTS1CPPct3+8x9ZE6Z0UGMLgCZ6XPN55bKzbolr/yYTVSIgHL0dNpvUFx2 ET0CU9NKkLZvQG2yT1KOtVljUtuyT5I2zptQk5MRzGXnEjEADsa2KeoEH6+CawDRaBpl O8ouzW9S3MJSceRed96G9NhMlXkVtZBkNhdk6RKQpnzL5ticV3C3S8oPN71wx/3XL6Ow 54Pw== X-Forwarded-Encrypted: i=1; AFNElJ9L8obaE/JmZX/Uiyor063GAoKVJngwb5fVgCObOS+Qi1UcSknBu+a+qy2gtwusxMTbbVLry/GblvbEBxKe@vger.kernel.org X-Gm-Message-State: AOJu0YxrYRibNI6LGbAFB8hQ7maKMjnf++OVuR0iCs3LRtdwO+8VrXts GGQkqcZdew3mHyLMMS0mDVga04XAt5n7dD31AhK0SaNPQXcQ+uKuXp+JVwq0pX/ULkE= X-Gm-Gg: AeBDievbXPy67lTLZn4ecroyQLFdU5RErY0vgJKg3ZNBUE7Q69tdcO/bdhHvlgcVvYj ZgPAPO11vSRLnr2hEKJandvYSIyPHejTXWvWdDUo07aQGwZ9L/YoU28zcHeBLsfIMBfo+gmzkqb Z2Pu2W/qcKq5VFLWztJvKVG8Za9bPyTweL0sm+6ta46O/saSc3NnXpJJjDgdqW+NjQPjvSzr/ll 9+EX9+45U6tfVOQ1WYDNfxbiQbST+5FS1i4riYNdqt+VoaV49QpYGOd0nWi71YHf5A/SScaxHdV kQxA64n3hHebhuwa6eqDA7wkehX8Kp0a7XWEQrPEbBREBbl3rUBt8ffkeMnGOURL+A1cG2bKo2H HNvuyh+Ibkg9Mo1WWlEbeyRu4rQh1d5K+MwtJrfbSPMF0xc45XBWxHJwgnSTyOcLqgK1xvJgW+Z W/yiBgJieM6FZlfhCXiuMWYL6Fjc2BkDaThtBWTzvV4T74UGVUD5L+8S0jcfK2NjWRf/3TU3Cy9 FtiVaaoeWFSeGvl X-Received: by 2002:a05:6214:dc3:b0:8b4:6df4:87e8 with SMTP id 6a1803df08f44-8b6699cc88fmr282706d6.49.1777650890881; Fri, 01 May 2026 08:54:50 -0700 (PDT) Received: from zippy.localdomain (c-75-72-117-212.hsd1.mn.comcast.net. [75.72.117.212]) by smtp.gmail.com with ESMTPSA id 6a1803df08f44-8b539aa7293sm26615406d6.22.2026.05.01.08.54.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 01 May 2026 08:54:50 -0700 (PDT) From: Alex Elder To: andrew+netdev@lunn.ch, davem@davemloft.net, edumazet@google.com, kuba@kernel.org, pabeni@redhat.com, maxime.chevallier@bootlin.com, rmk+kernel@armlinux.org.uk, andersson@kernel.org, konradybcio@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, linusw@kernel.org, brgl@kernel.org, arnd@arndb.de, gregkh@linuxfoundation.org Cc: Daniel Thompson , elder@riscstar.com, mohd.anwar@oss.qualcomm.com, a0987203069@gmail.com, alexandre.torgue@foss.st.com, ast@kernel.org, boon.khai.ng@altera.com, chenchuangyu@xiaomi.com, chenhuacai@kernel.org, daniel@iogearbox.net, hawk@kernel.org, hkallweit1@gmail.com, inochiama@gmail.com, john.fastabend@gmail.com, julianbraha@gmail.com, livelycarpet87@gmail.com, matthew.gerlach@altera.com, mcoquelin.stm32@gmail.com, me@ziyao.cc, prabhakar.mahadev-lad.rj@bp.renesas.com, richardcochran@gmail.com, rohan.g.thomas@altera.com, sdf@fomichev.me, siyanteng@cqsoftware.com.cn, weishangjuan@eswincomputing.com, wens@kernel.org, netdev@vger.kernel.org, bpf@vger.kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-gpio@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH net-next 07/12] net: stmmac: dwxgmac2: export symbols for XGMAC 3.01a DMA Date: Fri, 1 May 2026 10:54:15 -0500 Message-ID: <20260501155421.3329862-8-elder@riscstar.com> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20260501155421.3329862-1-elder@riscstar.com> References: <20260501155421.3329862-1-elder@riscstar.com> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit From: Daniel Thompson Toshiba TC956x is an Ethernet-AVB/TSN bridge and is essentially a small-and-highly-specialised SoC. Ethernet on this chip is provided by a DesignWare XGMAC. One consequence of the SoC-like design is that the internal AXI bus (used by the XGMAC for DMA) maps the PCI DMA space with a non-zero base address. This requires a translation step (happily just simple addition) to convert the PCI DMA address to the hardware DMA address. This is pretty funky so rather than push that translation logic into the core driver we intend to keep that logic inside the TC956x platform code. In order to do that we need to export a few symbols to allow us to override some of the DMA and descriptor op tables. FWIW this approach to overriding the ops tables is similar to the mechanism currently found in dwmac-loongson.c (with the exception that we have also exported a couple of functions so we don't have to replicate their content in the TC956x platform code). Signed-off-by: Daniel Thompson Signed-off-by: Alex Elder --- drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h | 7 +++++++ .../ethernet/stmicro/stmmac/dwxgmac2_core.c | 1 + .../ethernet/stmicro/stmmac/dwxgmac2_descs.c | 1 + .../net/ethernet/stmicro/stmmac/dwxgmac2_dma.c | 18 ++++++++++-------- 4 files changed, 19 insertions(+), 8 deletions(-) diff --git a/drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h b/drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h index bcf59ad8a1939..8cecde1bef8a1 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h +++ b/drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h @@ -468,4 +468,11 @@ extern const struct stmmac_dma_ops dwxgmac210_dma_ops; extern const struct stmmac_dma_ops dwxgmac301_dma_ops; extern const struct stmmac_desc_ops dwxgmac210_desc_ops; +void dwxgmac2_dma_init_rx_chan(struct stmmac_priv *priv, void __iomem *ioaddr, + struct stmmac_dma_cfg *dma_cfg, dma_addr_t phy, + u32 chan); +void dwxgmac2_dma_init_tx_chan(struct stmmac_priv *priv, void __iomem *ioaddr, + struct stmmac_dma_cfg *dma_cfg, dma_addr_t phy, + u32 chan); + #endif /* __STMMAC_DWXGMAC2_H__ */ diff --git a/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c b/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c index f02b434bbd505..c9547dc6912a3 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c +++ b/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_core.c @@ -1556,6 +1556,7 @@ int dwxgmac2_setup(struct stmmac_priv *priv) return 0; } +EXPORT_SYMBOL_GPL(dwxgmac2_setup); int dwxlgmac2_setup(struct stmmac_priv *priv) { diff --git a/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c b/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c index b5f200a874840..cc67d8e1a920a 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c +++ b/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_descs.c @@ -368,3 +368,4 @@ const struct stmmac_desc_ops dwxgmac210_desc_ops = { .set_vlan = dwxgmac2_set_vlan, .set_tbs = dwxgmac2_set_tbs, }; +EXPORT_SYMBOL_GPL(dwxgmac210_desc_ops); diff --git a/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_dma.c b/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_dma.c index dc2897e9931d1..ec365e66276f1 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_dma.c +++ b/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_dma.c @@ -62,10 +62,10 @@ static void dwxgmac2_dma_init_chan(struct stmmac_priv *priv, writel(XGMAC_DMA_INT_DEFAULT_EN, ioaddr + XGMAC_DMA_CH_INT_EN(chan)); } -static void dwxgmac2_dma_init_rx_chan(struct stmmac_priv *priv, - void __iomem *ioaddr, - struct stmmac_dma_cfg *dma_cfg, - dma_addr_t phy, u32 chan) +void dwxgmac2_dma_init_rx_chan(struct stmmac_priv *priv, + void __iomem *ioaddr, + struct stmmac_dma_cfg *dma_cfg, + dma_addr_t phy, u32 chan) { u32 rxpbl = dma_cfg->rxpbl ?: dma_cfg->pbl; u32 value; @@ -77,11 +77,11 @@ static void dwxgmac2_dma_init_rx_chan(struct stmmac_priv *priv, writel(upper_32_bits(phy), ioaddr + XGMAC_DMA_CH_RxDESC_HADDR(chan)); writel(lower_32_bits(phy), ioaddr + XGMAC_DMA_CH_RxDESC_LADDR(chan)); } +EXPORT_SYMBOL_GPL(dwxgmac2_dma_init_rx_chan); -static void dwxgmac2_dma_init_tx_chan(struct stmmac_priv *priv, - void __iomem *ioaddr, - struct stmmac_dma_cfg *dma_cfg, - dma_addr_t phy, u32 chan) +void dwxgmac2_dma_init_tx_chan(struct stmmac_priv *priv, void __iomem *ioaddr, + struct stmmac_dma_cfg *dma_cfg, dma_addr_t phy, + u32 chan) { u32 txpbl = dma_cfg->txpbl ?: dma_cfg->pbl; u32 value; @@ -93,6 +93,7 @@ static void dwxgmac2_dma_init_tx_chan(struct stmmac_priv *priv, writel(upper_32_bits(phy), ioaddr + XGMAC_DMA_CH_TxDESC_HADDR(chan)); writel(lower_32_bits(phy), ioaddr + XGMAC_DMA_CH_TxDESC_LADDR(chan)); } +EXPORT_SYMBOL_GPL(dwxgmac2_dma_init_tx_chan); static void dwxgmac2_dma_axi(void __iomem *ioaddr, struct stmmac_axi *axi) { @@ -671,3 +672,4 @@ const struct stmmac_dma_ops dwxgmac301_dma_ops = { .enable_sph = dwxgmac2_enable_sph, .enable_tbs = dwxgmac2_enable_tbs, }; +EXPORT_SYMBOL_GPL(dwxgmac301_dma_ops); -- 2.51.0