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[104.48.214.220]) by smtp.gmail.com with ESMTPSA id 00721157ae682-7bd66525651sm40140327b3.3.2026.05.03.13.30.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 03 May 2026 13:30:09 -0700 (PDT) From: Steev Klimaszewski To: krishna.chundru@oss.qualcomm.com Cc: bhelgaas@google.com, bjorn.andersson@oss.qualcomm.com, jingoohan1@gmail.com, jonathanh@nvidia.com, kwilczynski@kernel.org, linux-arm-kernel@lists.infradead.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, lpieralisi@kernel.org, mani@kernel.org, robh@kernel.org, will@kernel.org Subject: Re: PCI: qcom: Add D3cold support Date: Sun, 3 May 2026 15:30:06 -0500 Message-ID: <20260503203008.287559-1-threeway@gmail.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260429-d3cold-v5-0-89e9735b9df6@oss.qualcomm.com> References: <20260429-d3cold-v5-0-89e9735b9df6@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Hi Krishna, > This series adds support for putting Qualcomm PCIe host bridges into D3cold > when downstream conditions allow it, and introduces a small common helper > to determine D3cold eligibility based on endpoint state. > On Qualcomm platforms, PCIe host controllers are currently kept powered > even when there are no active endpoints (i.e. all endpoints are already in > PCI_D3hot). This prevents the SoC from entering deeper low‑power states > such as CXPC. > While PCIe D3cold support exists in the PCI core, host controller drivers > lack a common mechanism to determine whether it is safe to power off the > host bridge without breaking active devices or wakeup functionality. > As a result, controllers either avoid entering D3cold or depend on rough, > driver‑specific workarounds. > This series addresses that gap. > 1. Introduces pci_host_common_can_enter_d3cold(), a helper that determines > whether a host bridge may enter D3cold based on downstream PCIe endpoint > state. The helper permits D3cold only when all *active* endpoints are > already in PCI_D3hot, and any wakeup‑enabled endpoint supports PME > from D3cold. > 2. Updates the Designware PCIe host driver to use this helper in the > suspend_noirq() path, replacing the existing heuristic that blocked > D3cold whenever L1 ASPM was enabled. > 3. Enables D3cold support for Qualcomm PCIe controllers by wiring them into > the DesignWare common suspend/resume flow and explicitly powering down > controller resources when all endpoints are in D3hot. > The immediate outcome of this series is that Qualcomm PCIe host bridges can > enter D3cold when all endpoints are in D3hot. > This is a necessary but not sufficient step toward unblocking CXPC. With > this series applied, CXPC can be achieved on systems with no attached NVMe > devices. Support for NVMe‑attached systems requires additional changes > in NVMe driver, which are being worked on separately. > Tested on: > - Qualcomm Lemans EVK, Monaco & sc7280 platforms. > Validation steps: > - Boot without NVMe attach: > * PCIe host enters D3cold during suspend > * SoC is able to reach CXPC provided other drivers also remove > their votes as part of suspend. I have been testing this patchset with Mani's patchset that is supposed to be related to NVMe on the Thinkpad X13s found at: https://lore.kernel.org/all/20260414-l1ss-fix-v1-0-adbb4555b5ab@oss.qualcomm.com/ v4 of this patchset *boots* along with Mani's patchset, however, v5 does not, and unfortunately, the machine does not seem to get to a point where I can even get logs from it. Do you know what I might be missing? I have *not* attempted to remove the nvme drive and boot off USB to test it. -- steev