From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 46AD4410D3D for ; Fri, 8 May 2026 19:02:12 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=205.220.180.131 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778266934; cv=none; b=JLs0/OkIl9maVqYNKmAAYRu6Szlyr9PoSIPKm788GZZjQ8+OUKtvoTcfW53rPfI/iFRN/w6/wtm7yk88MxQZA9dhrw50H80So+aNXvQzYEJJwCo4ZKIOVUE2lcABoXOT4F3CKEEiEUfSPh6K9KhHivkDfV4W/rUa/OR/SKG7A0w= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1778266934; c=relaxed/simple; bh=n4a2tW695t0t/CvpOqMfCwEfmwTX9fOF5Byhdyp+BT8=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=F71dMHZHB4qS8A0uXArBuCggq79IcnwHnYroEfYkEN/FKviVADLMOjeaNhMaSEQd4lN+0z5kb91WovVzn1dDVUeWiQzFyyBoXSE0jwdlLqQ0HmzgMNbo0Eet+hA+L1fA3NfE2RdxuLJbGN7ONyWo2vez32vs7rtI67PghxPFAAQ= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com; spf=pass smtp.mailfrom=oss.qualcomm.com; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b=I80FktRJ; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b=WSLwbXe6; arc=none smtp.client-ip=205.220.180.131 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=oss.qualcomm.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com header.b="I80FktRJ"; dkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com header.b="WSLwbXe6" Received: from pps.filterd (m0279869.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id 648DDQL61173959 for ; Fri, 8 May 2026 19:02:11 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=qcppdkim1; bh= NUaGFY4uG/wsAI2XS7PoFgE9KxBgKk/nbUMH4o35YtI=; b=I80FktRJMYnq/xY8 eZJmFgzGwW5nTmpA5Jbil1Xm2/AYl4lKUNamjOaOO43SsilSOQXGHoFbjwmmbZey wTfiGag/QvEu0NSvOmHKFKBtT99qk/A5jZjDqAISvsutmfv/9e1V0xXSGrqK7Ifv pdfDByKQLLc8M+7M+1cA3dWf+jV8m1NHMV2L3+xQxm9lsROSD5sqCSQU1tk6R+V9 zCwjWE1rN5QlgOxZPtoulro3eIDpcwSk26CmZXOa8bDkxFWoTqhMKJYpHlN9NY2A 9ta6nY1HhiltfuSqU/A2ayuuSiQ5iIMZm8rOKNZvklXxPgxvK+uViCztDAzUrM9e L+rlOQ== Received: from mail-pg1-f198.google.com (mail-pg1-f198.google.com [209.85.215.198]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4e132hccvb-1 (version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT) for ; Fri, 08 May 2026 19:02:11 +0000 (GMT) Received: by mail-pg1-f198.google.com with SMTP id 41be03b00d2f7-c709551ec08so2616691a12.3 for ; Fri, 08 May 2026 12:02:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=oss.qualcomm.com; s=google; t=1778266930; x=1778871730; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=NUaGFY4uG/wsAI2XS7PoFgE9KxBgKk/nbUMH4o35YtI=; b=WSLwbXe6S/dMutWQl3KsUEuhKcRm9hK0fJHtQ4UFxgtLbUJKytw55SIWdsIj5XklRG ne0Ifq1+h4tNuxOHNIRWVYpArX4wzlZjizwqC05RIz1ye+AsF1tOSxhORltIxzyk2hc5 ZX+NjVsNkm61sO7mqYQdgCr0E7bkYcqp8lDCgkGzh1AZyzOgdGjcmJessgroKQSHLAoH goOPKQJ1VPC6EwPb5lHBGwUKt9jfG+yCbvNOufv7zow5o9mgtkiGv8WdEPCcjn5EzTEN OhnYZ+GsB8rT2hQVMhTEWd8w9w10zYpKXKmJMQXzppzlLkFWyGBpfr7q/CgtpTawnIzj Z2yw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1778266930; x=1778871730; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to; bh=NUaGFY4uG/wsAI2XS7PoFgE9KxBgKk/nbUMH4o35YtI=; b=K3yPftQzgGDIIupxKTmuQrbg5H/oeOHkSZ2OoaOtdnjltD9RZ5DotKh2r3OTRSqoNH FS9MtpagXe273PTtYWhxyTK1iR0OmmN0mUioj00OI8STX7kvmzE+26xrTfRjpYX2avcm HpQlZduKgWu6z9haiDNQTf1DoWEVHLQarjTb6upkdbgdfQU1WdD8P1/qZ4FcCip1r2xi V9hXwJa4YfyS+exaB2k0FYe2gfSSx6jr7kksgRGahnWEcVNGf4fVwbau/tbHxwLNn/Vk LII3b+UvuUvXpEFF+nSDfCIkx+j5FNC70rw0a5A/+ZfORj5zy444pgv2z2VVb5ppSwhb yJEA== X-Forwarded-Encrypted: i=1; AFNElJ99GvfvulfZFicjMglrTrUEiQti7ESTQxUOSjszbZr+NQGDl0h1YZsMguh/8lzbKFS7cN49hu4DWRFn8r2K@vger.kernel.org X-Gm-Message-State: AOJu0Yydi0AKPnrBsnXWQ/Qw3AcGWfOhwF1cS/lCGtb29rIr2tDlvyHK PlU3t8mX3/nO5ica/jO+faQUAOzZyb0AI0/sebDt3Rfeu0GfeoLwL8DHtsVSsiKbUPByCDtSyiT e9EeIV6zMfuxZv7rtPllv7Yg785QCEOtGwDL8Q1IkmaufeqNbggbyeE4MZsopu5WrBF2F X-Gm-Gg: AeBDiesQ6OOPSsc3hvd+SFv3q2nf5KtPrdSZgkqzgsUoF16gkOFmjn9R57uierx8T5G vr/3Bo7namkxg2OSD3taxHjfL8KcS1koscJvfU3DawkFutlBTVTjEGVqValRwQ7DPZPqZRTYfqd e5v3foCAQ4j6vzwYMejh3q5sdzWv0+sDlvUWLTBzGpzHW1n1TI1VWai4v7r5eYVWdSPzJ1En4MQ CQj8m9dtk1RoIzw4JrR1/Ox2e2PzMGdDjVMlgs4AMW7YzKOsHhN417mgJ4ATfeXEc0BTyLsnlL2 nvz31Xp2F4UCA+5xe+I2BDk2nBYRuklO2yC2uXNaid5JEWrOWW7ICVvoPylEvj6jLSJXVXcetyk hOGr6+QDiioiQCh/a3MCIfsmX1Uhwtp+Unb0BRcQlIlqb2fYcCCR9AQI= X-Received: by 2002:a05:6a00:198f:b0:838:1ece:9716 with SMTP id d2e1a72fcca58-83a5c5bd45cmr14044576b3a.22.1778266929612; Fri, 08 May 2026 12:02:09 -0700 (PDT) X-Received: by 2002:a05:6a00:198f:b0:838:1ece:9716 with SMTP id d2e1a72fcca58-83a5c5bd45cmr14044515b3a.22.1778266928888; Fri, 08 May 2026 12:02:08 -0700 (PDT) Received: from hu-bvisredd-hyd.qualcomm.com ([202.46.22.19]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-83965a3e3ecsm13395550b3a.19.2026.05.08.12.02.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 08 May 2026 12:02:08 -0700 (PDT) From: Vishnu Reddy Date: Sat, 09 May 2026 00:29:59 +0530 Subject: [PATCH v5 10/14] media: iris: Add power sequence for Glymur Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-Id: <20260509-glymur-v5-10-7fbb340c5dbd@oss.qualcomm.com> References: <20260509-glymur-v5-0-7fbb340c5dbd@oss.qualcomm.com> In-Reply-To: <20260509-glymur-v5-0-7fbb340c5dbd@oss.qualcomm.com> To: Vikash Garodia , Dikshita Agarwal , Abhinav Kumar , Bryan O'Donoghue , Mauro Carvalho Chehab , Joerg Roedel , Will Deacon , Robin Murphy , Hans Verkuil , Stefan Schmidt , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Stanimir Varbanov , Jorge Ramirez-Ortiz , Del Regno , Bjorn Andersson , Konrad Dybcio Cc: linux-kernel@vger.kernel.org, linux-media@vger.kernel.org, linux-arm-msm@vger.kernel.org, iommu@lists.linux.dev, Krzysztof Kozlowski , devicetree@vger.kernel.org, Vishnu Reddy X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1778266845; l=9169; i=busanna.reddy@oss.qualcomm.com; s=20260216; h=from:subject:message-id; bh=n4a2tW695t0t/CvpOqMfCwEfmwTX9fOF5Byhdyp+BT8=; b=pdCsMjG8JB+x1H4U5sQymr7L5UhTkyQFXmEbaXlzJUDUHUopxaz0m4Iro+KUODR9riHz3cl/0 vCS9tECQd+EDp+N6DBMfuaw/A5DPpEpA2VOslSzj0JbjwLhytc5h9l2 X-Developer-Key: i=busanna.reddy@oss.qualcomm.com; a=ed25519; pk=9vmy9HahBKVAa+GBFj1yHVbz0ey/ucIs1hrlfx+qtok= X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNTA4MDE5MCBTYWx0ZWRfX6Cygn0IN8Cii 3kiErLpHp3wi0S5DVhQeG2NIYt6MqrzyavJ851wNqhCE5MmvUaHUUIgGes4F5YLo66fxyrpPMHl IltnvN28itmvP/U6v9OISvlx5Yx3j0/fLuJmEk/mYhtiO4BGFDUsNZvXaqbyQAWeOxbQR3pqhNr LWospbFWDK8a5GDs9YEb4lz/SiEE3Y2rrOEgC9c+9+fxrADfPKgVHp4/2iLsdPa+FmfWQ1G2xS3 uPobz/rmvTXqCs3NicjjpCgmRifBgTsZIxzQAZKI3T3oHIJ/J0LdGi0/uyaTftV8t3VlcmB6CLT nIUpbGhphRUqsdQ5LvXNs9x51BTEDtkByKcno9vnAK6sONBTYPjel56nke+i6EnESrOeR1GusOI 9kEKROCpT7Ltc60PDvvHVT3fWo71FsN6nNgYYrG5a+Y97WLaEgEMrkyziL6TVeUGopHoMXhutbm lzB9YhXKFL6NBqnP3mg== X-Proofpoint-ORIG-GUID: tGuD0btimkojPAK4WcvuSNX6e5VrpsO_ X-Proofpoint-GUID: tGuD0btimkojPAK4WcvuSNX6e5VrpsO_ X-Authority-Analysis: v=2.4 cv=McxcfZ/f c=1 sm=1 tr=0 ts=69fe3333 cx=c_pps a=Qgeoaf8Lrialg5Z894R3/Q==:117 a=fChuTYTh2wq5r3m49p7fHw==:17 a=IkcTkHD0fZMA:10 a=NGcC8JguVDcA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=_glEPmIy2e8OvE2BGh3C:22 a=EUspDBNiAAAA:8 a=on-tpLi9NVdX0ogc7TgA:9 a=QEXdDO2ut3YA:10 a=x9snwWr2DeNwDh03kgHS:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-05-07_02,2026-05-08_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 malwarescore=0 suspectscore=0 spamscore=0 bulkscore=0 adultscore=0 priorityscore=1501 lowpriorityscore=0 impostorscore=0 phishscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2604200000 definitions=main-2605080190 Glymur has a secondary video codec core (vcodec1), equivalent to the primary core (vcodec0), but with independent power domains, clocks, and reset lines. Reuse the existing code wherever possible and add power sequence for vcodec1. Reviewed-by: Vikash Garodia Signed-off-by: Vishnu Reddy --- .../platform/qcom/iris/iris_platform_common.h | 4 + drivers/media/platform/qcom/iris/iris_vpu3x.c | 141 ++++++++++++++++++++- drivers/media/platform/qcom/iris/iris_vpu_common.h | 1 + .../platform/qcom/iris/iris_vpu_register_defines.h | 10 ++ 4 files changed, 154 insertions(+), 2 deletions(-) diff --git a/drivers/media/platform/qcom/iris/iris_platform_common.h b/drivers/media/platform/qcom/iris/iris_platform_common.h index 7d59e6364e9d..8995136ad29e 100644 --- a/drivers/media/platform/qcom/iris/iris_platform_common.h +++ b/drivers/media/platform/qcom/iris/iris_platform_common.h @@ -61,6 +61,9 @@ enum platform_clk_type { IRIS_VPP0_HW_CLK, IRIS_VPP1_HW_CLK, IRIS_APV_HW_CLK, + IRIS_AXI_VCODEC1_CLK, + IRIS_VCODEC1_CLK, + IRIS_VCODEC1_FREERUN_CLK, }; struct platform_clk_data { @@ -210,6 +213,7 @@ enum platform_pm_domain_type { IRIS_VPP0_HW_POWER_DOMAIN, IRIS_VPP1_HW_POWER_DOMAIN, IRIS_APV_HW_POWER_DOMAIN, + IRIS_VCODEC1_POWER_DOMAIN, }; struct platform_pd_data { diff --git a/drivers/media/platform/qcom/iris/iris_vpu3x.c b/drivers/media/platform/qcom/iris/iris_vpu3x.c index 13fbb21c2182..ff90c375e805 100644 --- a/drivers/media/platform/qcom/iris/iris_vpu3x.c +++ b/drivers/media/platform/qcom/iris/iris_vpu3x.c @@ -22,9 +22,19 @@ static bool iris_vpu3x_hw_power_collapsed(struct iris_core *core) u32 value, pwr_status; value = readl(core->reg_base + WRAPPER_CORE_POWER_STATUS); - pwr_status = value & BIT(1); + pwr_status = value & VCODEC0_POWER_STATUS; - return pwr_status ? false : true; + return !pwr_status; +} + +static bool iris_vpu36_hw1_power_collapsed(struct iris_core *core) +{ + u32 value, pwr_status; + + value = readl(core->reg_base + WRAPPER_CORE_POWER_STATUS); + pwr_status = value & VCODEC1_POWER_STATUS; + + return !pwr_status; } static void iris_vpu3_power_off_hardware(struct iris_core *core) @@ -254,6 +264,124 @@ static void iris_vpu35_power_off_hw(struct iris_core *core) iris_disable_unprepare_clock(core, IRIS_AXI_VCODEC_CLK); } +static int iris_vpu36_power_on_hw1(struct iris_core *core) +{ + int ret; + + ret = iris_enable_power_domains(core, IRIS_VCODEC1_POWER_DOMAIN); + if (ret) + return ret; + + ret = iris_prepare_enable_clock(core, IRIS_AXI_VCODEC1_CLK); + if (ret) + goto err_disable_hw1_power; + + ret = iris_prepare_enable_clock(core, IRIS_VCODEC1_FREERUN_CLK); + if (ret) + goto err_disable_axi1_clk; + + ret = iris_prepare_enable_clock(core, IRIS_VCODEC1_CLK); + if (ret) + goto err_disable_hw1_free_clk; + + return 0; + +err_disable_hw1_free_clk: + iris_disable_unprepare_clock(core, IRIS_VCODEC1_FREERUN_CLK); +err_disable_axi1_clk: + iris_disable_unprepare_clock(core, IRIS_AXI_VCODEC1_CLK); +err_disable_hw1_power: + iris_disable_power_domains(core, IRIS_VCODEC1_POWER_DOMAIN); + + return ret; +} + +static int iris_vpu36_power_on_hw(struct iris_core *core) +{ + int ret; + + ret = iris_vpu35_power_on_hw(core); + if (ret) + return ret; + + ret = iris_vpu36_power_on_hw1(core); + if (ret) + goto err_power_off_hw; + + return 0; + +err_power_off_hw: + iris_vpu35_power_off_hw(core); + + return ret; +} + +static void iris_vpu36_power_off_hw1(struct iris_core *core) +{ + u32 value, i; + int ret; + + if (iris_vpu36_hw1_power_collapsed(core)) + goto disable_power; + + value = readl(core->reg_base + WRAPPER_CORE_CLOCK_CONFIG); + if (value) + writel(CORE_CLK_RUN, core->reg_base + WRAPPER_CORE_CLOCK_CONFIG); + + for (i = 0; i < core->iris_platform_data->num_vpp_pipe; i++) { + ret = readl_poll_timeout(core->reg_base + VCODEC1_SS_IDLE_STATUSN + 4 * i, + value, value & DMA_NOC_IDLE, 2000, 20000); + if (ret) + goto disable_power; + } + + writel(REQ_VCODEC1_POWER_DOWN_PREP, core->reg_base + AON_WRAPPER_MVP_NOC_LPI_CONTROL); + ret = readl_poll_timeout(core->reg_base + AON_WRAPPER_MVP_NOC_LPI_STATUS, + value, value & NOC_LPI_VCODEC1_STATUS_DONE, 2000, 20000); + if (ret) + goto disable_power; + + writel(0, core->reg_base + AON_WRAPPER_MVP_NOC_LPI_CONTROL); + + writel(VCODEC1_BRIDGE_SW_RESET | VCODEC1_BRIDGE_HW_RESET_DISABLE, core->reg_base + + CPU_CS_AHB_BRIDGE_SYNC_RESET); + writel(VCODEC1_BRIDGE_HW_RESET_DISABLE, core->reg_base + CPU_CS_AHB_BRIDGE_SYNC_RESET); + writel(0x0, core->reg_base + CPU_CS_AHB_BRIDGE_SYNC_RESET); + +disable_power: + iris_genpd_set_hwmode(core, IRIS_VCODEC1_POWER_DOMAIN, false); + iris_disable_unprepare_clock(core, IRIS_VCODEC1_CLK); + iris_disable_unprepare_clock(core, IRIS_VCODEC1_FREERUN_CLK); + iris_disable_unprepare_clock(core, IRIS_AXI_VCODEC1_CLK); + iris_disable_power_domains(core, IRIS_VCODEC1_POWER_DOMAIN); +} + +static void iris_vpu36_power_off_hw(struct iris_core *core) +{ + iris_vpu35_power_off_hw(core); + iris_vpu36_power_off_hw1(core); +} + +static int iris_vpu36_set_hwmode(struct iris_core *core) +{ + int ret; + + ret = iris_genpd_set_hwmode(core, IRIS_VCODEC_POWER_DOMAIN, true); + if (ret) + return ret; + + ret = iris_genpd_set_hwmode(core, IRIS_VCODEC1_POWER_DOMAIN, true); + if (ret) + goto error_disable_vcodec_hwmode; + + return 0; + +error_disable_vcodec_hwmode: + iris_genpd_set_hwmode(core, IRIS_VCODEC_POWER_DOMAIN, false); + + return ret; +} + const struct vpu_ops iris_vpu3_ops = { .power_off_hw = iris_vpu3_power_off_hardware, .power_on_hw = iris_vpu_power_on_hw, @@ -281,3 +409,12 @@ const struct vpu_ops iris_vpu35_ops = { .calc_freq = iris_vpu3x_vpu4x_calculate_frequency, .set_hwmode = iris_vpu_set_hwmode, }; + +const struct vpu_ops iris_vpu36_ops = { + .power_off_hw = iris_vpu36_power_off_hw, + .power_on_hw = iris_vpu36_power_on_hw, + .power_off_controller = iris_vpu35_vpu4x_power_off_controller, + .power_on_controller = iris_vpu35_vpu4x_power_on_controller, + .calc_freq = iris_vpu3x_vpu4x_calculate_frequency, + .set_hwmode = iris_vpu36_set_hwmode, +}; diff --git a/drivers/media/platform/qcom/iris/iris_vpu_common.h b/drivers/media/platform/qcom/iris/iris_vpu_common.h index dee3b1349c5e..bee8ae9b4308 100644 --- a/drivers/media/platform/qcom/iris/iris_vpu_common.h +++ b/drivers/media/platform/qcom/iris/iris_vpu_common.h @@ -12,6 +12,7 @@ extern const struct vpu_ops iris_vpu2_ops; extern const struct vpu_ops iris_vpu3_ops; extern const struct vpu_ops iris_vpu33_ops; extern const struct vpu_ops iris_vpu35_ops; +extern const struct vpu_ops iris_vpu36_ops; extern const struct vpu_ops iris_vpu4x_ops; struct vpu_ops { diff --git a/drivers/media/platform/qcom/iris/iris_vpu_register_defines.h b/drivers/media/platform/qcom/iris/iris_vpu_register_defines.h index 72168b9ffa73..e67d98b8c91e 100644 --- a/drivers/media/platform/qcom/iris/iris_vpu_register_defines.h +++ b/drivers/media/platform/qcom/iris/iris_vpu_register_defines.h @@ -7,6 +7,7 @@ #define __IRIS_VPU_REGISTER_DEFINES_H__ #define VCODEC_BASE_OFFS 0x00000000 +#define VCODEC1_BASE_OFFS 0x00040000 #define AON_MVP_NOC_RESET 0x0001F000 #define CPU_BASE_OFFS 0x000A0000 #define WRAPPER_BASE_OFFS 0x000B0000 @@ -14,6 +15,8 @@ #define AON_BASE_OFFS 0x000E0000 #define VCODEC_SS_IDLE_STATUSN (VCODEC_BASE_OFFS + 0x70) +#define VCODEC1_SS_IDLE_STATUSN (VCODEC1_BASE_OFFS + 0x70) +#define DMA_NOC_IDLE BIT(22) #define AON_WRAPPER_MVP_NOC_RESET_REQ (AON_MVP_NOC_RESET + 0x000) #define VIDEO_NOC_RESET_REQ (BIT(0) | BIT(1)) @@ -35,6 +38,8 @@ #define CPU_CS_AHB_BRIDGE_SYNC_RESET (CPU_CS_BASE_OFFS + 0x160) #define CORE_BRIDGE_SW_RESET BIT(0) #define CORE_BRIDGE_HW_RESET_DISABLE BIT(1) +#define VCODEC1_BRIDGE_SW_RESET BIT(2) +#define VCODEC1_BRIDGE_HW_RESET_DISABLE BIT(3) #define CPU_CS_X2RPMH (CPU_CS_BASE_OFFS + 0x168) #define MSK_SIGNAL_FROM_TENSILICA BIT(0) @@ -52,14 +57,19 @@ #define WRAPPER_DEBUG_BRIDGE_LPI_STATUS (WRAPPER_BASE_OFFS + 0x58) #define WRAPPER_IRIS_CPU_NOC_LPI_CONTROL (WRAPPER_BASE_OFFS + 0x5C) #define REQ_POWER_DOWN_PREP BIT(0) +#define REQ_VCODEC1_POWER_DOWN_PREP BIT(1) #define WRAPPER_IRIS_CPU_NOC_LPI_STATUS (WRAPPER_BASE_OFFS + 0x60) #define NOC_LPI_STATUS_DONE BIT(0) /* Indicates the NOC handshake is complete */ #define NOC_LPI_STATUS_DENY BIT(1) /* Indicates the NOC handshake is denied */ #define NOC_LPI_STATUS_ACTIVE BIT(2) /* Indicates the NOC is active */ +#define NOC_LPI_VCODEC1_STATUS_DONE BIT(8) #define WRAPPER_IRIS_VCODEC_VPU_WRAPPER_SPARE_0 (WRAPPER_BASE_OFFS + 0x78) #define WRAPPER_CORE_POWER_STATUS (WRAPPER_BASE_OFFS + 0x80) +#define VCODEC0_POWER_STATUS BIT(1) +#define VCODEC1_POWER_STATUS BIT(4) + #define WRAPPER_CORE_CLOCK_CONFIG (WRAPPER_BASE_OFFS + 0x88) #define CORE_CLK_RUN 0x0 -- 2.34.1