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Thu, 14 May 2026 06:54:49 -0700 (PDT) X-Received: by 2002:a05:6a00:194e:b0:837:40f6:cb88 with SMTP id d2e1a72fcca58-83f0427d8b2mr8611772b3a.26.1778766888800; Thu, 14 May 2026 06:54:48 -0700 (PDT) Received: from localhost ([2601:1c0:5000:d5c:4ec8:83f5:8254:6891]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-83f19f79b60sm3162132b3a.52.2026.05.14.06.54.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 14 May 2026 06:54:47 -0700 (PDT) From: Rob Clark To: dri-devel@lists.freedesktop.org Cc: linux-arm-msm@vger.kernel.org, freedreno@lists.freedesktop.org, Akhil P Oommen , Anna Maniscalco , Rob Clark , Sean Paul , Konrad Dybcio , Dmitry Baryshkov , Abhinav Kumar , Jessica Zhang , Marijn Suijten , David Airlie , Simona Vetter , linux-kernel@vger.kernel.org (open list) Subject: [PATCH v6 16/16] drm/msm/a6xx: Allow IFPC with perfcntr stream Date: Thu, 14 May 2026 06:40:04 -0700 Message-ID: <20260514134052.361771-17-robin.clark@oss.qualcomm.com> X-Mailer: git-send-email 2.54.0 In-Reply-To: <20260514134052.361771-1-robin.clark@oss.qualcomm.com> References: <20260514134052.361771-1-robin.clark@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Proofpoint-GUID: uTTSefkEgxASVe3OqILb98cC9c-nwfT4 X-Authority-Analysis: v=2.4 cv=R74z39RX c=1 sm=1 tr=0 ts=6a05d42a cx=c_pps a=mDZGXZTwRPZaeRUbqKGCBw==:117 a=xqWC_Br6kY4A:10 a=NGcC8JguVDcA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=3WHJM1ZQz_JShphwDgj5:22 a=EUspDBNiAAAA:8 a=pGLkceISAAAA:8 a=5obZvuzjGUYrwyXX1KsA:9 a=zc0IvFSfCIW2DFIPzwfm:22 X-Proofpoint-ORIG-GUID: uTTSefkEgxASVe3OqILb98cC9c-nwfT4 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNTE0MDE0MCBTYWx0ZWRfX46gQcd/sZw7w afpYyG/X0Vl9dR7mQmGQtC4uRqnKuU2pmFUFMNGGUHoHpF4KDj6GCM5KamcEk/FuLn/7dk0hXf+ 7cDL7L0JM2hwY5IgB2nzzgpXu8NHaMVD/PPdFWX2i9Vt60cVn6xO8WrAXYpfAaTZdgQsviTeqv7 PVyhonL/ahTc3T31N2mpzXztL2aHyjD7GZAiVrukOR2jgyBlLX5V+exYBlwFNgzMXZK+fzMfFIc Zf5llwBMmzA9IPAXF+VRHJrG+pn7K1YOACGRzRlo+cObUIN6SUj8sGJ347eR2tb4mFNf22zG8LT jGTYB7xQgaf4xpXh2sBRLoIdnPQuJRkqKVJCbaMWH5x9a8CDy6IU9fLTrjL/XdrA+zQgZyJ0IqX HOY1vE53tWxmDE40v0TfrocFgoOY3feMjq18GfO872gu2EzWT6kAotX1lbJdZEJBT/8HNyY9kRO BI42MPJufgD1FEyOAFA== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-05-14_03,2026-05-13_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 suspectscore=0 impostorscore=0 adultscore=0 lowpriorityscore=0 clxscore=1015 phishscore=0 priorityscore=1501 bulkscore=0 malwarescore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2605050000 definitions=main-2605140140 Now that the dynamic pwrup reglist has SEL reg values to restore appended, so that SEL regs are restored on IFPC exit, we can stop completely disabling IFPC while global counter sampling is active. To accomplish this, we re-use sysprof_setup() with a force_on param to inhibit IFPC specifically while the counter regs are being read, while leaving IFPC enabled the rest of the time. Signed-off-by: Rob Clark Reviewed-by: Anna Maniscalco --- drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 4 ++-- drivers/gpu/drm/msm/adreno/a6xx_gpu.h | 2 +- drivers/gpu/drm/msm/msm_gpu.h | 10 ++-------- drivers/gpu/drm/msm/msm_perfcntr.c | 8 ++++++++ drivers/gpu/drm/msm/msm_submitqueue.c | 2 +- 5 files changed, 14 insertions(+), 12 deletions(-) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c index aba08fb76249..0a7d49a2c877 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c @@ -2034,9 +2034,9 @@ static int a6xx_gmu_get_irq(struct a6xx_gmu *gmu, struct platform_device *pdev, return irq; } -void a6xx_gmu_sysprof_setup(struct msm_gpu *gpu) +void a6xx_gmu_sysprof_setup(struct msm_gpu *gpu, bool force_on) { - bool sysprof = msm_gpu_sysprof_no_ifpc(gpu); + bool sysprof = msm_gpu_sysprof_no_ifpc(gpu) || force_on; struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu); struct a6xx_gmu *gmu = &a6xx_gpu->gmu; diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.h b/drivers/gpu/drm/msm/adreno/a6xx_gpu.h index f3cc9478b079..eecc71843bed 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.h +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.h @@ -280,7 +280,7 @@ void a6xx_gmu_clear_oob(struct a6xx_gmu *gmu, enum a6xx_gmu_oob_state state); int a6xx_gmu_init(struct a6xx_gpu *a6xx_gpu, struct device_node *node); int a6xx_gmu_wrapper_init(struct a6xx_gpu *a6xx_gpu, struct device_node *node); void a6xx_gmu_remove(struct a6xx_gpu *a6xx_gpu); -void a6xx_gmu_sysprof_setup(struct msm_gpu *gpu); +void a6xx_gmu_sysprof_setup(struct msm_gpu *gpu, bool force_on); void a6xx_preempt_init(struct msm_gpu *gpu); void a6xx_preempt_hw_init(struct msm_gpu *gpu); diff --git a/drivers/gpu/drm/msm/msm_gpu.h b/drivers/gpu/drm/msm/msm_gpu.h index cb74b7606987..e3b5fab6f68f 100644 --- a/drivers/gpu/drm/msm/msm_gpu.h +++ b/drivers/gpu/drm/msm/msm_gpu.h @@ -93,7 +93,7 @@ struct msm_gpu_funcs { * for cmdstream that is buffered in this FIFO upstream of the CP fw. */ bool (*progress)(struct msm_gpu *gpu, struct msm_ringbuffer *ring); - void (*sysprof_setup)(struct msm_gpu *gpu); + void (*sysprof_setup)(struct msm_gpu *gpu, bool force_on); /* Configure perfcntr SELect regs: */ void (*perfcntr_configure)(struct msm_gpu *gpu, struct msm_ringbuffer *ring, @@ -378,13 +378,7 @@ msm_gpu_sysprof_no_perfcntr_zap(struct msm_gpu *gpu) static inline bool msm_gpu_sysprof_no_ifpc(struct msm_gpu *gpu) { - /* - * For now, this is the same condition as disabling perfcntr clears - * on context switch. But once kernel perfcntr IFPC support is in - * place, we will only need to disable IFPC for legacy userspace - * setting SYSPROF param. - */ - return msm_gpu_sysprof_no_perfcntr_zap(gpu); + return refcount_read(&gpu->sysprof_active) > 1; } /* diff --git a/drivers/gpu/drm/msm/msm_perfcntr.c b/drivers/gpu/drm/msm/msm_perfcntr.c index d6716ce0657a..df8c2602b4bc 100644 --- a/drivers/gpu/drm/msm/msm_perfcntr.c +++ b/drivers/gpu/drm/msm/msm_perfcntr.c @@ -261,6 +261,10 @@ sample_worker(struct kthread_work *work) return; } + /* Inhibit IFPC while accessing registers: */ + if (gpu->funcs->sysprof_setup) + gpu->funcs->sysprof_setup(gpu, true); + if (gpu->funcs->perfcntr_flush) gpu->funcs->perfcntr_flush(gpu); @@ -295,6 +299,10 @@ sample_worker(struct kthread_work *work) } } + /* Re-enable IFPC: */ + if (gpu->funcs->sysprof_setup) + gpu->funcs->sysprof_setup(gpu, false); + smp_store_release(&stream->fifo.head, head); wake_up_all(&stream->poll_wq); } diff --git a/drivers/gpu/drm/msm/msm_submitqueue.c b/drivers/gpu/drm/msm/msm_submitqueue.c index a58fe41602c6..1a5a77b28016 100644 --- a/drivers/gpu/drm/msm/msm_submitqueue.c +++ b/drivers/gpu/drm/msm/msm_submitqueue.c @@ -42,7 +42,7 @@ int msm_context_set_sysprof(struct msm_context *ctx, struct msm_gpu *gpu, int sy /* Some gpu families require additional setup for sysprof */ if (gpu->funcs->sysprof_setup) - gpu->funcs->sysprof_setup(gpu); + gpu->funcs->sysprof_setup(gpu, false); ctx->sysprof = sysprof; -- 2.54.0