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Tue, 20 Oct 2026 06:24:28 -0700 (PDT) Received: from DESKTOP-NM9EKIA ([125.134.240.130]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2ea1fd8a55asm7010935ad.29.2026.10.20.06.24.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 20 Oct 2026 06:24:27 -0700 (PDT) From: joonhoekim <26rote@gmail.com> To: Qianhui Xu Cc: Joonhoe Kim <26rote@gmail.com>, Arpit Saini , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org Subject: Re: [PATCH] drm/msm/dsi: fix AHB clock staying enabled across suspend Date: Tue, 20 Oct 2026 22:24:14 +0900 Message-ID: <20261020132424.983-1-26rote@gmail.com> X-Mailer: git-send-email 2.55.0.windows.5 In-Reply-To: <179241542813.315541.11037007061803544238@mail.ustc.edu.cn> References: <20261006-dsi-ahb-clk-suspend-fix-v1-1-67da848e1b0a@oss.qualcomm.com> <20261016125036.1069-1-26rote@gmail.com> <179241542813.315541.11037007061803544238@mail.ustc.edu.cn> X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Transfer-Encoding: 8bit From: Joonhoe Kim <26rote@gmail.com> On Mon, Oct 19, 2026 at 09:10:28PM +0800, Qianhui Xu wrote: > Question: with your runtime-callback variant, does dispcc end up suspended > after DPMS off, and does the panel still come back on DPMS on? Yes to both, on SM8850 with v7.3-rc4. With the display off and the system awake: current code and Arpit's patch: disp_cc_mdss_ahb_clk prepared twice, dispcc runtime active, MMCX on prepare only in the PHY runtime callbacks: prepare count 0, dispcc runtime suspended, MMCX off The panel came back on every one of 30 DPMS off/on cycles with that variant. I repeated it today with the same variant on v7.3-rc4, blanking both outputs from the compositor, with nothing on DisplayPort and with four different sinks (a 4K TV and monitors at 5120x2160, 2560x1600 and 1920x2400): nothing on DP: DPU, both DSI and their PHYs, the DP controller, MDSS and dispcc all runtime suspended, disp_cc_mdss_ahb_clk enable=0 prepare=0 sink on DP: DPU, DSI and PHYs suspended, but the DP controller, MDSS and dispcc stay runtime active, disp_cc_mdss_ahb_clk enable=2 prepare=2 So here the remaining dispcc reference comes from the DP side while a sink is connected, and the display controller does not keep the MDP clock when blanked. This tree carries my DP patch that holds one runtime PM reference per plugged sink, so the DP part may differ from mainline. Arpit, thanks for confirming it is prepare=1 with enable=0 on your board during s2idle; that matches what I see. I could not measure a difference from it in s2idle (CX collapse counts were the same in all three cases), only in the display-off, system-awake case above. Thanks, Joonhoe Kim