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Tue, 20 Oct 2026 07:23:06 -0700 (PDT) Received: from redducc.localdomain ([183.83.156.125]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-36081ab80f9sm66917444eec.12.2026.10.20.07.22.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 20 Oct 2026 07:23:03 -0700 (PDT) From: Sushmit Singh Rathore To: Bjorn Andersson , Stephen Boyd Cc: Abel Vesa , Abel Vesa , Brian Masney , Jerome Brunet , Vinod Koul , Vladimir Zapolskiy , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, Sushmit Singh Rathore Subject: [PATCH v2 2/3] clk: qcom: camcc-sm8450: Retain flops across camera GDSC collapse Date: Tue, 20 Oct 2026 14:21:30 +0000 Message-ID: <20261020142157.1749-3-sushmit718@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20261020142157.1749-1-sushmit718@gmail.com> References: <20261020142157.1749-1-sushmit718@gmail.com> X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Transfer-Encoding: 8bit The camera GDSCs are collapsed between camera sessions. Without flop retention and with the default clock-disable wait, the IFE GDSC can stay stuck off when it is powered up for the next session. Program the same wait values and set RETAIN_FF_ENABLE as camcc-sm8550 and the downstream camera clock controller driver do for these GDSCs. Tested on the Nothing Phone (2) (SM8475) by running repeated camera sessions. Fixes: 6082037fe62e ("clk: qcom: add camera clock controller driver for SM8450 SoC") Assisted-by: LLM Signed-off-by: Sushmit Singh Rathore --- Changes in v2: - Use full name in From and Signed-off-by. drivers/clk/qcom/camcc-sm8450.c | 45 ++++++++++++++++++++++++++------- 1 file changed, 36 insertions(+), 9 deletions(-) diff --git a/drivers/clk/qcom/camcc-sm8450.c b/drivers/clk/qcom/camcc-sm8450.c index 4025db23d1a9..9f1dd51db0d5 100644 --- a/drivers/clk/qcom/camcc-sm8450.c +++ b/drivers/clk/qcom/camcc-sm8450.c @@ -2930,90 +2930,117 @@ static struct gdsc titan_top_gdsc; static struct gdsc bps_gdsc = { .gdscr = 0x10004, + .en_rest_wait_val = 0x2, + .en_few_wait_val = 0x2, + .clk_dis_wait_val = 0xf, .pd = { .name = "bps_gdsc", }, - .flags = HW_CTRL | POLL_CFG_GDSCR, + .flags = HW_CTRL | POLL_CFG_GDSCR | RETAIN_FF_ENABLE, .parent = &titan_top_gdsc.pd, .pwrsts = PWRSTS_OFF_ON, }; static struct gdsc ipe_0_gdsc = { .gdscr = 0x10078, + .en_rest_wait_val = 0x2, + .en_few_wait_val = 0x2, + .clk_dis_wait_val = 0xf, .pd = { .name = "ipe_0_gdsc", }, - .flags = HW_CTRL | POLL_CFG_GDSCR, + .flags = HW_CTRL | POLL_CFG_GDSCR | RETAIN_FF_ENABLE, .parent = &titan_top_gdsc.pd, .pwrsts = PWRSTS_OFF_ON, }; static struct gdsc sbi_gdsc = { .gdscr = 0x100d0, + .en_rest_wait_val = 0x2, + .en_few_wait_val = 0x2, + .clk_dis_wait_val = 0xf, .pd = { .name = "sbi_gdsc", }, - .flags = POLL_CFG_GDSCR, + .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE, .parent = &titan_top_gdsc.pd, .pwrsts = PWRSTS_OFF_ON, }; static struct gdsc ife_0_gdsc = { .gdscr = 0x11004, + .en_rest_wait_val = 0x2, + .en_few_wait_val = 0x2, + .clk_dis_wait_val = 0xf, .pd = { .name = "ife_0_gdsc", }, - .flags = POLL_CFG_GDSCR, + .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE, .parent = &titan_top_gdsc.pd, .pwrsts = PWRSTS_OFF_ON, }; static struct gdsc ife_1_gdsc = { .gdscr = 0x12004, + .en_rest_wait_val = 0x2, + .en_few_wait_val = 0x2, + .clk_dis_wait_val = 0xf, .pd = { .name = "ife_1_gdsc", }, - .flags = POLL_CFG_GDSCR, + .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE, .parent = &titan_top_gdsc.pd, .pwrsts = PWRSTS_OFF_ON, }; static struct gdsc ife_2_gdsc = { .gdscr = 0x12050, + .en_rest_wait_val = 0x2, + .en_few_wait_val = 0x2, + .clk_dis_wait_val = 0xf, .pd = { .name = "ife_2_gdsc", }, - .flags = POLL_CFG_GDSCR, + .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE, .parent = &titan_top_gdsc.pd, .pwrsts = PWRSTS_OFF_ON, }; static struct gdsc sfe_0_gdsc = { .gdscr = 0x13050, + .en_rest_wait_val = 0x2, + .en_few_wait_val = 0x2, + .clk_dis_wait_val = 0xf, .pd = { .name = "sfe_0_gdsc", }, - .flags = POLL_CFG_GDSCR, + .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE, .parent = &titan_top_gdsc.pd, .pwrsts = PWRSTS_OFF_ON, }; static struct gdsc sfe_1_gdsc = { .gdscr = 0x13098, + .en_rest_wait_val = 0x2, + .en_few_wait_val = 0x2, + .clk_dis_wait_val = 0xf, .pd = { .name = "sfe_1_gdsc", }, - .flags = POLL_CFG_GDSCR, + .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE, .parent = &titan_top_gdsc.pd, .pwrsts = PWRSTS_OFF_ON, }; static struct gdsc titan_top_gdsc = { .gdscr = 0x131dc, + .en_rest_wait_val = 0x2, + .en_few_wait_val = 0x2, + .clk_dis_wait_val = 0xf, .pd = { .name = "titan_top_gdsc", }, - .flags = POLL_CFG_GDSCR, + .flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE, .pwrsts = PWRSTS_OFF_ON, }; -- 2.43.0