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[213.149.37.24]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-48e3ecd35c2sm3544825f8f.39.2026.10.24.03.34.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 24 Oct 2026 03:34:12 -0700 (PDT) From: Robert Marko To: andersson@kernel.org, abelvesa@kernel.org, sboyd@kernel.org, bmasney+clk@redhat.com, jbrunet+clk@baylibre.com, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, konradybcio@kernel.org, taniya.das@oss.qualcomm.com, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Robert Marko Subject: [PATCH 2/2] arm64: dts: qcom: ipq8074: Add CMN PLL Date: Sat, 24 Oct 2026 12:33:10 +0200 Message-ID: <20261024103401.761125-2-robimarko@gmail.com> X-Mailer: git-send-email 2.56.0 In-Reply-To: <20261024103401.761125-1-robimarko@gmail.com> References: <20261024103401.761125-1-robimarko@gmail.com> X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Add the CMN PLL node, it will be used to feed the required fixed clocks to networking subsystem. CMN PLL provides bias_pll_cc_clk and bias_pll_nss_noc_clk to GCC. Signed-off-by: Robert Marko --- arch/arm64/boot/dts/qcom/ipq8074.dtsi | 27 +++++++++++++++++++++++++-- 1 file changed, 25 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/ipq8074.dtsi b/arch/arm64/boot/dts/qcom/ipq8074.dtsi index 75a5ae30d966..8afc63a72144 100644 --- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi @@ -5,6 +5,7 @@ #include #include +#include / { #address-cells = <2>; @@ -15,6 +16,12 @@ / { interrupt-parent = <&intc>; clocks { + ref_48mhz_clk: ref-48mhz-clk { + compatible = "fixed-clock"; + clock-frequency = <48000000>; + #clock-cells = <0>; + }; + sleep_clk: sleep_clk { compatible = "fixed-clock"; clock-frequency = <32768>; @@ -257,6 +264,18 @@ mdio: mdio@90000 { status = "disabled"; }; + cmn_pll: clock-controller@9b000 { + compatible = "qcom,ipq8074-cmn-pll"; + reg = <0x0009b000 0x800>; + clocks = <&ref_48mhz_clk>, + <&gcc GCC_CMN_12GPLL_AHB_CLK>, + <&gcc GCC_CMN_12GPLL_SYS_CLK>; + clock-names = "ref", "ahb", "sys"; + #clock-cells = <1>; + assigned-clocks = <&cmn_pll IPQ8074_CMN_PLL_CLK>; + assigned-clock-rates-u64 = /bits/ 64 <12000000000>; + }; + qfprom: efuse@a4000 { compatible = "qcom,ipq8074-qfprom", "qcom,qfprom"; reg = <0x000a4000 0x2000>; @@ -369,11 +388,15 @@ gcc: clock-controller@1800000 { clocks = <&xo>, <&sleep_clk>, <&pcie_qmp0>, - <&pcie_qmp1>; + <&pcie_qmp1>, + <&cmn_pll IPQ8074_BIAS_PLL_CC_CLK>, + <&cmn_pll IPQ8074_BIAS_PLL_NSS_NOC_CLK>; clock-names = "xo", "sleep_clk", "pcie0_pipe", - "pcie1_pipe"; + "pcie1_pipe", + "bias_pll_cc_clk", + "bias_pll_nss_noc_clk"; #clock-cells = <1>; #power-domain-cells = <1>; #reset-cells = <1>; -- 2.56.0