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[77.97.36.129]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-48e71b728ddsm158055f8f.9.2026.10.29.17.49.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 29 Oct 2026 17:49:15 -0700 (PDT) From: Filippo Falezza To: Sreeshankar K Cc: Filippo Falezza , andersson@kernel.org, sboyd@kernel.org, bmasney+clk@redhat.com, jbrunet+clk@baylibre.com, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, rafael@kernel.org, viresh.kumar@linaro.org, konradybcio@kernel.org, danila@mainlining.org, davidwronek@gmail.com, mani@kernel.org, robimarko@gmail.com, linux@gurudas.dev, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org Subject: Re: [PATCH v11 0/5] Add initial support for Qualcomm SM7250 SoC Date: Fri, 30 Oct 2026 00:48:43 +0000 Message-ID: <20261030004903.1068342-1-effeffe99@gmail.com> X-Mailer: git-send-email 2.56.0 In-Reply-To: <20261016042432.824-1-sreeshankar0910@gmail.com> References: <20261016042432.824-1-sreeshankar0910@gmail.com> X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Hello Sreeshankar, I'm bringing up mainline on a Motorola Moto G 5G Plus (XT2075-3, "nairo", SM7250), and your series is the base of it: I carried v9 and have now moved to v11, on top of next-20261021. On top of it I have the rest of what the phone needs at SoC level: TLMM, the apps SMMU, USB 2.0, UFS, SDHC, the GPU and display, interconnects, IPCC/AOSS, the modem, Wi-Fi, IPA, TSENS and the ADSP with the LPASS codec macros. With v11 in place of v9 (only the GCC driver differs), plus the two sm7250.dtsi changes below, the phone boots with no stuck clocks or GDSC errors, and the clock messages at boot are the same as with v9. UFS, the SD card, the USB gadget, the GPU and display, Wi-Fi, the modem with SMS and calls, and audio all work, and three s2idle cycles resume with USB, UFS and Wi-Fi intact, as does a wakeup by SMS. Tested-by: Filippo Falezza # Motorola Moto G 5G Plus (SM7250) Two changes to sm7250.dtsi that I carry for the phone: The cpu-map puts core6 in cluster1 and core7 in cluster2. The kernel then prints "/cpus/cpu-map/cluster1: empty cluster" and drops the whole cpu-map, since it looks for core0, core1, ... in each cluster. SM7250 is a single DynamIQ cluster, so I put all eight cores in cluster0, as sm8250.dtsi does. This is the same thing the review bot raised on 5/5. The cluster idle states: the downstream lito devicetree uses the modes 0x224 and 0xc24 for the two cluster power-collapse states, which gives arm,psci-suspend-param = <0x41002244> and <0x4100c244> rather than <0x41001244> and <0x4100b244>. With those values the RPMh sleep stats show the SoC reaching CX collapse and AOSS sleep in s2idle. I haven't checked what the current values do. I'm happy to send both as patches on top of your series, or you can fold them into the next version, whichever you prefer. On 2/5, the bot's point about ftbl_gcc_cpuss_ahb_clk_src looks right to me: v11 changed its source from P_BI_TCXO to DT_BI_TCXO_AO, but the table entry needs the parent map's source value, which is P_BI_TCXO. Nothing sets that rate on the phone, so I can't confirm it at runtime. Once your series is in, I'd like to send the remaining SoC support and the board devicetree, so that sm7250.dtsi has a board using it. Are you working on any of those parts yourself? I'd rather not duplicate your work, and I can send them as a series that depends on yours in the meantime. I did the testing and wrote this note with the help of an AI coding assistant (Claude Code); the results are from the phone. Thanks, Filippo