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a=openpgp; fpr=F43D03328115A198C90016883D200E9CA6329909 X-Developer-Signature: v=1; a=openpgp-sha256; l=2269; i=ardb@kernel.org; h=from:subject; bh=JUc6v0P1teNo8OlbdRyY2etIOH20xoIr68pdPx7aM1A=; b=owGbwMvMwCVmkMcZplerG8N4Wi2JIetLuBK718xmx/ypLhO8b639fiw/YoMK26dtJRWz97G1P e3qm9vfUcrCIMbFICumyCIw+++7nacnStU6z5KFmcPKBDKEgYtTACaSkcnI8PLL3UxDlVkHL3VV eYfd1ty9yDx39+JDbeVdgWsM/GT4LjMytE98yxv86sDjaf+WxKw843a1NVN31j8lu8f3s+fL8wj +5gAA X-Mailer: git-send-email 2.56.0.611.g1030f0b940-goog Message-ID: <20261111115303.3749380-11-ardb+git@google.com> Subject: [PATCH 2/7] arm64: dts: qcom: c630: Use LN_BB_CLK2 as the eDP bridge reference clock From: Ard Biesheuvel To: linux-arm-kernel@lists.infradead.org Cc: Ard Biesheuvel , Bjorn Andersson , Konrad Dybcio , Abel Vesa , Dmitry Baryshkov , linux-arm-msm@vger.kernel.org Content-Type: text/plain; charset="UTF-8" From: Ard Biesheuvel The SN65DSI86 eDP bridge on the Yoga C630 is described as being clocked by an always-on fixed 19.2 MHz reference clock. However, as on the SDM845 reference design (Cheza), its REFCLK appears to be fed by the LN_BB_CLK2 output of the PMIC, which also serves as the master clock of the WCD9340 audio codec. As nothing tells Linux that the bridge depends on LN_BB_CLK2, the clock only runs when the codec happens to have it enabled, and the WCD934x driver only enables it on demand. If the bridge is brought up while LN_BB_CLK2 is off or being toggled, e.g., when the display stack probes before the codec, or while the codec is being initialized, all AUX transfers fail and the DP PLL does not lock, leaving the panel dark: ti_sn65dsi86 10-002c: Can't read lane count (-110); assuming 4 ti_sn65dsi86 10-002c: Can't read eDP rev (-110), assuming 1.1 ti_sn65dsi86 10-002c: Can't read max rate (-110); assuming 5.4 GHz ti_sn65dsi86 10-002c: DP_PLL_LOCK polling failed (-110) So describe the actual clock instead, so that the bridge driver keeps it enabled for as long as the bridge is powered up. Fixes: 956e9c85f47b ("arm64: dts: qcom: c630: Define eDP bridge and panel") Signed-off-by: Ard Biesheuvel --- arch/arm64/boot/dts/qcom/sdm850-lenovo-yoga-c630.dts | 9 +-------- 1 file changed, 1 insertion(+), 8 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sdm850-lenovo-yoga-c630.dts b/arch/arm64/boot/dts/qcom/sdm850-lenovo-yoga-c630.dts index 9d38ae83c979..a4a573ea7e4a 100644 --- a/arch/arm64/boot/dts/qcom/sdm850-lenovo-yoga-c630.dts +++ b/arch/arm64/boot/dts/qcom/sdm850-lenovo-yoga-c630.dts @@ -97,13 +97,6 @@ sw_edp_1p2: edp-1p2-regulator { vin-supply = <&vreg_l2a_1p2>; }; - sn65dsi86_refclk: sn65dsi86-refclk { - compatible = "fixed-clock"; - #clock-cells = <0>; - - clock-frequency = <19200000>; - }; - vph_pwr: regulator-vph-pwr { compatible = "regulator-fixed"; regulator-name = "vph_pwr"; @@ -528,7 +521,7 @@ sn65dsi86: bridge@2c { vpll-supply = <&vreg_l14a_1p88>; vccio-supply = <&vreg_l14a_1p88>; - clocks = <&sn65dsi86_refclk>; + clocks = <&rpmhcc RPMH_LN_BB_CLK2>; clock-names = "refclk"; no-hpd; -- 2.56.0.611.g1030f0b940-goog