From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id AC0B123BF; Tue, 30 Apr 2024 00:21:08 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1714436468; cv=none; b=ojBneGOBy/msLCeBGh7F7JIlY0VQQpcM/4zd4GuOFJpmYTXqj+KJBFN8PW4AISIFFjH6x6T0PIvVuCxvLZr5VNll2L4/chXID7ZfPa8utxjyA/VfSc46uwa6u8gnxX2sByd3wC1VObcOsg1U0k0JYzeJ4r0n1OVoIYTgpriIMi8= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1714436468; c=relaxed/simple; bh=vlpQOh3I0nRLmsmE2sfzifRilau6eMr9R/cCdFVWVvw=; h=Message-ID:Content-Type:MIME-Version:In-Reply-To:References: Subject:From:Cc:To:Date; b=L/K0EK+Vqan2bk9utNDqNOMVwbYiz77fsOCrPIVafO8T5q6C63HLiU8iCfbjKppB38+KFMXq2xSgDrJoqjj90dfuN9mEuAJpsEwBUGm0jC//YOeddFRRqRONrFGMqig7ChuYwSi+D/K3yeooA1+lfKV+3jT3ocum4iimIYcGuyQ= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=RuR8Lu8F; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="RuR8Lu8F" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 3ACA5C113CD; Tue, 30 Apr 2024 00:21:08 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1714436468; bh=vlpQOh3I0nRLmsmE2sfzifRilau6eMr9R/cCdFVWVvw=; h=In-Reply-To:References:Subject:From:Cc:To:Date:From; b=RuR8Lu8FAED0ze/b1ZKh9hLN2nu51tNlCYAX+TAeqyl5lpYzCUQvrsPWYKWJHQ9t3 bH7Ky5OPllF5eInAshHMCCY1SDn+n152wLaYN7eWniabGSn2PgAMj5QeSfdsxhfCRD a+3ytue7JQ+Th57QCN+Zo86TOFIVlbbizaT4QBcqo/ICQmX09lB+Y4O4zcvPL2CrlP NKN3vizSmZhtrfM+q5k3tJFzcdfsM5zx86jfAZ6jbp9m/iukHxorVeA5JzlThjNCAT P4J0iRnAuqFD0dlpowj4OaFEtcO8QO7mDZBcjoFPagqR0ne+RnME2zn29WnRFXShBs yCrPFZVg6XGtg== Message-ID: <2337ba58adb3fb127710bead9b8665a9.sboyd@kernel.org> Content-Type: text/plain; charset="utf-8" Precedence: bulk X-Mailing-List: linux-arm-msm@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable In-Reply-To: <20240427-topic-8450sdc2-v1-1-631cbb59e0e5@linaro.org> References: <20240427-topic-8450sdc2-v1-1-631cbb59e0e5@linaro.org> Subject: Re: [PATCH] clk: qcom: gcc-sm8450: set OPS_PARENT_ENABLE on gcc_sdcc2_apps_clk_src From: Stephen Boyd Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, Dmitry Baryshkov , Konrad Dybcio To: Bjorn Andersson , Konrad Dybcio , Michael Turquette , Vinod Koul Date: Mon, 29 Apr 2024 17:21:05 -0700 User-Agent: alot/0.10 Quoting Konrad Dybcio (2024-04-27 05:01:07) > Similar to how it works on other SoCs, the top frequency of the SDHCI2 > core clock is generated by a separate PLL (peculiar design choice) that > is not guaranteed to be enabled (why does the clock framework not handle > this by default?). >=20 > Add the CLK_OPS_PARENT_ENABLE flag to make sure we're not muxing the > RCG input to a dormant source. The RCG2 hardware hasn't required the parent to be enabled for clk operations besides for the glitch-free source switch. What scenario is happening here that's requiring this flag? Is the RCG forcibly enabled perhaps because the bootloader has left the root enable bit set (CMD_ROOT_EN)? Or are we changing the parent while the clk framework thinks the clk is off when it is actually on? TL;DR: This is papering over a bigger bug.